diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/.DS_Store b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/.DS_Store
new file mode 100755
index 0000000000000000000000000000000000000000..d1231f515b7a20c26b1cfe594cd9b11016e139f1
Binary files /dev/null and b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/.DS_Store differ
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.atsln b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.atsln
new file mode 100755
index 0000000000000000000000000000000000000000..9a1d3d8b6f4dde29ddea7d462a6e1425a7cfd64b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.atsln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Atmel Studio Solution File, Format Version 11.00
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Bootloader_Sofia", "Bootloader_Sofia.cproj", "{7ABD2862-543D-4184-845E-8DC3E340E2CC}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|ARM = Debug|ARM
+ Release|ARM = Release|ARM
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {7ABD2862-543D-4184-845E-8DC3E340E2CC}.Debug|ARM.ActiveCfg = Debug|ARM
+ {7ABD2862-543D-4184-845E-8DC3E340E2CC}.Debug|ARM.Build.0 = Debug|ARM
+ {7ABD2862-543D-4184-845E-8DC3E340E2CC}.Release|ARM.ActiveCfg = Release|ARM
+ {7ABD2862-543D-4184-845E-8DC3E340E2CC}.Release|ARM.Build.0 = Release|ARM
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.atsuo b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.atsuo
new file mode 100755
index 0000000000000000000000000000000000000000..fe9a97402f6ec455e279c3ba7feae4cf34de45c7
Binary files /dev/null and b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.atsuo differ
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.cproj b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.cproj
new file mode 100755
index 0000000000000000000000000000000000000000..ca46b3f6792367f8e9323505657b40e60be34139
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/Bootloader_Sofia.cproj
@@ -0,0 +1,1089 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <PropertyGroup>
+ <SchemaVersion>2.0</SchemaVersion>
+ <ProjectVersion>6.2</ProjectVersion>
+ <ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
+ <ProjectGuid>{7abd2862-543d-4184-845e-8dc3e340e2cc}</ProjectGuid>
+ <avrdevice>ATSAMD21G18A</avrdevice>
+ <avrdeviceseries>samd21</avrdeviceseries>
+ <OutputType>Executable</OutputType>
+ <Language>C</Language>
+ <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+ <OutputFileExtension>.elf</OutputFileExtension>
+ <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+ <AssemblyName>bootloader_stk500v2_beta</AssemblyName>
+ <Name>Bootloader_Sofia</Name>
+ <RootNamespace>bootloader_stk500v2_beta</RootNamespace>
+ <ToolchainFlavour>Native</ToolchainFlavour>
+ <KeepTimersRunning>true</KeepTimersRunning>
+ <OverrideVtor>false</OverrideVtor>
+ <CacheFlash>true</CacheFlash>
+ <ProgFlashFromRam>true</ProgFlashFromRam>
+ <RamSnippetAddress>0x20000000</RamSnippetAddress>
+ <UncachedRange />
+ <OverrideVtorValue>exception_table</OverrideVtorValue>
+ <BootSegment>2</BootSegment>
+ <eraseonlaunchrule>0</eraseonlaunchrule>
+ <AsfFrameworkConfig>
+ <framework-data>
+ <options>
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="common.services.usb.class.device" value="Add" config="cdc" content-id="Atmel.ASF" />
+ <option id="sam0.drivers.extint" value="Add" config="callback" content-id="Atmel.ASF" />
+ <option id="sam0.drivers.nvm" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="sam0.drivers.port" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="sam0.drivers.rtc" value="Add" config="count_callback" content-id="Atmel.ASF" />
+ <option id="sam0.drivers.system" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="sam0.drivers.sercom.usart" value="Add" config="polled" content-id="Atmel.ASF" />
+ <option id="common.applications.user_application.xplained_pro2" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="common.utils" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="sam0.utils.cmsis.samd21.source.template" value="Add" config="" content-id="Atmel.ASF" />
+ </options>
+ <configurations>
+ <configuration key="config.sam0.drivers.extint" value="callback" default="callback" content-id="Atmel.ASF" />
+ </configurations>
+ <files>
+ <file path="src/main.c" framework="" version="" source="common2/applications/xplained_pro_user_application/main.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/config/conf_board.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config/conf_board.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/config/conf_clocks.h" framework="" version="" source="common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config/conf_clocks.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/boards/board.h" framework="" version="" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/utils/interrupt.h" framework="" version="" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/utils/parts.h" framework="" version="" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/boards/samd21_xplained_pro/board_init.c" framework="" version="" source="sam0/boards/samd21_xplained_pro/board_init.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h" framework="" version="" source="sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/port/port.c" framework="" version="" source="sam0/drivers/port/port.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/port/port.h" framework="" version="" source="sam0/drivers/port/port.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h" framework="" version="" source="sam0/drivers/port/quick_start/qs_port_basic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/clock.h" framework="" version="" source="sam0/drivers/system/clock/clock.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock.c" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21/clock.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock_config_check.h" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21/clock_config_check.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/clock_samd21_r21/gclk.c" framework="" version="" source="sam0/drivers/system/clock/clock_samd21_r21/gclk.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/gclk.h" framework="" version="" source="sam0/drivers/system/clock/gclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h" framework="" version="" source="sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h" framework="" version="" source="sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h" framework="" version="" source="sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.c" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h" framework="" version="" source="sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.c" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/pinmux/pinmux.h" framework="" version="" source="sam0/drivers/system/pinmux/pinmux.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" framework="" version="" source="sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/system.c" framework="" version="" source="sam0/drivers/system/system.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/system/system.h" framework="" version="" source="sam0/drivers/system/system.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/ac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/adc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dmac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/dsu.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/eic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/evsys.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/gclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/i2s.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/mtb.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/nvmctrl.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/pm.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/port.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/port.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/rtc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/sercom.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/sysctrl.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/tcc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/usb.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/component/wdt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/ac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/adc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dmac.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/dsu.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/eic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/evsys.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/gclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/i2s.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/mtb.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/nvmctrl.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pac2.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/pm.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/port.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/rtc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom2.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom3.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom4.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sercom5.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/sysctrl.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc3.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc4.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc5.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc6.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tc7.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tcc0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tcc1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/tcc2.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/usb.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/instance/wdt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21e15a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21e16a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21e17a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21e18a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21g15a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21g16a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21g17a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21g18a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21j15a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21j16a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21j17a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/pio/samd21j18a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21e15a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21e16a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21e17a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21e18a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21g15a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21g16a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21g17a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21g18a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21j15a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21j16a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21j17a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h" framework="" version="" source="sam0/utils/cmsis/samd21/include/samd21j18a.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c" framework="" version="" source="sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c" framework="" version="" source="sam0/utils/cmsis/samd21/source/system_samd21.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h" framework="" version="" source="sam0/utils/cmsis/samd21/source/system_samd21.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/compiler.h" framework="" version="" source="sam0/utils/compiler.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/header_files/io.h" framework="" version="" source="sam0/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld" framework="" version="" source="sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/make/Makefile.sam.in" framework="" version="" source="sam0/utils/make/Makefile.sam.in" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/preprocessor/mrecursion.h" framework="" version="" source="sam0/utils/preprocessor/mrecursion.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/preprocessor/mrepeat.h" framework="" version="" source="sam0/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/preprocessor/preprocessor.h" framework="" version="" source="sam0/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/preprocessor/stringz.h" framework="" version="" source="sam0/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/preprocessor/tpaste.h" framework="" version="" source="sam0/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/status_codes.h" framework="" version="" source="sam0/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/utils/syscalls/gcc/syscalls.c" framework="" version="" source="sam0/utils/syscalls/gcc/syscalls.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" framework="" version="" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/Include/arm_math.h" framework="" version="" source="thirdparty/CMSIS/Include/arm_math.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h" framework="" version="" source="thirdparty/CMSIS/Include/core_cm0plus.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h" framework="" version="" source="thirdparty/CMSIS/Include/core_cmFunc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h" framework="" version="" source="thirdparty/CMSIS/Include/core_cmInstr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a" framework="" version="" source="thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/README.txt" framework="" version="" source="thirdparty/CMSIS/README.txt" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/thirdparty/CMSIS/license.txt" framework="" version="" source="thirdparty/CMSIS/license.txt" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/sleepmgr/samd/sleepmgr.c" framework="" version="3.19.0" source="common\services\sleepmgr\samd\sleepmgr.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/sleepmgr/sleepmgr.h" framework="" version="3.19.0" source="common\services\sleepmgr\sleepmgr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/sleepmgr/samd/sleepmgr.h" framework="" version="3.19.0" source="common\services\sleepmgr\samd\sleepmgr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/Config/conf_sleepmgr.h" framework="" version="3.19.0" source="common\services\sleepmgr\samd\module_config\conf_sleepmgr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/usb_atmel.h" framework="" version="3.19.0" source="common\services\usb\usb_atmel.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/usb_protocol.h" framework="" version="3.19.0" source="common\services\usb\usb_protocol.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h" framework="" version="3.19.0" source="common\services\usb\class\cdc\usb_protocol_cdc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/class/cdc/device/udi_cdc.c" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\udi_cdc.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\udi_cdc_desc.c" changed="False" content-id="Atmel.ASF" />
+ <file path="atmel_devices_cdc.cat" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\atmel_devices_cdc.cat" changed="False" content-id="Atmel.ASF" />
+ <file path="atmel_devices_cdc.inf" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\atmel_devices_cdc.inf" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/class/cdc/device/udi_cdc.h" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\udi_cdc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\udi_cdc_conf.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/Config/conf_usb.h" framework="" version="3.19.0" source="common\services\usb\class\cdc\device\module_config\conf_usb.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/udc/udc.c" framework="" version="3.19.0" source="common\services\usb\udc\udc.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/udc/udc.h" framework="" version="3.19.0" source="common\services\usb\udc\udc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/udc/udd.h" framework="" version="3.19.0" source="common\services\usb\udc\udd.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/udc/udc_desc.h" framework="" version="3.19.0" source="common\services\usb\udc\udc_desc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/common/services/usb/udc/udi.h" framework="" version="3.19.0" source="common\services\usb\udc\udi.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/extint/extint_callback.c" framework="" version="3.19.0" source="sam0\drivers\extint\extint_callback.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/extint/extint.c" framework="" version="3.19.0" source="sam0\drivers\extint\extint.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/extint/extint_callback.h" framework="" version="3.19.0" source="sam0\drivers\extint\extint_callback.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/extint/extint.h" framework="" version="3.19.0" source="sam0\drivers\extint\extint.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/Config/conf_extint.h" framework="" version="3.19.0" source="sam0\drivers\extint\module_config\conf_extint.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/usb/usb.c" framework="" version="3.19.0" source="sam0\drivers\usb\usb.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/usb/usb.h" framework="" version="3.19.0" source="sam0\drivers\usb\usb.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/usb/stack_interface/usb_dual.c" framework="" version="3.19.0" source="sam0\drivers\usb\stack_interface\usb_dual.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/usb/stack_interface/usb_dual.h" framework="" version="3.19.0" source="sam0\drivers\usb\stack_interface\usb_dual.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/usb/stack_interface/usb_device_udd.c" framework="" version="3.19.0" source="sam0\drivers\usb\stack_interface\usb_device_udd.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/nvm/nvm.c" framework="" version="3.19.0" source="sam0\drivers\nvm\nvm.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/nvm/quick_start_basic/qs_nvm_basic.h" framework="" version="3.19.0" source="sam0\drivers\nvm\quick_start_basic\qs_nvm_basic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/nvm/nvm.h" framework="" version="3.19.0" source="sam0\drivers\nvm\nvm.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/rtc/rtc_count.c" framework="" version="3.19.0" source="sam0\drivers\rtc\rtc_count.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/rtc/rtc_count_interrupt.c" framework="" version="3.19.0" source="sam0\drivers\rtc\rtc_count_interrupt.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/rtc/quick_start_count_callback/qs_rtc_count_callback.h" framework="" version="3.19.0" source="sam0\drivers\rtc\quick_start_count_callback\qs_rtc_count_callback.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/rtc/quick_start_count/qs_rtc_count_basic.h" framework="" version="3.19.0" source="sam0\drivers\rtc\quick_start_count\qs_rtc_count_basic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/rtc/rtc_count.h" framework="" version="3.19.0" source="sam0\drivers\rtc\rtc_count.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/rtc/rtc_count_interrupt.h" framework="" version="3.19.0" source="sam0\drivers\rtc\rtc_count_interrupt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/sercom_interrupt.c" framework="" version="3.19.0" source="sam0\drivers\sercom\sercom_interrupt.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/sercom.c" framework="" version="3.19.0" source="sam0\drivers\sercom\sercom.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/sercom_interrupt.h" framework="" version="3.19.0" source="sam0\drivers\sercom\sercom_interrupt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/sercom_pinout.h" framework="" version="3.19.0" source="sam0\drivers\sercom\sercom_pinout.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/sercom.h" framework="" version="3.19.0" source="sam0\drivers\sercom\sercom.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/usart/usart.c" framework="" version="3.19.0" source="sam0\drivers\sercom\usart\usart.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h" framework="" version="3.19.0" source="sam0\drivers\sercom\usart\quick_start\qs_usart_basic_use.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/usart/usart.h" framework="" version="3.19.0" source="sam0\drivers\sercom\usart\usart.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h" framework="" version="3.19.0" source="sam0\drivers\sercom\usart\quick_start_dma\qs_usart_dma_use.h" changed="False" content-id="Atmel.ASF" />
+ </files>
+ <documentation help="http://asf.atmel.com/docs/3.19.0/common.applications.user_application.xplained_pro2.samd21_xplained_pro/html/index.html" />
+ <offline-documentation help="" />
+ <dependencies>
+ <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.19.0" />
+ </dependencies>
+ <project id="common.applications.user_application.xplained_pro2.samd21_xplained_pro" value="Add" config="" content-id="Atmel.ASF" />
+ <board id="board.samd21_xplained_pro" value="Add" config="" content-id="Atmel.ASF" />
+ </framework-data>
+ </AsfFrameworkConfig>
+ <avrtool>com.atmel.avrdbg.tool.edbg</avrtool>
+ <avrtoolinterface>SWD</avrtoolinterface>
+ <com_atmel_avrdbg_tool_edbg>
+ <ToolOptions>
+ <InterfaceProperties>
+ <SwdClock>2000000</SwdClock>
+ </InterfaceProperties>
+ <InterfaceName>SWD</InterfaceName>
+ </ToolOptions>
+ <ToolType>com.atmel.avrdbg.tool.edbg</ToolType>
+ <ToolNumber>FFFFFFFFFFFFFFFFFFFF</ToolNumber>
+ <ToolName>EDBG</ToolName>
+ </com_atmel_avrdbg_tool_edbg>
+ <preserveEEPROM>true</preserveEEPROM>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+ <ToolchainSettings>
+ <ArmGcc>
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>NDEBUG</Value>
+ <Value>BOARD=SAMD21_XPLAINED_PRO</Value>
+ <Value>__SAMD21J18A__</Value>
+ <Value>ARM_MATH_CM0=true</Value>
+ <Value>USB_DEVICE_LPM_SUPPORT</Value>
+ <Value>UDD_ENABLE</Value>
+ <Value>EXTINT_CALLBACK_MODE=true</Value>
+ <Value>RTC_COUNT_ASYNC=true</Value>
+ <Value>USART_CALLBACK_MODE=false</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>../common2/applications/xplained_pro_user_application/samd21j18a_samd21_xplained_pro/config</Value>
+ <Value>../src/ASF/sam0/utils/header_files</Value>
+ <Value>../src/ASF/thirdparty/CMSIS/Lib/GCC</Value>
+ <Value>../src/config</Value>
+ <Value>../src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21</Value>
+ <Value>../src/ASF/common/utils</Value>
+ <Value>../src/ASF/sam0/boards/samd21_xplained_pro</Value>
+ <Value>../src/ASF/sam0/drivers/system/pinmux</Value>
+ <Value>../src</Value>
+ <Value>../src/ASF/sam0/utils/preprocessor</Value>
+ <Value>../src/ASF/sam0/utils/cmsis/samd21/include</Value>
+ <Value>../src/ASF/sam0/drivers/system</Value>
+ <Value>../src/ASF/common/boards</Value>
+ <Value>../src/ASF/sam0/drivers/port</Value>
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+ <None Include="src\config\conf_usb.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\usb\class\cdc\device\udi_cdc_conf.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\usb\class\cdc\device\udi_cdc.h">
+ <SubType>compile</SubType>
+ </None>
+ <Compile Include="src\ASF\common\services\usb\class\cdc\device\udi_cdc_desc.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <None Include="atmel_devices_cdc.cat">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="atmel_devices_cdc.inf">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\usb\class\cdc\usb_protocol_cdc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\usb\usb_protocol.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\usb\usb_atmel.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\config\conf_sleepmgr.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\sleepmgr\samd\sleepmgr.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\services\sleepmgr\sleepmgr.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\asf.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\config\conf_board.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\config\conf_clocks.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\rtc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\interrupt\system_interrupt.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\boards\samd21_xplained_pro\samd21_xplained_pro.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\mtb.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\clock\clock.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\port.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tc7.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\i2s.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\linker_scripts\samd21\gcc\samd21j18a_flash.ld">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\make\Makefile.sam.in">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\thirdparty\CMSIS\CMSIS END USER LICENCE AGREEMENT.pdf">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\thirdparty\CMSIS\Include\arm_math.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\system.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21g18a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\gclk.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\usb.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21g15a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21g16a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21g17a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21g18a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\preprocessor\mrepeat.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\interrupt\system_interrupt_samd21\system_interrupt_features.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\rtc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\pm.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\dac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sercom5.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21g16a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sercom0.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21g17a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21g15a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\gclk.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\pac2.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\pac1.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\pac0.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\eic.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\pm.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tcc2.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tcc1.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tcc0.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\adc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\preprocessor\preprocessor.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tc5.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\sysctrl.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cmFunc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\evsys.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\wdt.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\clock\quick_start_gclk\qs_gclk_basic.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\ac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sercom3.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\evsys.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\boards\board.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21j15a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\clock\quick_start_clock\qs_clock_source.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21j16a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21j17a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21j18a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sysctrl.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\nvmctrl.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\preprocessor\stringz.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\usb.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cmInstr.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\adc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21j18a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\nvmctrl.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\status_codes.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21j16a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21j17a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\dsu.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21j15a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\mtb.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\pinmux\pinmux.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sercom1.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\dsu.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\dmac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\i2s.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tc3.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\tc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21e18a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\header_files\io.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tc6.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\clock\clock_samd21_r21\clock_config_check.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\preprocessor\mrecursion.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\compiler.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21e15a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21e16a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21e17a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\pio\samd21e18a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\sercom.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\utils\parts.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21e16a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\port.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\dmac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21e17a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\pac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21e15a.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sercom4.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\samd21.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cm0plus.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\port\quick_start\qs_port_basic.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\utils\interrupt.h">
+ <SubType>compile</SubType>
+ </None>
+ <Compile Include="src\ASF\common\utils\interrupt\interrupt_sam_nvic.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <None Include="src\ASF\sam0\drivers\port\port.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\wdt.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\eic.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\pinmux\quick_start\qs_pinmux_basic.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\interrupt\quick_start\qs_system_interrupt.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\tc4.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\dac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\ac.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\drivers\system\clock\gclk.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\preprocessor\tpaste.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\instance\sercom2.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\sam0\utils\cmsis\samd21\include\component\tcc.h">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\common\utils\interrupt\interrupt_sam_nvic.h">
+ <SubType>compile</SubType>
+ </None>
+ <Compile Include="src\ASF\sam0\boards\samd21_xplained_pro\board_init.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\drivers\port\port.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\drivers\system\clock\clock_samd21_r21\clock.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\drivers\system\clock\clock_samd21_r21\gclk.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\drivers\system\interrupt\system_interrupt.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\drivers\system\pinmux\pinmux.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\drivers\system\system.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\utils\cmsis\samd21\source\gcc\startup_samd21.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\utils\cmsis\samd21\source\system_samd21.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\ASF\sam0\utils\syscalls\gcc\syscalls.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\main.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <None Include="src\ASF\thirdparty\CMSIS\Lib\GCC\libarm_cortexM0l_math.a">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="src\ASF\thirdparty\CMSIS\README.txt">
+ <SubType>compile</SubType>
+ </None>
+ </ItemGroup>
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/atmel_devices_cdc.cat b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/atmel_devices_cdc.cat
new file mode 100755
index 0000000000000000000000000000000000000000..09a0673b21a5966e0404eaad5d83ab5a3ca57a95
Binary files /dev/null and b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/atmel_devices_cdc.cat differ
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/atmel_devices_cdc.inf b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/atmel_devices_cdc.inf
new file mode 100755
index 0000000000000000000000000000000000000000..d2df608e6b8d7b3c942923cd2534113fcd56db89
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/atmel_devices_cdc.inf
@@ -0,0 +1,182 @@
+; Windows 2000, XP, Vista, 7 and 8 (x32 and x64) setup file for Atmel CDC Devices
+; Copyright (c) 2000-2013 ATMEL, Inc.
+
+[Version]
+Signature = "$Windows NT$"
+Class = Ports
+ClassGuid = {4D36E978-E325-11CE-BFC1-08002BE10318}
+
+Provider = %Manufacturer%
+LayoutFile = layout.inf
+CatalogFile = atmel_devices_cdc.cat
+DriverVer = 01/08/2013,6.0.0.0
+
+;----------------------------------------------------------
+; Targets
+;----------------------------------------------------------
+[Manufacturer]
+%Manufacturer%=DeviceList, NTAMD64, NTIA64, NT
+
+[DeviceList]
+%ATMEL_CDC_XPLAINED%=DriverInstall, USB\VID_03EB&PID_2122
+%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall, USB\VID_03EB&PID_214B
+%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall, USB\VID_03EB&PID_214A
+%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2307
+%ATMEL_CDC_EVK1XXX%=DriverInstall, USB\VID_03EB&PID_2310
+%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2404
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall, USB\VID_03EB&PID_2421&MI_00
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall, USB\VID_03EB&PID_2424&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall, USB\VID_03EB&PID_2425&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall, USB\VID_03EB&PID_2425&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall, USB\VID_03EB&PID_2426&MI_00
+%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall, USB\VID_03EB&PID_2426&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall, USB\VID_03EB&PID_2426&MI_04
+%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall, USB\VID_03EB&PID_2426&MI_06
+%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall, USB\VID_03EB&PID_2426&MI_08
+%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall, USB\VID_03EB&PID_2426&MI_0A
+%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall, USB\VID_03EB&PID_2426&MI_0C
+
+[DeviceList.NTAMD64]
+%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122
+%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B
+%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A
+%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307
+%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310
+%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00
+%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04
+%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06
+%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08
+%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A
+%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C
+
+[DeviceList.NTIA64]
+%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122
+%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B
+%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A
+%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307
+%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310
+%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00
+%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04
+%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06
+%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08
+%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A
+%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C
+
+[DeviceList.NT]
+%ATMEL_CDC_XPLAINED%=DriverInstall.NT, USB\VID_03EB&PID_2122
+%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NT, USB\VID_03EB&PID_214B
+%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NT, USB\VID_03EB&PID_214A
+%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2307
+%ATMEL_CDC_EVK1XXX%=DriverInstall.NT, USB\VID_03EB&PID_2310
+%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2404
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NT, USB\VID_03EB&PID_2421&MI_00
+%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NT, USB\VID_03EB&PID_2424&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_00
+%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_00
+%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_02
+%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_04
+%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_06
+%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_08
+%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0A
+%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0C
+
+;----------------------------------------------------------
+; Windows 2000, XP, Vista, Windows 7, Windows 8 - 32bit
+;----------------------------------------------------------
+[Reader_Install.NTx86]
+
+
+[DestinationDirs]
+DefaultDestDir=12
+DriverInstall.NT.Copy=12
+
+[DriverInstall.NT]
+include=mdmcpq.inf
+CopyFiles=DriverInstall.NT.Copy
+AddReg=DriverInstall.NT.AddReg
+
+[DriverInstall.NT.Copy]
+usbser.sys
+
+[DriverInstall.NT.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NT.Services]
+AddService = usbser, 0x00000002, DriverService.NT
+
+[DriverService.NT]
+DisplayName = %Serial.SvcDesc%
+ServiceType = 1 ; SERVICE_KERNEL_DRIVER
+StartType = 3 ; SERVICE_DEMAND_START
+ErrorControl = 1 ; SERVICE_ERROR_NORMAL
+ServiceBinary = %12%\usbser.sys
+LoadOrderGroup = Base
+
+;----------------------------------------------------------
+; Windows XP, Vista, Windows 7, Windows 8 - 64bit
+;----------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.NTamd64
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverCopyFiles.NTamd64]
+usbser.sys,,,0x20
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%Serial.SvcDesc%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\usbser.sys
+
+;----------------------------------------------------------
+; String
+;----------------------------------------------------------
+
+[Strings]
+Manufacturer = "ATMEL, Inc."
+ATMEL_CDC_XPLAINED = "XPLAINED Virtual Com Port"
+ATMEL_CDC_USB_ZIGBIT_Sub = "ZigBit SubGHz USBstick Com Port"
+ATMEL_CDC_USB_ZIGBIT_2_4 = "ZigBit 2.4GHz USBstick Com Port"
+ATMEL_CDC_SFW_EXAMPLE = "Communication Device Class SFW example"
+ATMEL_CDC_EVK1XXX = "EVK1XXX Virtual Com Port"
+ATMEL_CDC_ASF_EXAMPLE = "Communication Device Class ASF example"
+ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2 = "Communication Device Class ASF composite example 2"
+ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4 = "Communication Device Class ASF composite example 4"
+ATMEL_CDC_ASF_EXAMPLE2_COM1 = "Communication Device Class ASF example2, COM1"
+ATMEL_CDC_ASF_EXAMPLE2_COM2 = "Communication Device Class ASF example2, COM2"
+ATMEL_CDC_ASF_EXAMPLE3_COM1 = "Communication Device Class ASF example3, COM1"
+ATMEL_CDC_ASF_EXAMPLE3_COM2 = "Communication Device Class ASF example3, COM2"
+ATMEL_CDC_ASF_EXAMPLE3_COM3 = "Communication Device Class ASF example3, COM3"
+ATMEL_CDC_ASF_EXAMPLE3_COM4 = "Communication Device Class ASF example3, COM4"
+ATMEL_CDC_ASF_EXAMPLE3_COM5 = "Communication Device Class ASF example3, COM5"
+ATMEL_CDC_ASF_EXAMPLE3_COM6 = "Communication Device Class ASF example3, COM6"
+ATMEL_CDC_ASF_EXAMPLE3_COM7 = "Communication Device Class ASF example3, COM7"
+
+Serial.SvcDesc = "USB Serial emulation driver"
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/.DS_Store b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/.DS_Store
new file mode 100755
index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6
Binary files /dev/null and b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/.DS_Store differ
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/boards/board.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/boards/board.h
new file mode 100755
index 0000000000000000000000000000000000000000..729d94cdd227a72e6d6c820916f1fb64900e2999
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/boards/board.h
@@ -0,0 +1,383 @@
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.
+#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
+#define UC3L_EK 7 //!< AT32UC3L-EK board.
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board
+#define SAM3S_EK 32 //!< SAM3S-EK board.
+#define SAM3U_EK 33 //!< SAM3U-EK board.
+#define SAM3X_EK 34 //!< SAM3X-EK board.
+#define SAM3N_EK 35 //!< SAM3N-EK board.
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
+#define SAM4S_EK 37 //!< SAM4S-EK board.
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
+#define STK600_MEGA 39 //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board
+#define SAM4L_EK 45 //!< SAM4L-EK board.
+#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK 51 //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit
+#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit
+#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit
+#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board
+#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB
+#define SAM4C_EK 64 //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
+#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
+#define ATPL230AMB 73 //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices
+#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD 99 //!< User-reserved board (if any).
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102 1 //!< AT32UC3B EXT1102 board
+#define MC300 2 //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+# include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+# include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+# include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+# include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+# include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+# include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+# include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+ /*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+# include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+# include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+# include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+# include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+# include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+# include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+# include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+# include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+# include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+# include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+# include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+# include "sam3s_ek/sam3s_ek.h"
+# include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+# include "sam3s_ek2/sam3s_ek2.h"
+# include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+# include "sam3u_ek/sam3u_ek.h"
+# include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+# include "sam3x_ek/sam3x_ek.h"
+# include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+# include "sam3n_ek/sam3n_ek.h"
+# include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+# include "sam4s_ek/sam4s_ek.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+# include "sam4s_xplained/sam4s_xplained.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+# include "sam4s_ek2/sam4s_ek2.h"
+# include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+ /*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+# include "arduino_due_x/arduino_due_x.h"
+# include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+# include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+# include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+# include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+# include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+# include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+# include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+# include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+# include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+# include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+# include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+# include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+# include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+# include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+# include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+# include "atpl230amb/atpl230amb.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+# include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+# include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+# include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+# include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == USER_BOARD
+ // User-reserved area: #include the header file of your board here (if any).
+# include "user_board.h"
+#elif BOARD == DUMMY_BOARD
+# include "dummy/dummy_board.h"
+#else
+# error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+# if EXT_BOARD == MC300
+# include "mc300/mc300.h"
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+# include "sensors_xplained/sensors_xplained.h"
+# elif EXT_BOARD == RZ600_AT86RF231
+# include "at86rf231/at86rf231.h"
+# elif EXT_BOARD == RZ600_AT86RF230B
+# include "at86rf230b/at86rf230b.h"
+# elif EXT_BOARD == RZ600_AT86RF212
+# include "at86rf212/at86rf212.h"
+# elif EXT_BOARD == SECURITY_XPLAINED
+# include "security_xplained.h"
+# elif EXT_BOARD == USER_EXT_BOARD
+ // User-reserved area: #include the header file of your extension board here
+ // (if any).
+# endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif // _BOARD_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/samd/sleepmgr.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/samd/sleepmgr.c
new file mode 100755
index 0000000000000000000000000000000000000000..2ad360c447227abe0e17ed2d6b4b8b44b98f6995
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/samd/sleepmgr.c
@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <sleepmgr.h>
+
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+
+uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES];
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/samd/sleepmgr.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/samd/sleepmgr.h
new file mode 100755
index 0000000000000000000000000000000000000000..261e1da19a0f4068dc5f4d36e25f1ef192741394
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/samd/sleepmgr.h
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SAM_SLEEPMGR_INCLUDED
+#define SAM_SLEEPMGR_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <conf_sleepmgr.h>
+#include <interrupt.h>
+#include "system.h"
+
+/**
+ * \weakgroup sleepmgr_group
+ * @{
+ */
+
+enum sleepmgr_mode {
+ /** Active mode. */
+ SLEEPMGR_ACTIVE = 0,
+
+ /**
+ * Idle 0 mode.
+ * Potential Wake Up sources: Synchronous(APB, AHB), asynchronous.
+ */
+ SLEEPMGR_IDLE_0,
+
+ /**
+ * Idle 1 mode.
+ * Potential Wake Up sources: Synchronous (APB), asynchronous
+ */
+ SLEEPMGR_IDLE_1,
+
+ /**
+ * Idle 2 mode.
+ * Potential Wake Up sources: Asynchronous
+ */
+ SLEEPMGR_IDLE_2,
+
+ /**
+ * Standby mode.
+ * Potential Wake Up sources: Asynchronous
+ */
+ SLEEPMGR_STANDBY,
+
+ SLEEPMGR_NR_OF_MODES,
+};
+
+/**
+ * \internal
+ * \name Internal arrays
+ * @{
+ */
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+/** Sleep mode lock counters */
+extern uint8_t sleepmgr_locks[];
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+/** @} */
+
+static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
+{
+ Assert(sleep_mode != SLEEPMGR_ACTIVE);
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ cpu_irq_disable();
+
+ /* Enter the sleep mode. */
+ system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1));
+ cpu_irq_enable();
+ system_sleep();
+#else
+ UNUSED(sleep_mode);
+ cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAM_SLEEPMGR_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/sleepmgr.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/sleepmgr.h
new file mode 100755
index 0000000000000000000000000000000000000000..2d64817428db85e0626e24efca016f21e7498b0a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/sleepmgr/sleepmgr.h
@@ -0,0 +1,256 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager
+ *
+ * Copyright (c) 2010 - 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SLEEPMGR_H
+#define SLEEPMGR_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
+# include "sam/sleepmgr.h"
+#elif XMEGA
+# include "xmega/sleepmgr.h"
+#elif UC3
+# include "uc3/sleepmgr.h"
+#elif SAM4L
+# include "sam4l/sleepmgr.h"
+#elif MEGA
+# include "mega/sleepmgr.h"
+#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11)
+# include "samd/sleepmgr.h"
+#else
+# error Unsupported device.
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup sleepmgr_group Sleep manager
+ *
+ * The sleep manager is a service for ensuring that the device is not put to
+ * sleep in deeper sleep modes than the system (e.g., peripheral drivers,
+ * services or the application) allows at any given time.
+ *
+ * It is based on the use of lock counting for the individual sleep modes, and
+ * will put the device to sleep in the shallowest sleep mode that has a non-zero
+ * lock count. The drivers/services/application can change these counts by use
+ * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode.
+ * Refer to \ref sleepmgr_mode for a list of the sleep modes available for
+ * locking, and the device datasheet for information on their effect.
+ *
+ * The application must supply the file \ref conf_sleepmgr.h.
+ *
+ * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE
+ * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not
+ * defined, the functions are replaced with dummy functions and no RAM is used.
+ *
+ * @{
+ */
+
+/**
+ * \def CONFIG_SLEEPMGR_ENABLE
+ * \brief Configuration symbol for enabling the sleep manager
+ *
+ * If this symbol is not defined, the functions of this service are replaced
+ * with dummy functions. This is useful for reducing code size and execution
+ * time if the sleep manager is not needed in the application.
+ *
+ * This symbol may be defined in \ref conf_sleepmgr.h.
+ */
+#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE)
+# define CONFIG_SLEEPMGR_ENABLE
+#endif
+
+/**
+ * \enum sleepmgr_mode
+ * \brief Sleep mode locks
+ *
+ * Identifiers for the different sleep mode locks.
+ */
+
+/**
+ * \brief Initialize the lock counts
+ *
+ * Sets all lock counts to 0, except the very last one, which is set to 1. This
+ * is done to simplify the algorithm for finding the deepest allowable sleep
+ * mode in \ref sleepmgr_enter_sleep.
+ */
+static inline void sleepmgr_init(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ uint8_t i;
+
+ for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) {
+ sleepmgr_locks[i] = 0;
+ }
+ sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Increase lock count for a sleep mode
+ *
+ * Increases the lock count for \a mode to ensure that the sleep manager does
+ * not put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to lock.
+ */
+static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ irqflags_t flags;
+
+ Assert(sleepmgr_locks[mode] < 0xff);
+
+ // Enter a critical section
+ flags = cpu_irq_save();
+
+ ++sleepmgr_locks[mode];
+
+ // Leave the critical section
+ cpu_irq_restore(flags);
+#else
+ UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Decrease lock count for a sleep mode
+ *
+ * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep
+ * manager can put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to unlock.
+ */
+static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ irqflags_t flags;
+
+ Assert(sleepmgr_locks[mode]);
+
+ // Enter a critical section
+ flags = cpu_irq_save();
+
+ --sleepmgr_locks[mode];
+
+ // Leave the critical section
+ cpu_irq_restore(flags);
+#else
+ UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+ /**
+ * \brief Retrieves the deepest allowable sleep mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The deepest allowable
+ * sleep mode is then returned.
+ */
+static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
+{
+ enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
+
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ uint8_t *lock_ptr = sleepmgr_locks;
+
+ // Find first non-zero lock count, starting with the shallowest modes.
+ while (!(*lock_ptr)) {
+ lock_ptr++;
+ sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
+ }
+
+ // Catch the case where one too many sleepmgr_unlock_mode() call has been
+ // performed on the deepest sleep mode.
+ Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+
+ return sleep_mode;
+}
+
+/**
+ * \fn sleepmgr_enter_sleep
+ * \brief Go to sleep in the deepest allowed mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The device is then put to
+ * sleep in the sleep mode that corresponds to the lock.
+ *
+ * \note This function enables interrupts before going to sleep, and will leave
+ * them enabled upon return. This also applies if sleep is skipped due to ACTIVE
+ * mode being locked.
+ */
+
+static inline void sleepmgr_enter_sleep(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ enum sleepmgr_mode sleep_mode;
+
+ cpu_irq_disable();
+
+ // Find the deepest allowable sleep mode
+ sleep_mode = sleepmgr_get_sleep_mode();
+ // Return right away if first mode (ACTIVE) is locked.
+ if (sleep_mode==SLEEPMGR_ACTIVE) {
+ cpu_irq_enable();
+ return;
+ }
+ // Enter the deepest allowable sleep mode with interrupts enabled
+ sleepmgr_sleep(sleep_mode);
+#else
+ cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SLEEPMGR_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc.c
new file mode 100755
index 0000000000000000000000000000000000000000..27a1724a6474e408266d4e9386715a1acef66c1e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc.c
@@ -0,0 +1,1100 @@
+/**
+ * \file
+ *
+ * \brief USB Device Communication Device Class (CDC) interface.
+ *
+ * Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "usb_protocol_cdc.h"
+#include "udd.h"
+#include "udc.h"
+#include "udi_cdc.h"
+#include <string.h>
+
+#ifdef UDI_CDC_LOW_RATE
+# ifdef USB_DEVICE_HS_SUPPORT
+# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
+# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
+# else
+# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE)
+# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE)
+# endif
+#else
+# ifdef USB_DEVICE_HS_SUPPORT
+# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
+# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE)
+# else
+# define UDI_CDC_TX_BUFFERS (5*UDI_CDC_DATA_EPS_FS_SIZE)
+# define UDI_CDC_RX_BUFFERS (5*UDI_CDC_DATA_EPS_FS_SIZE)
+# endif
+#endif
+
+#ifndef UDI_CDC_TX_EMPTY_NOTIFY
+# define UDI_CDC_TX_EMPTY_NOTIFY(port)
+#endif
+
+/**
+ * \ingroup udi_cdc_group
+ * \defgroup udi_cdc_group_udc Interface with USB Device Core (UDC)
+ *
+ * Structures and functions required by UDC.
+ *
+ * @{
+ */
+bool udi_cdc_comm_enable(void);
+void udi_cdc_comm_disable(void);
+bool udi_cdc_comm_setup(void);
+bool udi_cdc_data_enable(void);
+void udi_cdc_data_disable(void);
+bool udi_cdc_data_setup(void);
+uint8_t udi_cdc_getsetting(void);
+void udi_cdc_data_sof_notify(void);
+UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm = {
+ .enable = udi_cdc_comm_enable,
+ .disable = udi_cdc_comm_disable,
+ .setup = udi_cdc_comm_setup,
+ .getsetting = udi_cdc_getsetting,
+};
+UDC_DESC_STORAGE udi_api_t udi_api_cdc_data = {
+ .enable = udi_cdc_data_enable,
+ .disable = udi_cdc_data_disable,
+ .setup = udi_cdc_data_setup,
+ .getsetting = udi_cdc_getsetting,
+ .sof_notify = udi_cdc_data_sof_notify,
+};
+//@}
+
+/**
+ * \ingroup udi_cdc_group
+ * \defgroup udi_cdc_group_internal Implementation of UDI CDC
+ *
+ * Class internal implementation
+ * @{
+ */
+
+/**
+ * \name Internal routines
+ */
+//@{
+
+/**
+ * \name Routines to control serial line
+ */
+//@{
+
+/**
+ * \brief Returns the port number corresponding at current setup request
+ *
+ * \return port number
+ */
+static uint8_t udi_cdc_setup_to_port(void);
+
+/**
+ * \brief Sends line coding to application
+ *
+ * Called after SETUP request when line coding data is received.
+ */
+static void udi_cdc_line_coding_received(void);
+
+/**
+ * \brief Records new state
+ *
+ * \param port Communication port number to manage
+ * \param b_set State is enabled if true, else disabled
+ * \param bit_mask Field to process (see CDC_SERIAL_STATE_ defines)
+ */
+static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask);
+
+/**
+ * \brief Check and eventually notify the USB host of new state
+ *
+ * \param port Communication port number to manage
+ * \param ep Port communication endpoint
+ */
+static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep);
+
+/**
+ * \brief Ack sent of serial state message
+ * Callback called after serial state message sent
+ *
+ * \param status UDD_EP_TRANSFER_OK, if transfer finished
+ * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted
+ * \param n number of data transfered
+ */
+static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep);
+
+//@}
+
+/**
+ * \name Routines to process data transfer
+ */
+//@{
+
+/**
+ * \brief Enable the reception of data from the USB host
+ *
+ * The value udi_cdc_rx_trans_sel indicate the RX buffer to fill.
+ *
+ * \param port Communication port number to manage
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+static bool udi_cdc_rx_start(uint8_t port);
+
+/**
+ * \brief Update rx buffer management with a new data
+ * Callback called after data reception on USB line
+ *
+ * \param status UDD_EP_TRANSFER_OK, if transfer finish
+ * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted
+ * \param n number of data received
+ */
+static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep);
+
+/**
+ * \brief Ack sent of tx buffer
+ * Callback called after data transfer on USB line
+ *
+ * \param status UDD_EP_TRANSFER_OK, if transfer finished
+ * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted
+ * \param n number of data transfered
+ */
+static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep);
+
+/**
+ * \brief Send buffer on line or wait a SOF event
+ *
+ * \param port Communication port number to manage
+ */
+static void udi_cdc_tx_send(uint8_t port);
+
+//@}
+
+//@}
+
+/**
+ * \name Information about configuration of communication line
+ */
+//@{
+COMPILER_WORD_ALIGNED
+ static usb_cdc_line_coding_t udi_cdc_line_coding[UDI_CDC_PORT_NB];
+static bool udi_cdc_serial_state_msg_ongoing[UDI_CDC_PORT_NB];
+static volatile le16_t udi_cdc_state[UDI_CDC_PORT_NB];
+COMPILER_WORD_ALIGNED static usb_cdc_notify_serial_state_t uid_cdc_state_msg[UDI_CDC_PORT_NB];
+
+//! Status of CDC COMM interfaces
+static volatile uint8_t udi_cdc_nb_comm_enabled = 0;
+//@}
+
+/**
+ * \name Variables to manage RX/TX transfer requests
+ * Two buffers for each sense are used to optimize the speed.
+ */
+//@{
+
+//! Status of CDC DATA interfaces
+static volatile uint8_t udi_cdc_nb_data_enabled = 0;
+static volatile bool udi_cdc_data_running = false;
+//! Buffer to receive data
+COMPILER_WORD_ALIGNED static uint8_t udi_cdc_rx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_RX_BUFFERS];
+//! Data available in RX buffers
+static uint16_t udi_cdc_rx_buf_nb[UDI_CDC_PORT_NB][2];
+//! Give the current RX buffer used (rx0 if 0, rx1 if 1)
+static volatile uint8_t udi_cdc_rx_buf_sel[UDI_CDC_PORT_NB];
+//! Read position in current RX buffer
+static volatile uint16_t udi_cdc_rx_pos[UDI_CDC_PORT_NB];
+//! Signal a transfer on-going
+static volatile bool udi_cdc_rx_trans_ongoing[UDI_CDC_PORT_NB];
+
+//! Define a transfer halted
+#define UDI_CDC_TRANS_HALTED 2
+
+//! Buffer to send data
+COMPILER_WORD_ALIGNED static uint8_t udi_cdc_tx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_TX_BUFFERS];
+//! Data available in TX buffers
+static uint16_t udi_cdc_tx_buf_nb[UDI_CDC_PORT_NB][2];
+//! Give current TX buffer used (tx0 if 0, tx1 if 1)
+static volatile uint8_t udi_cdc_tx_buf_sel[UDI_CDC_PORT_NB];
+//! Value of SOF during last TX transfer
+static uint16_t udi_cdc_tx_sof_num[UDI_CDC_PORT_NB];
+//! Signal a transfer on-going
+static volatile bool udi_cdc_tx_trans_ongoing[UDI_CDC_PORT_NB];
+//! Signal that both buffer content data to send
+static volatile bool udi_cdc_tx_both_buf_to_send[UDI_CDC_PORT_NB];
+
+//@}
+
+bool udi_cdc_comm_enable(void)
+{
+ uint8_t port;
+ uint8_t iface_comm_num;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+ udi_cdc_nb_comm_enabled = 0;
+#else
+ if (udi_cdc_nb_comm_enabled > UDI_CDC_PORT_NB) {
+ udi_cdc_nb_comm_enabled = 0;
+ }
+ port = udi_cdc_nb_comm_enabled;
+#endif
+
+ // Initialize control signal management
+ udi_cdc_state[port] = CPU_TO_LE16(0);
+
+ uid_cdc_state_msg[port].header.bmRequestType =
+ USB_REQ_DIR_IN | USB_REQ_TYPE_CLASS |
+ USB_REQ_RECIP_INTERFACE;
+ uid_cdc_state_msg[port].header.bNotification = USB_REQ_CDC_NOTIFY_SERIAL_STATE;
+ uid_cdc_state_msg[port].header.wValue = LE16(0);
+
+ switch (port) {
+#define UDI_CDC_PORT_TO_IFACE_COMM(index, unused) \
+ case index: \
+ iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_##index; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_IFACE_COMM, ~)
+#undef UDI_CDC_PORT_TO_IFACE_COMM
+ default:
+ iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_0;
+ break;
+ }
+
+ uid_cdc_state_msg[port].header.wIndex = LE16(iface_comm_num);
+ uid_cdc_state_msg[port].header.wLength = LE16(2);
+ uid_cdc_state_msg[port].value = CPU_TO_LE16(0);
+
+ udi_cdc_line_coding[port].dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE);
+ udi_cdc_line_coding[port].bCharFormat = UDI_CDC_DEFAULT_STOPBITS;
+ udi_cdc_line_coding[port].bParityType = UDI_CDC_DEFAULT_PARITY;
+ udi_cdc_line_coding[port].bDataBits = UDI_CDC_DEFAULT_DATABITS;
+ // Call application callback
+ // to initialize memories or indicate that interface is enabled
+ UDI_CDC_SET_CODING_EXT(port,(&udi_cdc_line_coding[port]));
+ if (!UDI_CDC_ENABLE_EXT(port)) {
+ return false;
+ }
+ udi_cdc_nb_comm_enabled++;
+ return true;
+}
+
+bool udi_cdc_data_enable(void)
+{
+ uint8_t port;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+ udi_cdc_nb_data_enabled = 0;
+#else
+ if (udi_cdc_nb_data_enabled > UDI_CDC_PORT_NB) {
+ udi_cdc_nb_data_enabled = 0;
+ }
+ port = udi_cdc_nb_data_enabled;
+#endif
+
+ // Initialize TX management
+ udi_cdc_tx_trans_ongoing[port] = false;
+ udi_cdc_tx_both_buf_to_send[port] = false;
+ udi_cdc_tx_buf_sel[port] = 0;
+ udi_cdc_tx_buf_nb[port][0] = 0;
+ udi_cdc_tx_buf_nb[port][1] = 0;
+ udi_cdc_tx_sof_num[port] = 0;
+ udi_cdc_tx_send(port);
+
+ // Initialize RX management
+ udi_cdc_rx_trans_ongoing[port] = false;
+ udi_cdc_rx_buf_sel[port] = 0;
+ udi_cdc_rx_buf_nb[port][0] = 0;
+ udi_cdc_rx_pos[port] = 0;
+ if (!udi_cdc_rx_start(port)) {
+ return false;
+ }
+ udi_cdc_nb_data_enabled++;
+ if (udi_cdc_nb_data_enabled == UDI_CDC_PORT_NB) {
+ udi_cdc_data_running = true;
+ }
+ return true;
+}
+
+void udi_cdc_comm_disable(void)
+{
+ Assert(udi_cdc_nb_comm_enabled != 0);
+ udi_cdc_nb_comm_enabled--;
+}
+
+void udi_cdc_data_disable(void)
+{
+ uint8_t port;
+ UNUSED(port);
+
+ Assert(udi_cdc_nb_data_enabled != 0);
+ udi_cdc_nb_data_enabled--;
+ port = udi_cdc_nb_data_enabled;
+ UDI_CDC_DISABLE_EXT(port);
+ udi_cdc_data_running = false;
+}
+
+bool udi_cdc_comm_setup(void)
+{
+ uint8_t port = udi_cdc_setup_to_port();
+
+ if (Udd_setup_is_in()) {
+ // GET Interface Requests
+ if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
+ // Requests Class Interface Get
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_CDC_GET_LINE_CODING:
+ // Get configuration of CDC line
+ if (sizeof(usb_cdc_line_coding_t) !=
+ udd_g_ctrlreq.req.wLength)
+ return false; // Error for USB host
+ udd_g_ctrlreq.payload =
+ (uint8_t *) &
+ udi_cdc_line_coding[port];
+ udd_g_ctrlreq.payload_size =
+ sizeof(usb_cdc_line_coding_t);
+ return true;
+ }
+ }
+ }
+ if (Udd_setup_is_out()) {
+ // SET Interface Requests
+ if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
+ // Requests Class Interface Set
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_CDC_SET_LINE_CODING:
+ // Change configuration of CDC line
+ if (sizeof(usb_cdc_line_coding_t) !=
+ udd_g_ctrlreq.req.wLength)
+ return false; // Error for USB host
+ udd_g_ctrlreq.callback =
+ udi_cdc_line_coding_received;
+ udd_g_ctrlreq.payload =
+ (uint8_t *) &
+ udi_cdc_line_coding[port];
+ udd_g_ctrlreq.payload_size =
+ sizeof(usb_cdc_line_coding_t);
+ return true;
+ case USB_REQ_CDC_SET_CONTROL_LINE_STATE:
+ // According cdc spec 1.1 chapter 6.2.14
+ UDI_CDC_SET_DTR_EXT(port, (0 !=
+ (udd_g_ctrlreq.req.wValue
+ & CDC_CTRL_SIGNAL_DTE_PRESENT)));
+ UDI_CDC_SET_RTS_EXT(port, (0 !=
+ (udd_g_ctrlreq.req.wValue
+ & CDC_CTRL_SIGNAL_ACTIVATE_CARRIER)));
+ return true;
+ }
+ }
+ }
+ return false; // request Not supported
+}
+
+bool udi_cdc_data_setup(void)
+{
+ return false; // request Not supported
+}
+
+uint8_t udi_cdc_getsetting(void)
+{
+ return 0; // CDC don't have multiple alternate setting
+}
+
+void udi_cdc_data_sof_notify(void)
+{
+ static uint8_t port_notify = 0;
+
+ // A call of udi_cdc_data_sof_notify() is done for each port
+ udi_cdc_tx_send(port_notify);
+#if UDI_CDC_PORT_NB != 1 // To optimize code
+ port_notify++;
+ if (port_notify >= UDI_CDC_PORT_NB) {
+ port_notify = 0;
+ }
+#endif
+}
+
+
+//-------------------------------------------------
+//------- Internal routines to control serial line
+
+static uint8_t udi_cdc_setup_to_port(void)
+{
+ uint8_t port;
+
+ switch (udd_g_ctrlreq.req.wIndex & 0xFF) {
+#define UDI_CDC_IFACE_COMM_TO_PORT(iface, unused) \
+ case UDI_CDC_COMM_IFACE_NUMBER_##iface: \
+ port = iface; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_IFACE_COMM_TO_PORT, ~)
+#undef UDI_CDC_IFACE_COMM_TO_PORT
+ default:
+ port = 0;
+ break;
+ }
+ return port;
+}
+
+static void udi_cdc_line_coding_received(void)
+{
+ uint8_t port = udi_cdc_setup_to_port();
+ UNUSED(port);
+
+ UDI_CDC_SET_CODING_EXT(port, (&udi_cdc_line_coding[port]));
+}
+
+static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask)
+{
+ irqflags_t flags;
+ udd_ep_id_t ep_comm;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ // Update state
+ flags = cpu_irq_save(); // Protect udi_cdc_state
+ if (b_set) {
+ udi_cdc_state[port] |= bit_mask;
+ } else {
+ udi_cdc_state[port] &= ~(unsigned)bit_mask;
+ }
+ cpu_irq_restore(flags);
+
+ // Send it if possible and state changed
+ switch (port) {
+#define UDI_CDC_PORT_TO_COMM_EP(index, unused) \
+ case index: \
+ ep_comm = UDI_CDC_COMM_EP_##index; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_COMM_EP, ~)
+#undef UDI_CDC_PORT_TO_COMM_EP
+ default:
+ ep_comm = UDI_CDC_COMM_EP_0;
+ break;
+ }
+ udi_cdc_ctrl_state_notify(port, ep_comm);
+}
+
+
+static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep)
+{
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ // Send it if possible and state changed
+ if ((!udi_cdc_serial_state_msg_ongoing[port])
+ && (udi_cdc_state[port] != uid_cdc_state_msg[port].value)) {
+ // Fill notification message
+ uid_cdc_state_msg[port].value = udi_cdc_state[port];
+ // Send notification message
+ udi_cdc_serial_state_msg_ongoing[port] =
+ udd_ep_run(ep,
+ false,
+ (uint8_t *) & uid_cdc_state_msg[port],
+ sizeof(uid_cdc_state_msg[0]),
+ udi_cdc_serial_state_msg_sent);
+ }
+}
+
+
+static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
+{
+ uint8_t port;
+ UNUSED(n);
+ UNUSED(status);
+
+ switch (ep) {
+#define UDI_CDC_GET_PORT_FROM_COMM_EP(iface, unused) \
+ case UDI_CDC_COMM_EP_##iface: \
+ port = iface; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_GET_PORT_FROM_COMM_EP, ~)
+#undef UDI_CDC_GET_PORT_FROM_COMM_EP
+ default:
+ port = 0;
+ break;
+ }
+
+ udi_cdc_serial_state_msg_ongoing[port] = false;
+
+ // For the irregular signals like break, the incoming ring signal,
+ // or the overrun error state, this will reset their values to zero
+ // and again will not send another notification until their state changes.
+ udi_cdc_state[port] &= ~(CDC_SERIAL_STATE_BREAK |
+ CDC_SERIAL_STATE_RING |
+ CDC_SERIAL_STATE_FRAMING |
+ CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN);
+ uid_cdc_state_msg[port].value &= ~(CDC_SERIAL_STATE_BREAK |
+ CDC_SERIAL_STATE_RING |
+ CDC_SERIAL_STATE_FRAMING |
+ CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN);
+ // Send it if possible and state changed
+ udi_cdc_ctrl_state_notify(port, ep);
+}
+
+
+//-------------------------------------------------
+//------- Internal routines to process data transfer
+
+
+static bool udi_cdc_rx_start(uint8_t port)
+{
+ irqflags_t flags;
+ uint8_t buf_sel_trans;
+ udd_ep_id_t ep;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ flags = cpu_irq_save();
+ buf_sel_trans = udi_cdc_rx_buf_sel[port];
+ if (udi_cdc_rx_trans_ongoing[port] ||
+ (udi_cdc_rx_pos[port] < udi_cdc_rx_buf_nb[port][buf_sel_trans])) {
+ // Transfer already on-going or current buffer no empty
+ cpu_irq_restore(flags);
+ return false;
+ }
+
+ // Change current buffer
+ udi_cdc_rx_pos[port] = 0;
+ udi_cdc_rx_buf_sel[port] = (buf_sel_trans==0)?1:0;
+
+ // Start transfer on RX
+ udi_cdc_rx_trans_ongoing[port] = true;
+ cpu_irq_restore(flags);
+
+ if (udi_cdc_multi_is_rx_ready(port)) {
+ UDI_CDC_RX_NOTIFY(port);
+ }
+ // Send the buffer with enable of short packet
+ switch (port) {
+#define UDI_CDC_PORT_TO_DATA_EP_OUT(index, unused) \
+ case index: \
+ ep = UDI_CDC_DATA_EP_OUT_##index; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_OUT, ~)
+#undef UDI_CDC_PORT_TO_DATA_EP_OUT
+ default:
+ ep = UDI_CDC_DATA_EP_OUT_0;
+ break;
+ }
+ return udd_ep_run(ep,
+ true,
+ udi_cdc_rx_buf[port][buf_sel_trans],
+ UDI_CDC_RX_BUFFERS,
+ udi_cdc_data_received);
+}
+
+
+static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
+{
+ uint8_t buf_sel_trans;
+ uint8_t port;
+
+ switch (ep) {
+#define UDI_CDC_DATA_EP_OUT_TO_PORT(index, unused) \
+ case UDI_CDC_DATA_EP_OUT_##index: \
+ port = index; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_OUT_TO_PORT, ~)
+#undef UDI_CDC_DATA_EP_OUT_TO_PORT
+ default:
+ port = 0;
+ break;
+ }
+
+ if (UDD_EP_TRANSFER_OK != status) {
+ // Abort reception
+ return;
+ }
+ buf_sel_trans = (udi_cdc_rx_buf_sel[port]==0)?1:0;
+ if (!n) {
+ udd_ep_run( ep,
+ true,
+ udi_cdc_rx_buf[port][buf_sel_trans],
+ UDI_CDC_RX_BUFFERS,
+ udi_cdc_data_received);
+ return;
+ }
+ udi_cdc_rx_buf_nb[port][buf_sel_trans] = n;
+ udi_cdc_rx_trans_ongoing[port] = false;
+ udi_cdc_rx_start(port);
+}
+
+
+static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
+{
+ uint8_t port;
+ UNUSED(n);
+
+ switch (ep) {
+#define UDI_CDC_DATA_EP_IN_TO_PORT(index, unused) \
+ case UDI_CDC_DATA_EP_IN_##index: \
+ port = index; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_IN_TO_PORT, ~)
+#undef UDI_CDC_DATA_EP_IN_TO_PORT
+ default:
+ port = 0;
+ break;
+ }
+
+ if (UDD_EP_TRANSFER_OK != status) {
+ // Abort transfer
+ return;
+ }
+ udi_cdc_tx_buf_nb[port][(udi_cdc_tx_buf_sel[port]==0)?1:0] = 0;
+ udi_cdc_tx_both_buf_to_send[port] = false;
+ udi_cdc_tx_trans_ongoing[port] = false;
+
+ if (n != 0) {
+ UDI_CDC_TX_EMPTY_NOTIFY(port);
+ }
+ udi_cdc_tx_send(port);
+}
+
+
+static void udi_cdc_tx_send(uint8_t port)
+{
+ irqflags_t flags;
+ uint8_t buf_sel_trans;
+ bool b_short_packet;
+ udd_ep_id_t ep;
+ static uint16_t sof_zlp_counter = 0;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ if (udi_cdc_tx_trans_ongoing[port]) {
+ return; // Already on going or wait next SOF to send next data
+ }
+ if (udd_is_high_speed()) {
+ if (udi_cdc_tx_sof_num[port] == udd_get_micro_frame_number()) {
+ return; // Wait next SOF to send next data
+ }
+ }else{
+ if (udi_cdc_tx_sof_num[port] == udd_get_frame_number()) {
+ return; // Wait next SOF to send next data
+ }
+ }
+
+ flags = cpu_irq_save(); // to protect udi_cdc_tx_buf_sel
+ buf_sel_trans = udi_cdc_tx_buf_sel[port];
+ if (udi_cdc_tx_buf_nb[port][buf_sel_trans] == 0) {
+ sof_zlp_counter++;
+ if (((!udd_is_high_speed()) && (sof_zlp_counter < 100))
+ || (udd_is_high_speed() && (sof_zlp_counter < 800))) {
+ cpu_irq_restore(flags);
+ return;
+ }
+ }
+ sof_zlp_counter = 0;
+
+ if (!udi_cdc_tx_both_buf_to_send[port]) {
+ // Send current Buffer
+ // and switch the current buffer
+ udi_cdc_tx_buf_sel[port] = (buf_sel_trans==0)?1:0;
+ }else{
+ // Send the other Buffer
+ // and no switch the current buffer
+ buf_sel_trans = (buf_sel_trans==0)?1:0;
+ }
+ udi_cdc_tx_trans_ongoing[port] = true;
+ cpu_irq_restore(flags);
+
+ b_short_packet = (udi_cdc_tx_buf_nb[port][buf_sel_trans] != UDI_CDC_TX_BUFFERS);
+ if (b_short_packet) {
+ if (udd_is_high_speed()) {
+ udi_cdc_tx_sof_num[port] = udd_get_micro_frame_number();
+ }else{
+ udi_cdc_tx_sof_num[port] = udd_get_frame_number();
+ }
+ }else{
+ udi_cdc_tx_sof_num[port] = 0; // Force next transfer without wait SOF
+ }
+
+ // Send the buffer with enable of short packet
+ switch (port) {
+#define UDI_CDC_PORT_TO_DATA_EP_IN(index, unused) \
+ case index: \
+ ep = UDI_CDC_DATA_EP_IN_##index; \
+ break;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_IN, ~)
+#undef UDI_CDC_PORT_TO_DATA_EP_IN
+ default:
+ ep = UDI_CDC_DATA_EP_IN_0;
+ break;
+ }
+ udd_ep_run( ep,
+ b_short_packet,
+ udi_cdc_tx_buf[port][buf_sel_trans],
+ udi_cdc_tx_buf_nb[port][buf_sel_trans],
+ udi_cdc_data_sent);
+}
+
+
+//---------------------------------------------
+//------- Application interface
+
+
+//------- Application interface
+
+void udi_cdc_ctrl_signal_dcd(bool b_set)
+{
+ udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DCD);
+}
+
+void udi_cdc_ctrl_signal_dsr(bool b_set)
+{
+ udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DSR);
+}
+
+void udi_cdc_signal_framing_error(void)
+{
+ udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_FRAMING);
+}
+
+void udi_cdc_signal_parity_error(void)
+{
+ udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_PARITY);
+}
+
+void udi_cdc_signal_overrun(void)
+{
+ udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_OVERRUN);
+}
+
+void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set)
+{
+ udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DCD);
+}
+
+void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set)
+{
+ udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DSR);
+}
+
+void udi_cdc_multi_signal_framing_error(uint8_t port)
+{
+ udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_FRAMING);
+}
+
+void udi_cdc_multi_signal_parity_error(uint8_t port)
+{
+ udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_PARITY);
+}
+
+void udi_cdc_multi_signal_overrun(uint8_t port)
+{
+ udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_OVERRUN);
+}
+
+iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port)
+{
+ irqflags_t flags;
+ uint16_t pos;
+ iram_size_t nb_received;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+ flags = cpu_irq_save();
+ pos = udi_cdc_rx_pos[port];
+ nb_received = udi_cdc_rx_buf_nb[port][udi_cdc_rx_buf_sel[port]] - pos;
+ cpu_irq_restore(flags);
+ return nb_received;
+}
+
+iram_size_t udi_cdc_get_nb_received_data(void)
+{
+ return udi_cdc_multi_get_nb_received_data(0);
+}
+
+bool udi_cdc_multi_is_rx_ready(uint8_t port)
+{
+ return (udi_cdc_multi_get_nb_received_data(port) > 0);
+}
+
+bool udi_cdc_is_rx_ready(void)
+{
+ return udi_cdc_multi_is_rx_ready(0);
+}
+
+int udi_cdc_multi_getc(uint8_t port)
+{
+ irqflags_t flags;
+ int rx_data = 0;
+ bool b_databit_9;
+ uint16_t pos;
+ uint8_t buf_sel;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits);
+
+udi_cdc_getc_process_one_byte:
+ // Check available data
+ flags = cpu_irq_save();
+ pos = udi_cdc_rx_pos[port];
+ buf_sel = udi_cdc_rx_buf_sel[port];
+ cpu_irq_restore(flags);
+ while (pos >= udi_cdc_rx_buf_nb[port][buf_sel]) {
+ if (!udi_cdc_data_running) {
+ return 0;
+ }
+ goto udi_cdc_getc_process_one_byte;
+ }
+
+ // Read data
+ rx_data |= udi_cdc_rx_buf[port][buf_sel][pos];
+ udi_cdc_rx_pos[port] = pos+1;
+
+ udi_cdc_rx_start(port);
+
+ if (b_databit_9) {
+ // Receive MSB
+ b_databit_9 = false;
+ rx_data = rx_data << 8;
+ goto udi_cdc_getc_process_one_byte;
+ }
+ return rx_data;
+}
+
+int udi_cdc_getc(void)
+{
+ return udi_cdc_multi_getc(0);
+}
+
+iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size)
+{
+ irqflags_t flags;
+ uint8_t *ptr_buf = (uint8_t *)buf;
+ iram_size_t copy_nb;
+ uint16_t pos;
+ uint8_t buf_sel;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+udi_cdc_read_buf_loop_wait:
+ // Check available data
+ flags = cpu_irq_save();
+ pos = udi_cdc_rx_pos[port];
+ buf_sel = udi_cdc_rx_buf_sel[port];
+ cpu_irq_restore(flags);
+ while (pos >= udi_cdc_rx_buf_nb[port][buf_sel]) {
+ if (!udi_cdc_data_running) {
+ return size;
+ }
+ goto udi_cdc_read_buf_loop_wait;
+ }
+
+ // Read data
+ copy_nb = udi_cdc_rx_buf_nb[port][buf_sel] - pos;
+ if (copy_nb>size) {
+ copy_nb = size;
+ }
+ memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], copy_nb);
+ udi_cdc_rx_pos[port] += copy_nb;
+ ptr_buf += copy_nb;
+ size -= copy_nb;
+ udi_cdc_rx_start(port);
+
+ if (size) {
+ goto udi_cdc_read_buf_loop_wait;
+ }
+ return 0;
+}
+
+iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size)
+{
+ return udi_cdc_multi_read_buf(0, buf, size);
+}
+
+iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port)
+{
+ irqflags_t flags;
+ iram_size_t buf_sel_nb, buf_nosel_nb, retval;
+ uint8_t buf_sel;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ flags = cpu_irq_save();
+ buf_sel = udi_cdc_tx_buf_sel[port];
+ buf_sel_nb = udi_cdc_tx_buf_nb[port][buf_sel];
+ buf_nosel_nb = udi_cdc_tx_buf_nb[port][(buf_sel == 0)? 1 : 0];
+ if (buf_sel_nb == UDI_CDC_TX_BUFFERS) {
+ if ((!udi_cdc_tx_trans_ongoing[port])
+ && (!udi_cdc_tx_both_buf_to_send[port])) {
+ /* One buffer is full, but the other buffer is not used.
+ * (not used = transfer on-going)
+ * then move to the other buffer to store data */
+ udi_cdc_tx_both_buf_to_send[port] = true;
+ udi_cdc_tx_buf_sel[port] = (buf_sel == 0)? 1 : 0;
+ buf_sel_nb = 0;
+ buf_nosel_nb = UDI_CDC_TX_BUFFERS;
+ }
+ }
+ retval = UDI_CDC_TX_BUFFERS - buf_sel_nb;
+ cpu_irq_restore(flags);
+ return retval;
+}
+
+iram_size_t udi_cdc_get_free_tx_buffer(void)
+{
+ return udi_cdc_multi_get_free_tx_buffer(0);
+}
+
+bool udi_cdc_multi_is_tx_ready(uint8_t port)
+{
+ return (udi_cdc_multi_get_free_tx_buffer(port) != 0);
+}
+
+bool udi_cdc_is_tx_ready(void)
+{
+ return udi_cdc_multi_is_tx_ready(0);
+}
+
+int udi_cdc_multi_putc(uint8_t port, int value)
+{
+ irqflags_t flags;
+ bool b_databit_9;
+ uint8_t buf_sel;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits);
+
+udi_cdc_putc_process_one_byte:
+ // Check available space
+ if (!udi_cdc_multi_is_tx_ready(port)) {
+ if (!udi_cdc_data_running) {
+ return false;
+ }
+ goto udi_cdc_putc_process_one_byte;
+ }
+
+ // Write value
+ flags = cpu_irq_save();
+ buf_sel = udi_cdc_tx_buf_sel[port];
+ udi_cdc_tx_buf[port][buf_sel][udi_cdc_tx_buf_nb[port][buf_sel]++] = value;
+ cpu_irq_restore(flags);
+
+ if (b_databit_9) {
+ // Send MSB
+ b_databit_9 = false;
+ value = value >> 8;
+ goto udi_cdc_putc_process_one_byte;
+ }
+ return true;
+}
+
+int udi_cdc_putc(int value)
+{
+ return udi_cdc_multi_putc(0, value);
+}
+
+iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size)
+{
+ irqflags_t flags;
+ uint8_t buf_sel;
+ uint16_t buf_nb;
+ iram_size_t copy_nb;
+ uint8_t *ptr_buf = (uint8_t *)buf;
+
+#if UDI_CDC_PORT_NB == 1 // To optimize code
+ port = 0;
+#endif
+
+ if (9 == udi_cdc_line_coding[port].bDataBits) {
+ size *=2;
+ }
+
+udi_cdc_write_buf_loop_wait:
+ // Check available space
+ if (!udi_cdc_multi_is_tx_ready(port)) {
+ if (!udi_cdc_data_running) {
+ return size;
+ }
+ goto udi_cdc_write_buf_loop_wait;
+ }
+
+ // Write values
+ flags = cpu_irq_save();
+ buf_sel = udi_cdc_tx_buf_sel[port];
+ buf_nb = udi_cdc_tx_buf_nb[port][buf_sel];
+ copy_nb = UDI_CDC_TX_BUFFERS - buf_nb;
+ if (copy_nb > size) {
+ copy_nb = size;
+ }
+ memcpy(&udi_cdc_tx_buf[port][buf_sel][buf_nb], ptr_buf, copy_nb);
+ udi_cdc_tx_buf_nb[port][buf_sel] = buf_nb + copy_nb;
+ cpu_irq_restore(flags);
+
+ // Update buffer pointer
+ ptr_buf = ptr_buf + copy_nb;
+ size -= copy_nb;
+
+ if (size) {
+ goto udi_cdc_write_buf_loop_wait;
+ }
+
+ return 0;
+}
+
+iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size)
+{
+ return udi_cdc_multi_write_buf(0, buf, size);
+}
+
+//@}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc.h
new file mode 100755
index 0000000000000000000000000000000000000000..d13fc13ab34daee55cb30a31fdc4306a562a74e8
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc.h
@@ -0,0 +1,796 @@
+/**
+ * \file
+ *
+ * \brief USB Device Communication Device Class (CDC) interface definitions.
+ *
+ * Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UDI_CDC_H_
+#define _UDI_CDC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "usb_protocol_cdc.h"
+#include "udd.h"
+#include "udc_desc.h"
+#include "udi.h"
+
+// Check the number of port
+#ifndef UDI_CDC_PORT_NB
+# define UDI_CDC_PORT_NB 1
+#endif
+#if (UDI_CDC_PORT_NB < 1) || (UDI_CDC_PORT_NB > 7)
+# error UDI_CDC_PORT_NB must be between 1 and 7
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup udi_cdc_group_udc
+ * @{
+ */
+
+//! Global structure which contains standard UDI API for UDC
+extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm;
+extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_data;
+//@}
+
+/**
+ * \ingroup udi_cdc_group
+ * \defgroup udi_cdc_group_desc USB interface descriptors
+ *
+ * The following structures provide predefined USB interface descriptors.
+ * It must be used to define the final USB descriptors.
+ */
+//@{
+
+/**
+ * \brief Communication Class interface descriptor
+ *
+ * Interface descriptor with associated functional and endpoint
+ * descriptors for the CDC Communication Class interface.
+ */
+typedef struct {
+ //! Standard interface descriptor
+ usb_iface_desc_t iface;
+ //! CDC Header functional descriptor
+ usb_cdc_hdr_desc_t header;
+ //! CDC Abstract Control Model functional descriptor
+ usb_cdc_acm_desc_t acm;
+ //! CDC Union functional descriptor
+ usb_cdc_union_desc_t union_desc;
+ //! CDC Call Management functional descriptor
+ usb_cdc_call_mgmt_desc_t call_mgmt;
+ //! Notification endpoint descriptor
+ usb_ep_desc_t ep_notify;
+} udi_cdc_comm_desc_t;
+
+
+/**
+ * \brief Data Class interface descriptor
+ *
+ * Interface descriptor with associated endpoint descriptors for the
+ * CDC Data Class interface.
+ */
+typedef struct {
+ //! Standard interface descriptor
+ usb_iface_desc_t iface;
+ //! Data IN/OUT endpoint descriptors
+ usb_ep_desc_t ep_in;
+ usb_ep_desc_t ep_out;
+} udi_cdc_data_desc_t;
+
+
+//! CDC communication endpoints size for all speeds
+#define UDI_CDC_COMM_EP_SIZE 64
+//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B)
+#define UDI_CDC_DATA_EPS_FS_SIZE 64
+//! CDC data endpoints size for HS speed (512B only)
+#define UDI_CDC_DATA_EPS_HS_SIZE 512
+
+/**
+ * \name Content of interface descriptors
+ * Up to 7 CDC interfaces can be implemented on a USB device.
+ */
+//@{
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_0
+#define UDI_CDC_IAD_STRING_ID_0 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_0
+#define UDI_CDC_COMM_STRING_ID_0 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_0
+#define UDI_CDC_DATA_STRING_ID_0 0
+#endif
+#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0)
+#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0)
+#define UDI_CDC_DATA_DESC_0_FS UDI_CDC_DATA_DESC_FS(0)
+#define UDI_CDC_DATA_DESC_0_HS UDI_CDC_DATA_DESC_HS(0)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_1
+#define UDI_CDC_IAD_STRING_ID_1 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_1
+#define UDI_CDC_COMM_STRING_ID_1 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_1
+#define UDI_CDC_DATA_STRING_ID_1 0
+#endif
+#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1)
+#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1)
+#define UDI_CDC_DATA_DESC_1_FS UDI_CDC_DATA_DESC_FS(1)
+#define UDI_CDC_DATA_DESC_1_HS UDI_CDC_DATA_DESC_HS(1)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_2
+#define UDI_CDC_IAD_STRING_ID_2 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_2
+#define UDI_CDC_COMM_STRING_ID_2 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_2
+#define UDI_CDC_DATA_STRING_ID_2 0
+#endif
+#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2)
+#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2)
+#define UDI_CDC_DATA_DESC_2_FS UDI_CDC_DATA_DESC_FS(2)
+#define UDI_CDC_DATA_DESC_2_HS UDI_CDC_DATA_DESC_HS(2)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_3
+#define UDI_CDC_IAD_STRING_ID_3 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_3
+#define UDI_CDC_COMM_STRING_ID_3 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_3
+#define UDI_CDC_DATA_STRING_ID_3 0
+#endif
+#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3)
+#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3)
+#define UDI_CDC_DATA_DESC_3_FS UDI_CDC_DATA_DESC_FS(3)
+#define UDI_CDC_DATA_DESC_3_HS UDI_CDC_DATA_DESC_HS(3)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_4
+#define UDI_CDC_IAD_STRING_ID_4 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_4
+#define UDI_CDC_COMM_STRING_ID_4 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_4
+#define UDI_CDC_DATA_STRING_ID_4 0
+#endif
+#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4)
+#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4)
+#define UDI_CDC_DATA_DESC_4_FS UDI_CDC_DATA_DESC_FS(4)
+#define UDI_CDC_DATA_DESC_4_HS UDI_CDC_DATA_DESC_HS(4)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_5
+#define UDI_CDC_IAD_STRING_ID_5 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_5
+#define UDI_CDC_COMM_STRING_ID_5 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_5
+#define UDI_CDC_DATA_STRING_ID_5 0
+#endif
+#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5)
+#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5)
+#define UDI_CDC_DATA_DESC_5_FS UDI_CDC_DATA_DESC_FS(5)
+#define UDI_CDC_DATA_DESC_5_HS UDI_CDC_DATA_DESC_HS(5)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_6
+#define UDI_CDC_IAD_STRING_ID_6 0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_6
+#define UDI_CDC_COMM_STRING_ID_6 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_6
+#define UDI_CDC_DATA_STRING_ID_6 0
+#endif
+#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6)
+#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6)
+#define UDI_CDC_DATA_DESC_6_FS UDI_CDC_DATA_DESC_FS(6)
+#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6)
+//@}
+
+
+//! Content of CDC IAD interface descriptor for all speeds
+#define UDI_CDC_IAD_DESC(port) { \
+ .bLength = sizeof(usb_iad_desc_t),\
+ .bDescriptorType = USB_DT_IAD,\
+ .bInterfaceCount = 2,\
+ .bFunctionClass = CDC_CLASS_COMM,\
+ .bFunctionSubClass = CDC_SUBCLASS_ACM,\
+ .bFunctionProtocol = CDC_PROTOCOL_V25TER,\
+ .bFirstInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\
+ .iFunction = UDI_CDC_IAD_STRING_ID_##port,\
+ }
+
+//! Content of CDC COMM interface descriptor for all speeds
+#define UDI_CDC_COMM_DESC(port) { \
+ .iface.bLength = sizeof(usb_iface_desc_t),\
+ .iface.bDescriptorType = USB_DT_INTERFACE,\
+ .iface.bAlternateSetting = 0,\
+ .iface.bNumEndpoints = 1,\
+ .iface.bInterfaceClass = CDC_CLASS_COMM,\
+ .iface.bInterfaceSubClass = CDC_SUBCLASS_ACM,\
+ .iface.bInterfaceProtocol = CDC_PROTOCOL_V25TER,\
+ .header.bFunctionLength = sizeof(usb_cdc_hdr_desc_t),\
+ .header.bDescriptorType = CDC_CS_INTERFACE,\
+ .header.bDescriptorSubtype = CDC_SCS_HEADER,\
+ .header.bcdCDC = LE16(0x0110),\
+ .call_mgmt.bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t),\
+ .call_mgmt.bDescriptorType = CDC_CS_INTERFACE,\
+ .call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT,\
+ .call_mgmt.bmCapabilities = \
+ CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI,\
+ .acm.bFunctionLength = sizeof(usb_cdc_acm_desc_t),\
+ .acm.bDescriptorType = CDC_CS_INTERFACE,\
+ .acm.bDescriptorSubtype = CDC_SCS_ACM,\
+ .acm.bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS,\
+ .union_desc.bFunctionLength = sizeof(usb_cdc_union_desc_t),\
+ .union_desc.bDescriptorType = CDC_CS_INTERFACE,\
+ .union_desc.bDescriptorSubtype= CDC_SCS_UNION,\
+ .ep_notify.bLength = sizeof(usb_ep_desc_t),\
+ .ep_notify.bDescriptorType = USB_DT_ENDPOINT,\
+ .ep_notify.bmAttributes = USB_EP_TYPE_INTERRUPT,\
+ .ep_notify.wMaxPacketSize = LE16(UDI_CDC_COMM_EP_SIZE),\
+ .ep_notify.bInterval = 0x10,\
+ .ep_notify.bEndpointAddress = UDI_CDC_COMM_EP_##port,\
+ .iface.bInterfaceNumber = UDI_CDC_COMM_IFACE_NUMBER_##port,\
+ .call_mgmt.bDataInterface = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+ .union_desc.bMasterInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\
+ .union_desc.bSlaveInterface0 = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+ .iface.iInterface = UDI_CDC_COMM_STRING_ID_##port,\
+ }
+
+//! Content of CDC DATA interface descriptors
+#define UDI_CDC_DATA_DESC_COMMON \
+ .iface.bLength = sizeof(usb_iface_desc_t),\
+ .iface.bDescriptorType = USB_DT_INTERFACE,\
+ .iface.bAlternateSetting = 0,\
+ .iface.bNumEndpoints = 2,\
+ .iface.bInterfaceClass = CDC_CLASS_DATA,\
+ .iface.bInterfaceSubClass = 0,\
+ .iface.bInterfaceProtocol = 0,\
+ .ep_in.bLength = sizeof(usb_ep_desc_t),\
+ .ep_in.bDescriptorType = USB_DT_ENDPOINT,\
+ .ep_in.bmAttributes = USB_EP_TYPE_BULK,\
+ .ep_in.bInterval = 0,\
+ .ep_out.bLength = sizeof(usb_ep_desc_t),\
+ .ep_out.bDescriptorType = USB_DT_ENDPOINT,\
+ .ep_out.bmAttributes = USB_EP_TYPE_BULK,\
+ .ep_out.bInterval = 0,
+
+#define UDI_CDC_DATA_DESC_FS(port) { \
+ UDI_CDC_DATA_DESC_COMMON \
+ .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\
+ .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\
+ .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\
+ .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\
+ .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+ .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\
+ }
+
+#define UDI_CDC_DATA_DESC_HS(port) { \
+ UDI_CDC_DATA_DESC_COMMON \
+ .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\
+ .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\
+ .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\
+ .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\
+ .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+ .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\
+ }
+
+//@}
+
+/**
+ * \ingroup udi_group
+ * \defgroup udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC)
+ *
+ * Common APIs used by high level application to use this USB class.
+ *
+ * These routines are used to transfer and control data
+ * to/from USB CDC endpoint.
+ *
+ * See \ref udi_cdc_quickstart.
+ * @{
+ */
+
+/**
+ * \name Interface for application with single CDC interface support
+ */
+//@{
+
+/**
+ * \brief Notify a state change of DCD signal
+ *
+ * \param b_set DCD is enabled if true, else disabled
+ */
+void udi_cdc_ctrl_signal_dcd(bool b_set);
+
+/**
+ * \brief Notify a state change of DSR signal
+ *
+ * \param b_set DSR is enabled if true, else disabled
+ */
+void udi_cdc_ctrl_signal_dsr(bool b_set);
+
+/**
+ * \brief Notify a framing error
+ */
+void udi_cdc_signal_framing_error(void);
+
+/**
+ * \brief Notify a parity error
+ */
+void udi_cdc_signal_parity_error(void);
+
+/**
+ * \brief Notify a overrun
+ */
+void udi_cdc_signal_overrun(void);
+
+/**
+ * \brief Gets the number of byte received
+ *
+ * \return the number of data available
+ */
+iram_size_t udi_cdc_get_nb_received_data(void);
+
+/**
+ * \brief This function checks if a character has been received on the CDC line
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool udi_cdc_is_rx_ready(void);
+
+/**
+ * \brief Waits and gets a value on CDC line
+ *
+ * \return value read on CDC line
+ */
+int udi_cdc_getc(void);
+
+/**
+ * \brief Reads a RAM buffer on CDC line
+ *
+ * \param buf Values read
+ * \param size Number of value read
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size);
+
+/**
+ * \brief Gets the number of free byte in TX buffer
+ *
+ * \return the number of free byte in TX buffer
+ */
+iram_size_t udi_cdc_get_free_tx_buffer(void);
+
+/**
+ * \brief This function checks if a new character sent is possible
+ * The type int is used to support scanf redirection from compiler LIB.
+ *
+ * \return \c 1 if a new character can be sent
+ */
+bool udi_cdc_is_tx_ready(void);
+
+/**
+ * \brief Puts a byte on CDC line
+ * The type int is used to support printf redirection from compiler LIB.
+ *
+ * \param value Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int udi_cdc_putc(int value);
+
+/**
+ * \brief Writes a RAM buffer on CDC line
+ *
+ * \param buf Values to write
+ * \param size Number of value to write
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size);
+//@}
+
+/**
+ * \name Interface for application with multi CDC interfaces support
+ */
+//@{
+
+/**
+ * \brief Notify a state change of DCD signal
+ *
+ * \param port Communication port number to manage
+ * \param b_set DCD is enabled if true, else disabled
+ */
+void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set);
+
+/**
+ * \brief Notify a state change of DSR signal
+ *
+ * \param port Communication port number to manage
+ * \param b_set DSR is enabled if true, else disabled
+ */
+void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set);
+
+/**
+ * \brief Notify a framing error
+ *
+ * \param port Communication port number to manage
+ */
+void udi_cdc_multi_signal_framing_error(uint8_t port);
+
+/**
+ * \brief Notify a parity error
+ *
+ * \param port Communication port number to manage
+ */
+void udi_cdc_multi_signal_parity_error(uint8_t port);
+
+/**
+ * \brief Notify a overrun
+ *
+ * \param port Communication port number to manage
+ */
+void udi_cdc_multi_signal_overrun(uint8_t port);
+
+/**
+ * \brief Gets the number of byte received
+ *
+ * \param port Communication port number to manage
+ *
+ * \return the number of data available
+ */
+iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port);
+
+/**
+ * \brief This function checks if a character has been received on the CDC line
+ *
+ * \param port Communication port number to manage
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool udi_cdc_multi_is_rx_ready(uint8_t port);
+
+/**
+ * \brief Waits and gets a value on CDC line
+ *
+ * \param port Communication port number to manage
+ *
+ * \return value read on CDC line
+ */
+int udi_cdc_multi_getc(uint8_t port);
+
+/**
+ * \brief Reads a RAM buffer on CDC line
+ *
+ * \param port Communication port number to manage
+ * \param buf Values read
+ * \param size Number of values read
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size);
+
+/**
+ * \brief Gets the number of free byte in TX buffer
+ *
+ * \param port Communication port number to manage
+ *
+ * \return the number of free byte in TX buffer
+ */
+iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port);
+
+/**
+ * \brief This function checks if a new character sent is possible
+ * The type int is used to support scanf redirection from compiler LIB.
+ *
+ * \param port Communication port number to manage
+ *
+ * \return \c 1 if a new character can be sent
+ */
+bool udi_cdc_multi_is_tx_ready(uint8_t port);
+
+/**
+ * \brief Puts a byte on CDC line
+ * The type int is used to support printf redirection from compiler LIB.
+ *
+ * \param port Communication port number to manage
+ * \param value Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int udi_cdc_multi_putc(uint8_t port, int value);
+
+/**
+ * \brief Writes a RAM buffer on CDC line
+ *
+ * \param port Communication port number to manage
+ * \param buf Values to write
+ * \param size Number of value to write
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size);
+//@}
+
+//@}
+
+/**
+ * \page udi_cdc_quickstart Quick start guide for USB device Communication Class Device module (UDI CDC)
+ *
+ * This is the quick start guide for the \ref udi_cdc_group
+ * "USB device interface CDC module (UDI CDC)" with step-by-step instructions on
+ * how to configure and use the modules in a selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section udi_cdc_basic_use_case Basic use case
+ * In this basic use case, the "USB CDC (Single Interface Device)" module is used
+ * with only one communication port.
+ * The "USB CDC (Composite Device)" module usage is described in \ref udi_cdc_use_cases
+ * "Advanced use cases".
+ *
+ * \section udi_cdc_basic_use_case_setup Setup steps
+ * \subsection udi_cdc_basic_use_case_setup_prereq Prerequisites
+ * \copydetails udc_basic_use_case_setup_prereq
+ * \subsection udi_cdc_basic_use_case_setup_code Example code
+ * \copydetails udc_basic_use_case_setup_code
+ * \subsection udi_cdc_basic_use_case_setup_flow Workflow
+ * \copydetails udc_basic_use_case_setup_flow
+ *
+ * \section udi_cdc_basic_use_case_usage Usage steps
+ *
+ * \subsection udi_cdc_basic_use_case_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
+ extern bool my_callback_cdc_enable(void);
+ #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
+ extern void my_callback_cdc_disable(void);
+ #define UDI_CDC_LOW_RATE
+
+ #define UDI_CDC_DEFAULT_RATE 115200
+ #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
+ #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
+ #define UDI_CDC_DEFAULT_DATABITS 8
+
+ #include "udi_cdc_conf.h" // At the end of conf_usb.h file
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+ static bool my_flag_autorize_cdc_transfert = false;
+ bool my_callback_cdc_enable(void)
+ {
+ my_flag_autorize_cdc_transfert = true;
+ return true;
+ }
+ void my_callback_cdc_disable(void)
+ {
+ my_flag_autorize_cdc_transfert = false;
+ }
+
+ void task(void)
+ {
+ if (my_flag_autorize_cdc_transfert) {
+ udi_cdc_putc('A');
+ udi_cdc_getc();
+ }
+ }
+\endcode
+ *
+ * \subsection udi_cdc_basic_use_case_setup_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following configuration
+ * which is the USB device CDC configuration:
+ * - \code #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for CDC \endcode
+ * \note The USB serial number is mandatory when a CDC interface is used.
+ * - \code #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
+ extern bool my_callback_cdc_enable(void); \endcode
+ * \note After the device enumeration (detecting and identifying USB devices),
+ * the USB host starts the device configuration. When the USB CDC interface
+ * from the device is accepted by the host, the USB host enables this interface and the
+ * UDI_CDC_ENABLE_EXT() callback function is called and return true.
+ * Thus, when this event is received, the data transfer on CDC interface are authorized.
+ * - \code #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
+ extern void my_callback_cdc_disable(void); \endcode
+ * \note When the USB device is unplugged or is reset by the USB host, the USB
+ * interface is disabled and the UDI_CDC_DISABLE_EXT() callback function
+ * is called. Thus, the data transfer must be stopped on CDC interface.
+ * - \code #define UDI_CDC_LOW_RATE \endcode
+ * \note Define it when the transfer CDC Device to Host is a low rate
+ * (<512000 bauds) to reduce CDC buffers size.
+ * - \code #define UDI_CDC_DEFAULT_RATE 115200
+ #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
+ #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
+ #define UDI_CDC_DEFAULT_DATABITS 8 \endcode
+ * \note Default configuration of communication port at startup.
+ * -# Send or wait data on CDC line:
+ * - \code // Waits and gets a value on CDC line
+ int udi_cdc_getc(void);
+ // Reads a RAM buffer on CDC line
+ iram_size_t udi_cdc_read_buf(int* buf, iram_size_t size);
+ // Puts a byte on CDC line
+ int udi_cdc_putc(int value);
+ // Writes a RAM buffer on CDC line
+ iram_size_t udi_cdc_write_buf(const int* buf, iram_size_t size); \endcode
+ *
+ * \section udi_cdc_use_cases Advanced use cases
+ * For more advanced use of the UDI CDC module, see the following use cases:
+ * - \subpage udi_cdc_use_case_composite
+ * - \subpage udc_use_case_1
+ * - \subpage udc_use_case_2
+ * - \subpage udc_use_case_3
+ * - \subpage udc_use_case_4
+ * - \subpage udc_use_case_5
+ * - \subpage udc_use_case_6
+ */
+
+/**
+ * \page udi_cdc_use_case_composite CDC in a composite device
+ *
+ * A USB Composite Device is a USB Device which uses more than one USB class.
+ * In this use case, the "USB CDC (Composite Device)" module is used to
+ * create a USB composite device. Thus, this USB module can be associated with
+ * another "Composite Device" module, like "USB HID Mouse (Composite Device)".
+ *
+ * Also, you can refer to application note
+ * <A href="http://www.atmel.com/dyn/resources/prod_documents/doc8445.pdf">
+ * AVR4902 ASF - USB Composite Device</A>.
+ *
+ * \section udi_cdc_use_case_composite_setup Setup steps
+ * For the setup code of this use case to work, the
+ * \ref udi_cdc_basic_use_case "basic use case" must be followed.
+ *
+ * \section udi_cdc_use_case_composite_usage Usage steps
+ *
+ * \subsection udi_cdc_use_case_composite_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #define USB_DEVICE_EP_CTRL_SIZE 64
+ #define USB_DEVICE_NB_INTERFACE (X+2)
+ #define USB_DEVICE_MAX_EP (X+3)
+
+ #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
+ #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
+ #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
+ #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0
+ #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1
+
+ #define UDI_COMPOSITE_DESC_T \
+ usb_iad_desc_t udi_cdc_iad; \
+ udi_cdc_comm_desc_t udi_cdc_comm; \
+ udi_cdc_data_desc_t udi_cdc_data; \
+ ...
+ #define UDI_COMPOSITE_DESC_FS \
+ .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
+ .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
+ .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \
+ ...
+ #define UDI_COMPOSITE_DESC_HS \
+ .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
+ .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
+ .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \
+ ...
+ #define UDI_COMPOSITE_API \
+ &udi_api_cdc_comm, \
+ &udi_api_cdc_data, \
+ ...
+\endcode
+ *
+ * \subsection udi_cdc_use_case_composite_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required for a USB composite device configuration:
+ * - \code // Endpoint control size, This must be:
+ // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM)
+ // - 64 for a high speed device
+ #define USB_DEVICE_EP_CTRL_SIZE 64
+ // Total Number of interfaces on this USB device.
+ // Add 2 for CDC.
+ #define USB_DEVICE_NB_INTERFACE (X+2)
+ // Total number of endpoints on this USB device.
+ // This must include each endpoint for each interface.
+ // Add 3 for CDC.
+ #define USB_DEVICE_MAX_EP (X+3) \endcode
+ * -# Ensure that conf_usb.h contains the description of
+ * composite device:
+ * - \code // The endpoint numbers chosen by you for the CDC.
+ // The endpoint numbers starting from 1.
+ #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
+ #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
+ #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
+ // The interface index of an interface starting from 0
+ #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0
+ #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB composite device configuration:
+ * - \code // USB Interfaces descriptor structure
+ #define UDI_COMPOSITE_DESC_T \
+ ...
+ usb_iad_desc_t udi_cdc_iad; \
+ udi_cdc_comm_desc_t udi_cdc_comm; \
+ udi_cdc_data_desc_t udi_cdc_data; \
+ ...
+ // USB Interfaces descriptor value for Full Speed
+ #define UDI_COMPOSITE_DESC_FS \
+ ...
+ .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
+ .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
+ .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \
+ ...
+ // USB Interfaces descriptor value for High Speed
+ #define UDI_COMPOSITE_DESC_HS \
+ ...
+ .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
+ .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
+ .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \
+ ...
+ // USB Interface APIs
+ #define UDI_COMPOSITE_API \
+ ...
+ &udi_api_cdc_comm, \
+ &udi_api_cdc_data, \
+ ... \endcode
+ * - \note The descriptors order given in the four lists above must be the
+ * same as the order defined by all interface indexes. The interface index
+ * orders are defined through UDI_X_IFACE_NUMBER defines.\n
+ * Also, the CDC requires a USB Interface Association Descriptor (IAD) for
+ * composite device.
+ */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDI_CDC_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h
new file mode 100755
index 0000000000000000000000000000000000000000..bcb3a65e2499c0096447688f49f3d4fe6108e380
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h
@@ -0,0 +1,152 @@
+/**
+ * \file
+ *
+ * \brief Default CDC configuration for a USB Device with a single interface
+ *
+ * Copyright (c) 2009 - 2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UDI_CDC_CONF_H_
+#define _UDI_CDC_CONF_H_
+
+#include "usb_protocol_cdc.h"
+#include "conf_usb.h"
+
+#ifndef UDI_CDC_PORT_NB
+# define UDI_CDC_PORT_NB 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup udi_cdc_group_single_desc
+ * @{
+ */
+
+//! Control endpoint size (Endpoint 0)
+#define USB_DEVICE_EP_CTRL_SIZE 64
+
+#if XMEGA
+/**
+ * \name Endpoint configuration on XMEGA
+ * The XMEGA supports a IN and OUT endpoint with the same number endpoint,
+ * thus XMEGA can support up to 7 CDC interfaces.
+ */
+//@{
+#define UDI_CDC_DATA_EP_IN_0 ( 1 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_0 ( 2 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_0 ( 2 | USB_EP_DIR_IN) // Notify endpoint
+#define UDI_CDC_DATA_EP_IN_1 ( 3 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_1 ( 4 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_1 ( 4 | USB_EP_DIR_IN) // Notify endpoint
+#define UDI_CDC_DATA_EP_IN_2 ( 5 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_2 ( 6 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_2 ( 6 | USB_EP_DIR_IN) // Notify endpoint
+#define UDI_CDC_DATA_EP_IN_3 ( 7 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_3 ( 8 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_3 ( 8 | USB_EP_DIR_IN) // Notify endpoint
+#define UDI_CDC_DATA_EP_IN_4 ( 9 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_4 (10 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_4 (10 | USB_EP_DIR_IN) // Notify endpoint
+#define UDI_CDC_DATA_EP_IN_5 (11 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_5 (12 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_5 (12 | USB_EP_DIR_IN) // Notify endpoint
+#define UDI_CDC_DATA_EP_IN_6 (13 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_6 (14 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_6 (14 | USB_EP_DIR_IN) // Notify endpoint
+//! 2 endpoints numbers used per CDC interface
+#define USB_DEVICE_MAX_EP (2*UDI_CDC_PORT_NB)
+//@}
+
+#else
+
+/**
+ * \name Default endpoint configuration
+ * The USBB, UDP, UDPHS and UOTGHS interfaces can support up to 2 CDC interfaces.
+ */
+//@{
+# if UDI_CDC_PORT_NB > 2
+# error USBB, UDP, UDPHS and UOTGHS interfaces have not enought endpoints.
+# endif
+#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
+#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
+#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
+# if SAM3U
+ /* For 3U max endpoint size of 4 is 64, use 5 and 6 as bulk tx and rx */
+# define UDI_CDC_DATA_EP_IN_1 (6 | USB_EP_DIR_IN) // TX
+# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX
+# define UDI_CDC_COMM_EP_1 (4 | USB_EP_DIR_IN) // Notify
+# else
+# define UDI_CDC_DATA_EP_IN_1 (4 | USB_EP_DIR_IN) // TX
+# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX
+# define UDI_CDC_COMM_EP_1 (6 | USB_EP_DIR_IN) // Notify
+# endif
+//! 3 endpoints used per CDC interface
+#define USB_DEVICE_MAX_EP (3*UDI_CDC_PORT_NB)
+//@}
+
+#endif
+
+/**
+ * \name Default Interface numbers
+ */
+//@{
+#define UDI_CDC_COMM_IFACE_NUMBER_0 0
+#define UDI_CDC_DATA_IFACE_NUMBER_0 1
+#define UDI_CDC_COMM_IFACE_NUMBER_1 2
+#define UDI_CDC_DATA_IFACE_NUMBER_1 3
+#define UDI_CDC_COMM_IFACE_NUMBER_2 4
+#define UDI_CDC_DATA_IFACE_NUMBER_2 5
+#define UDI_CDC_COMM_IFACE_NUMBER_3 6
+#define UDI_CDC_DATA_IFACE_NUMBER_3 7
+#define UDI_CDC_COMM_IFACE_NUMBER_4 8
+#define UDI_CDC_DATA_IFACE_NUMBER_4 9
+#define UDI_CDC_COMM_IFACE_NUMBER_5 10
+#define UDI_CDC_DATA_IFACE_NUMBER_5 11
+#define UDI_CDC_COMM_IFACE_NUMBER_6 12
+#define UDI_CDC_DATA_IFACE_NUMBER_6 13
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDI_CDC_CONF_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c
new file mode 100755
index 0000000000000000000000000000000000000000..92a7e25aecf93914725e3458ae68dfa765242f1f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c
@@ -0,0 +1,251 @@
+/**
+ * \file
+ *
+ * \brief Default descriptors for a USB Device with a single interface CDC
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "conf_usb.h"
+#include "udd.h"
+#include "udc_desc.h"
+#include "udi_cdc.h"
+
+
+/**
+ * \defgroup udi_cdc_group_single_desc USB device descriptors for a single interface
+ *
+ * The following structures provide the USB device descriptors required for
+ * USB Device with a single interface CDC.
+ *
+ * It is ready to use and do not require more definition.
+ *
+ * @{
+ */
+
+//! Two interfaces for a CDC device
+#define USB_DEVICE_NB_INTERFACE (2*UDI_CDC_PORT_NB)
+
+#ifdef USB_DEVICE_LPM_SUPPORT
+# define USB_VERSION USB_V2_1
+#else
+# define USB_VERSION USB_V2_0
+#endif
+
+//! USB Device Descriptor
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {
+ .bLength = sizeof(usb_dev_desc_t),
+ .bDescriptorType = USB_DT_DEVICE,
+ .bcdUSB = LE16(USB_VERSION),
+#if UDI_CDC_PORT_NB > 1
+ .bDeviceClass = 0,
+#else
+ .bDeviceClass = CDC_CLASS_DEVICE,
+#endif
+ .bDeviceSubClass = 0,
+ .bDeviceProtocol = 0,
+ .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE,
+ .idVendor = LE16(USB_DEVICE_VENDOR_ID),
+ .idProduct = LE16(USB_DEVICE_PRODUCT_ID),
+ .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8)
+ | USB_DEVICE_MINOR_VERSION),
+#ifdef USB_DEVICE_MANUFACTURE_NAME
+ .iManufacturer = 1,
+#else
+ .iManufacturer = 0, // No manufacture string
+#endif
+#ifdef USB_DEVICE_PRODUCT_NAME
+ .iProduct = 2,
+#else
+ .iProduct = 0, // No product string
+#endif
+#ifdef USB_DEVICE_SERIAL_NAME
+ .iSerialNumber = 3,
+#else
+ .iSerialNumber = 0, // No serial string
+#endif
+ .bNumConfigurations = 1
+};
+
+
+#ifdef USB_DEVICE_HS_SUPPORT
+//! USB Device Qualifier Descriptor for HS
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = {
+ .bLength = sizeof(usb_dev_qual_desc_t),
+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
+ .bcdUSB = LE16(USB_VERSION),
+#if UDI_CDC_PORT_NB > 1
+ .bDeviceClass = 0,
+#else
+ .bDeviceClass = CDC_CLASS_DEVICE,
+#endif
+ .bDeviceSubClass = 0,
+ .bDeviceProtocol = 0,
+ .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE,
+ .bNumConfigurations = 1
+};
+#endif
+
+#ifdef USB_DEVICE_LPM_SUPPORT
+//! USB Device Qualifier Descriptor
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_lpm_desc_t udc_device_lpm = {
+ .bos.bLength = sizeof(usb_dev_bos_desc_t),
+ .bos.bDescriptorType = USB_DT_BOS,
+ .bos.wTotalLength = LE16(sizeof(usb_dev_bos_desc_t) + sizeof(usb_dev_capa_ext_desc_t)),
+ .bos.bNumDeviceCaps = 1,
+ .capa_ext.bLength = sizeof(usb_dev_capa_ext_desc_t),
+ .capa_ext.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
+ .capa_ext.bDevCapabilityType = USB_DC_USB20_EXTENSION,
+ .capa_ext.bmAttributes = USB_DC_EXT_LPM, // alfran: modified to fix ASF USB 3.0 incompatibility
+};
+#endif
+
+//! Structure for USB Device Configuration Descriptor
+COMPILER_PACK_SET(1)
+typedef struct {
+ usb_conf_desc_t conf;
+#if UDI_CDC_PORT_NB == 1
+ udi_cdc_comm_desc_t udi_cdc_comm_0;
+ udi_cdc_data_desc_t udi_cdc_data_0;
+#else
+# define UDI_CDC_DESC_STRUCTURE(index, unused) \
+ usb_iad_desc_t udi_cdc_iad_##index; \
+ udi_cdc_comm_desc_t udi_cdc_comm_##index; \
+ udi_cdc_data_desc_t udi_cdc_data_##index;
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_STRUCTURE, ~)
+# undef UDI_CDC_DESC_STRUCTURE
+#endif
+} udc_desc_t;
+COMPILER_PACK_RESET()
+
+//! USB Device Configuration Descriptor filled for full and high speed
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE udc_desc_t udc_desc_fs = {
+ .conf.bLength = sizeof(usb_conf_desc_t),
+ .conf.bDescriptorType = USB_DT_CONFIGURATION,
+ .conf.wTotalLength = LE16(sizeof(udc_desc_t)),
+ .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE,
+ .conf.bConfigurationValue = 1,
+ .conf.iConfiguration = 0,
+ .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
+ .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
+#if UDI_CDC_PORT_NB == 1
+ .udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0,
+ .udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_FS,
+#else
+# define UDI_CDC_DESC_FS(index, unused) \
+ .udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index,\
+ .udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index,\
+ .udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_FS,
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_FS, ~)
+# undef UDI_CDC_DESC_FS
+#endif
+};
+
+#ifdef USB_DEVICE_HS_SUPPORT
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE udc_desc_t udc_desc_hs = {
+ .conf.bLength = sizeof(usb_conf_desc_t),
+ .conf.bDescriptorType = USB_DT_CONFIGURATION,
+ .conf.wTotalLength = LE16(sizeof(udc_desc_t)),
+ .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE,
+ .conf.bConfigurationValue = 1,
+ .conf.iConfiguration = 0,
+ .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
+ .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
+#if UDI_CDC_PORT_NB == 1
+ .udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0,
+ .udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_HS,
+#else
+# define UDI_CDC_DESC_HS(index, unused) \
+ .udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index, \
+ .udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index, \
+ .udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_HS,
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_HS, ~)
+# undef UDI_CDC_DESC_HS
+#endif
+};
+#endif
+
+/**
+ * \name UDC structures which content all USB Device definitions
+ */
+//@{
+
+//! Associate an UDI for each USB interface
+UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = {
+# define UDI_CDC_API(index, unused) \
+ &udi_api_cdc_comm, \
+ &udi_api_cdc_data,
+ MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_API, ~)
+# undef UDI_CDC_API
+};
+
+//! Add UDI with USB Descriptors FS & HS
+UDC_DESC_STORAGE udc_config_speed_t udc_config_fs[1] = { {
+ .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs,
+ .udi_apis = udi_apis,
+}};
+#ifdef USB_DEVICE_HS_SUPPORT
+UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = { {
+ .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs,
+ .udi_apis = udi_apis,
+}};
+#endif
+
+//! Add all information about USB Device in global structure for UDC
+UDC_DESC_STORAGE udc_config_t udc_config = {
+ .confdev_lsfs = &udc_device_desc,
+ .conf_lsfs = udc_config_fs,
+#ifdef USB_DEVICE_HS_SUPPORT
+ .confdev_hs = &udc_device_desc,
+ .qualifier = &udc_device_qual,
+ .conf_hs = udc_config_hs,
+#endif
+#ifdef USB_DEVICE_LPM_SUPPORT
+ .conf_bos = &udc_device_lpm.bos,
+#else
+ .conf_bos = NULL,
+#endif
+};
+
+//@}
+//@}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h
new file mode 100755
index 0000000000000000000000000000000000000000..ec6235af4cd6e0137e408f3601a43ff5050632d9
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h
@@ -0,0 +1,315 @@
+/**
+ * \file
+ *
+ * \brief USB Communication Device Class (CDC) protocol definitions
+ *
+ * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _USB_PROTOCOL_CDC_H_
+#define _USB_PROTOCOL_CDC_H_
+
+#include "compiler.h"
+
+/**
+ * \ingroup usb_protocol_group
+ * \defgroup cdc_protocol_group Communication Device Class Definitions
+ * @{
+ */
+
+/**
+ * \name Possible values of class
+ */
+//@{
+#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class
+#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface
+#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface
+//@}
+
+//! \name USB CDC Subclass IDs
+//@{
+#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model
+#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model
+#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model
+#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model
+#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model
+#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model
+#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model
+//@}
+
+//! \name USB CDC Communication Interface Protocol IDs
+//@{
+#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands
+//@}
+
+//! \name USB CDC Data Interface Protocol IDs
+//@{
+#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI
+#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC
+#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent
+#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol
+#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol
+#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor
+#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures
+#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control
+#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN
+#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands
+#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver
+/**
+ * \brief Describes the Protocol Unit Functional Descriptors [sic]
+ * on Communication Class Interface
+ */
+#define CDC_PROTOCOL_PUFD 0xFE
+//@}
+
+//! \name USB CDC Functional Descriptor Types
+//@{
+#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor
+#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor
+//@}
+
+//! \name USB CDC Functional Descriptor Subtypes
+//@{
+#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor
+#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management
+#define CDC_SCS_ACM 0x02 //!< Abstract Control Management
+#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor
+//@}
+
+//! \name USB CDC Request IDs
+//@{
+#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00
+#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01
+#define USB_REQ_CDC_SET_COMM_FEATURE 0x02
+#define USB_REQ_CDC_GET_COMM_FEATURE 0x03
+#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04
+#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10
+#define USB_REQ_CDC_SET_HOOK_STATE 0x11
+#define USB_REQ_CDC_PULSE_SETUP 0x12
+#define USB_REQ_CDC_SEND_PULSE 0x13
+#define USB_REQ_CDC_SET_PULSE_TIME 0x14
+#define USB_REQ_CDC_RING_AUX_JACK 0x15
+#define USB_REQ_CDC_SET_LINE_CODING 0x20
+#define USB_REQ_CDC_GET_LINE_CODING 0x21
+#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22
+#define USB_REQ_CDC_SEND_BREAK 0x23
+#define USB_REQ_CDC_SET_RINGER_PARMS 0x30
+#define USB_REQ_CDC_GET_RINGER_PARMS 0x31
+#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32
+#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33
+#define USB_REQ_CDC_SET_LINE_PARMS 0x34
+#define USB_REQ_CDC_GET_LINE_PARMS 0x35
+#define USB_REQ_CDC_DIAL_DIGITS 0x36
+#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37
+#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38
+#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39
+#define USB_REQ_CDC_GET_PROFILE 0x3A
+#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41
+#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42
+#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43
+#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44
+#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50
+#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51
+#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52
+#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53
+// Added bNotification codes according cdc spec 1.1 chapter 6.3
+#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09
+#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20
+#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28
+#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29
+//@}
+
+/*
+ * Need to pack structures tightly, or the compiler might insert padding
+ * and violate the spec-mandated layout.
+ */
+COMPILER_PACK_SET(1)
+
+//! \name USB CDC Descriptors
+//@{
+
+
+//! CDC Header Functional Descriptor
+typedef struct {
+ uint8_t bFunctionLength;
+ uint8_t bDescriptorType;
+ uint8_t bDescriptorSubtype;
+ le16_t bcdCDC;
+} usb_cdc_hdr_desc_t;
+
+//! CDC Call Management Functional Descriptor
+typedef struct {
+ uint8_t bFunctionLength;
+ uint8_t bDescriptorType;
+ uint8_t bDescriptorSubtype;
+ uint8_t bmCapabilities;
+ uint8_t bDataInterface;
+} usb_cdc_call_mgmt_desc_t;
+
+//! CDC ACM Functional Descriptor
+typedef struct {
+ uint8_t bFunctionLength;
+ uint8_t bDescriptorType;
+ uint8_t bDescriptorSubtype;
+ uint8_t bmCapabilities;
+} usb_cdc_acm_desc_t;
+
+//! CDC Union Functional Descriptor
+typedef struct {
+ uint8_t bFunctionLength;
+ uint8_t bDescriptorType;
+ uint8_t bDescriptorSubtype;
+ uint8_t bMasterInterface;
+ uint8_t bSlaveInterface0;
+} usb_cdc_union_desc_t;
+
+
+//! \name USB CDC Call Management Capabilities
+//@{
+//! Device handles call management itself
+#define CDC_CALL_MGMT_SUPPORTED (1 << 0)
+//! Device can send/receive call management info over a Data Class interface
+#define CDC_CALL_MGMT_OVER_DCI (1 << 1)
+//@}
+
+//! \name USB CDC ACM Capabilities
+//@{
+//! Device supports the request combination of
+//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
+#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0)
+//! Device supports the request combination of
+//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding,
+//! and the notification Serial_State.
+#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1)
+//! Device supports the request Send_Break
+#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2)
+//! Device supports the notification Network_Connection.
+#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3)
+//@}
+//@}
+
+//! \name USB CDC line control
+//@{
+
+//! \name USB CDC line coding
+//@{
+//! Line Coding structure
+typedef struct {
+ le32_t dwDTERate;
+ uint8_t bCharFormat;
+ uint8_t bParityType;
+ uint8_t bDataBits;
+} usb_cdc_line_coding_t;
+//! Possible values of bCharFormat
+enum cdc_char_format {
+ CDC_STOP_BITS_1 = 0, //!< 1 stop bit
+ CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits
+ CDC_STOP_BITS_2 = 2, //!< 2 stop bits
+};
+//! Possible values of bParityType
+enum cdc_parity {
+ CDC_PAR_NONE = 0, //!< No parity
+ CDC_PAR_ODD = 1, //!< Odd parity
+ CDC_PAR_EVEN = 2, //!< Even parity
+ CDC_PAR_MARK = 3, //!< Parity forced to 0 (space)
+ CDC_PAR_SPACE = 4, //!< Parity forced to 1 (mark)
+};
+//@}
+
+//! \name USB CDC control signals
+//! spec 1.1 chapter 6.2.14
+//@{
+
+//! Control signal structure
+typedef struct {
+ uint16_t value;
+} usb_cdc_control_signal_t;
+
+//! \name Possible values in usb_cdc_control_signal_t
+//@{
+//! Carrier control for half duplex modems.
+//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS.
+//! The device ignores the value of this bit
+//! when operating in full duplex mode.
+#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1)
+//! Indicates to DCE if DTE is present or not.
+//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
+#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0)
+//@}
+//@}
+
+
+//! \name USB CDC notification message
+//@{
+
+typedef struct {
+ uint8_t bmRequestType;
+ uint8_t bNotification;
+ le16_t wValue;
+ le16_t wIndex;
+ le16_t wLength;
+} usb_cdc_notify_msg_t;
+
+//! \name USB CDC serial state
+//@{*
+
+//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5)
+typedef struct {
+ usb_cdc_notify_msg_t header;
+ le16_t value;
+} usb_cdc_notify_serial_state_t;
+
+//! \name Possible values in usb_cdc_notify_serial_state_t
+//@{
+#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1<<0))
+#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1<<1))
+#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1<<2))
+#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1<<3))
+#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1<<4))
+#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1<<5))
+#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1<<6))
+//@}
+//! @}
+
+//! @}
+
+COMPILER_PACK_RESET()
+
+//! @}
+
+#endif // _USB_PROTOCOL_CDC_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc.c
new file mode 100755
index 0000000000000000000000000000000000000000..461a342b666affc5f32f850f6b29e78311b9b423
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc.c
@@ -0,0 +1,1138 @@
+/**
+ * \file
+ *
+ * \brief USB Device Controller (UDC)
+ *
+ * Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "udd.h"
+#include "udc_desc.h"
+#include "udi.h"
+#include "udc.h"
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_group_interne Implementation of UDC
+ *
+ * Internal implementation
+ * @{
+ */
+
+//! \name Internal variables to manage the USB device
+//! @{
+
+//! Device status state (see enum usb_device_status in usb_protocol.h)
+static le16_t udc_device_status;
+
+//! Device Configuration number selected by the USB host
+static uint8_t udc_num_configuration = 0;
+
+//! Pointer on the selected speed device configuration
+static udc_config_speed_t UDC_DESC_STORAGE *udc_ptr_conf;
+
+//! Pointer on interface descriptor used by SETUP request.
+static usb_iface_desc_t UDC_DESC_STORAGE *udc_ptr_iface;
+
+//! @}
+
+
+//! \name Internal structure to store the USB device main strings
+//! @{
+
+/**
+ * \brief Language ID of USB device (US ID by default)
+ */
+COMPILER_WORD_ALIGNED
+static UDC_DESC_STORAGE usb_str_lgid_desc_t udc_string_desc_languageid = {
+ .desc.bLength = sizeof(usb_str_lgid_desc_t),
+ .desc.bDescriptorType = USB_DT_STRING,
+ .string = {LE16(USB_LANGID_EN_US)}
+};
+
+/**
+ * \brief USB device manufacture name storage
+ * String is allocated only if USB_DEVICE_MANUFACTURE_NAME is declared
+ * by usb application configuration
+ */
+#ifdef USB_DEVICE_MANUFACTURE_NAME
+static uint8_t udc_string_manufacturer_name[] = USB_DEVICE_MANUFACTURE_NAME;
+# define USB_DEVICE_MANUFACTURE_NAME_SIZE \
+ (sizeof(udc_string_manufacturer_name)-1)
+#else
+# define USB_DEVICE_MANUFACTURE_NAME_SIZE 0
+#endif
+
+/**
+ * \brief USB device product name storage
+ * String is allocated only if USB_DEVICE_PRODUCT_NAME is declared
+ * by usb application configuration
+ */
+#ifdef USB_DEVICE_PRODUCT_NAME
+static uint8_t udc_string_product_name[] = USB_DEVICE_PRODUCT_NAME;
+# define USB_DEVICE_PRODUCT_NAME_SIZE (sizeof(udc_string_product_name)-1)
+#else
+# define USB_DEVICE_PRODUCT_NAME_SIZE 0
+#endif
+
+/**
+ * \brief Get USB device serial number
+ *
+ * Use the define USB_DEVICE_SERIAL_NAME to set static serial number.
+ *
+ * For dynamic serial number set the define USB_DEVICE_GET_SERIAL_NAME_POINTER
+ * to a suitable pointer. This will also require the serial number length
+ * define USB_DEVICE_GET_SERIAL_NAME_LENGTH.
+ */
+#if defined USB_DEVICE_GET_SERIAL_NAME_POINTER
+ static const uint8_t *udc_get_string_serial_name(void)
+ {
+ return (const uint8_t *)USB_DEVICE_GET_SERIAL_NAME_POINTER;
+ }
+# define USB_DEVICE_SERIAL_NAME_SIZE \
+ USB_DEVICE_GET_SERIAL_NAME_LENGTH
+#elif defined USB_DEVICE_SERIAL_NAME
+ static const uint8_t *udc_get_string_serial_name(void)
+ {
+ return (const uint8_t *)USB_DEVICE_SERIAL_NAME;
+ }
+# define USB_DEVICE_SERIAL_NAME_SIZE \
+ (sizeof(USB_DEVICE_SERIAL_NAME)-1)
+#else
+# define USB_DEVICE_SERIAL_NAME_SIZE 0
+#endif
+
+/**
+ * \brief USB device string descriptor
+ * Structure used to transfer ASCII strings to USB String descriptor structure.
+ */
+struct udc_string_desc_t {
+ usb_str_desc_t header;
+ le16_t string[Max(Max(USB_DEVICE_MANUFACTURE_NAME_SIZE, \
+ USB_DEVICE_PRODUCT_NAME_SIZE), USB_DEVICE_SERIAL_NAME_SIZE)];
+};
+COMPILER_WORD_ALIGNED
+static UDC_DESC_STORAGE struct udc_string_desc_t udc_string_desc = {
+ .header.bDescriptorType = USB_DT_STRING
+};
+//! @}
+
+usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void)
+{
+ return udc_ptr_iface;
+}
+
+/**
+ * \brief Returns a value to check the end of USB Configuration descriptor
+ *
+ * \return address after the last byte of USB Configuration descriptor
+ */
+static usb_conf_desc_t UDC_DESC_STORAGE *udc_get_eof_conf(void)
+{
+ return (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *)
+ udc_ptr_conf->desc +
+ le16_to_cpu(udc_ptr_conf->desc->wTotalLength));
+}
+
+#if (0!=USB_DEVICE_MAX_EP)
+/**
+ * \brief Search specific descriptor in global interface descriptor
+ *
+ * \param desc Address of interface descriptor
+ * or previous specific descriptor found
+ * \param desc_id Descriptor ID to search
+ *
+ * \return address of specific descriptor found
+ * \return NULL if it is the end of global interface descriptor
+ */
+static usb_conf_desc_t UDC_DESC_STORAGE *udc_next_desc_in_iface(usb_conf_desc_t
+ UDC_DESC_STORAGE * desc, uint8_t desc_id)
+{
+ usb_conf_desc_t UDC_DESC_STORAGE *ptr_eof_desc;
+
+ ptr_eof_desc = udc_get_eof_conf();
+ // Go to next descriptor
+ desc = (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) desc +
+ desc->bLength);
+ // Check the end of configuration descriptor
+ while (ptr_eof_desc > desc) {
+ // If new interface descriptor is found,
+ // then it is the end of the current global interface descriptor
+ if (USB_DT_INTERFACE == desc->bDescriptorType) {
+ break; // End of global interface descriptor
+ }
+ if (desc_id == desc->bDescriptorType) {
+ return desc; // Specific descriptor found
+ }
+ // Go to next descriptor
+ desc = (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) desc +
+ desc->bLength);
+ }
+ return NULL; // No specific descriptor found
+}
+#endif
+
+/**
+ * \brief Search an interface descriptor
+ * This routine updates the internal pointer udc_ptr_iface.
+ *
+ * \param iface_num Interface number to find in Configuration Descriptor
+ * \param setting_num Setting number of interface to find
+ *
+ * \return 1 if found or 0 if not found
+ */
+static bool udc_update_iface_desc(uint8_t iface_num, uint8_t setting_num)
+{
+ usb_conf_desc_t UDC_DESC_STORAGE *ptr_end_desc;
+
+ if (0 == udc_num_configuration) {
+ return false;
+ }
+
+ if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) {
+ return false;
+ }
+
+ // Start at the beginning of configuration descriptor
+ udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *)
+ udc_ptr_conf->desc;
+
+ // Check the end of configuration descriptor
+ ptr_end_desc = udc_get_eof_conf();
+ while (ptr_end_desc >
+ (UDC_DESC_STORAGE usb_conf_desc_t *) udc_ptr_iface) {
+ if (USB_DT_INTERFACE == udc_ptr_iface->bDescriptorType) {
+ // A interface descriptor is found
+ // Check interface and alternate setting number
+ if ((iface_num == udc_ptr_iface->bInterfaceNumber) &&
+ (setting_num ==
+ udc_ptr_iface->bAlternateSetting)) {
+ return true; // Interface found
+ }
+ }
+ // Go to next descriptor
+ udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *) (
+ (uint8_t *) udc_ptr_iface +
+ udc_ptr_iface->bLength);
+ }
+ return false; // Interface not found
+}
+
+/**
+ * \brief Disables an usb device interface (UDI)
+ * This routine call the UDI corresponding to interface number
+ *
+ * \param iface_num Interface number to disable
+ *
+ * \return 1 if it is done or 0 if interface is not found
+ */
+static bool udc_iface_disable(uint8_t iface_num)
+{
+ udi_api_t UDC_DESC_STORAGE *udi_api;
+
+ // Select first alternate setting of the interface
+ // to update udc_ptr_iface before call iface->getsetting()
+ if (!udc_update_iface_desc(iface_num, 0)) {
+ return false;
+ }
+
+ // Select the interface with the current alternate setting
+ udi_api = udc_ptr_conf->udi_apis[iface_num];
+
+#if (0!=USB_DEVICE_MAX_EP)
+ if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) {
+ return false;
+ }
+
+ // Start at the beginning of interface descriptor
+ {
+ usb_ep_desc_t UDC_DESC_STORAGE *ep_desc;
+ ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) udc_ptr_iface;
+ while (1) {
+ // Search Endpoint descriptor included in global interface descriptor
+ ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *)
+ udc_next_desc_in_iface((UDC_DESC_STORAGE
+ usb_conf_desc_t *)
+ ep_desc, USB_DT_ENDPOINT);
+ if (NULL == ep_desc) {
+ break;
+ }
+ // Free the endpoint used by the interface
+ udd_ep_free(ep_desc->bEndpointAddress);
+ }
+ }
+#endif
+
+ // Disable interface
+ udi_api->disable();
+ return true;
+}
+
+/**
+ * \brief Enables an usb device interface (UDI)
+ * This routine calls the UDI corresponding
+ * to the interface and setting number.
+ *
+ * \param iface_num Interface number to enable
+ * \param setting_num Setting number to enable
+ *
+ * \return 1 if it is done or 0 if interface is not found
+ */
+static bool udc_iface_enable(uint8_t iface_num, uint8_t setting_num)
+{
+ // Select the interface descriptor
+ if (!udc_update_iface_desc(iface_num, setting_num)) {
+ return false;
+ }
+
+#if (0!=USB_DEVICE_MAX_EP)
+ usb_ep_desc_t UDC_DESC_STORAGE *ep_desc;
+
+ // Start at the beginning of the global interface descriptor
+ ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) udc_ptr_iface;
+ while (1) {
+ // Search Endpoint descriptor included in the global interface descriptor
+ ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *)
+ udc_next_desc_in_iface((UDC_DESC_STORAGE
+ usb_conf_desc_t *) ep_desc,
+ USB_DT_ENDPOINT);
+ if (NULL == ep_desc)
+ break;
+ // Alloc the endpoint used by the interface
+ if (!udd_ep_alloc(ep_desc->bEndpointAddress,
+ ep_desc->bmAttributes,
+ le16_to_cpu
+ (ep_desc->wMaxPacketSize))) {
+ return false;
+ }
+ }
+#endif
+ // Enable the interface
+ return udc_ptr_conf->udi_apis[iface_num]->enable();
+}
+
+/*! \brief Start the USB Device stack
+ */
+void udc_start(void)
+{
+ udd_enable();
+}
+
+/*! \brief Stop the USB Device stack
+ */
+void udc_stop(void)
+{
+ udd_disable();
+ udc_reset();
+}
+
+/**
+ * \brief Reset the current configuration of the USB device,
+ * This routines can be called by UDD when a RESET on the USB line occurs.
+ */
+void udc_reset(void)
+{
+ uint8_t iface_num;
+
+ if (udc_num_configuration) {
+ for (iface_num = 0;
+ iface_num < udc_ptr_conf->desc->bNumInterfaces;
+ iface_num++) {
+ udc_iface_disable(iface_num);
+ }
+ }
+ udc_num_configuration = 0;
+#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \
+ == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP))
+ if (CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP) & udc_device_status) {
+ // Remote wakeup is enabled then disable it
+ UDC_REMOTEWAKEUP_DISABLE();
+ }
+#endif
+ udc_device_status =
+#if (USB_DEVICE_ATTR & USB_CONFIG_ATTR_SELF_POWERED)
+ CPU_TO_LE16(USB_DEV_STATUS_SELF_POWERED);
+#else
+ CPU_TO_LE16(USB_DEV_STATUS_BUS_POWERED);
+#endif
+}
+
+void udc_sof_notify(void)
+{
+ uint8_t iface_num;
+
+ if (udc_num_configuration) {
+ for (iface_num = 0;
+ iface_num < udc_ptr_conf->desc->bNumInterfaces;
+ iface_num++) {
+ if (udc_ptr_conf->udi_apis[iface_num]->sof_notify != NULL) {
+ udc_ptr_conf->udi_apis[iface_num]->sof_notify();
+ }
+ }
+ }
+}
+
+/**
+ * \brief Standard device request to get device status
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_get_status(void)
+{
+ if (udd_g_ctrlreq.req.wLength != sizeof(udc_device_status)) {
+ return false;
+ }
+
+ udd_set_setup_payload( (uint8_t *) & udc_device_status,
+ sizeof(udc_device_status));
+ return true;
+}
+
+#if (0!=USB_DEVICE_MAX_EP)
+/**
+ * \brief Standard endpoint request to get endpoint status
+ *
+ * \return true if success
+ */
+static bool udc_req_std_ep_get_status(void)
+{
+ static le16_t udc_ep_status;
+
+ if (udd_g_ctrlreq.req.wLength != sizeof(udc_ep_status)) {
+ return false;
+ }
+
+ udc_ep_status = udd_ep_is_halted(udd_g_ctrlreq.req.
+ wIndex & 0xFF) ? CPU_TO_LE16(USB_EP_STATUS_HALTED) : 0;
+
+ udd_set_setup_payload( (uint8_t *) & udc_ep_status,
+ sizeof(udc_ep_status));
+ return true;
+}
+#endif
+
+/**
+ * \brief Standard device request to change device status
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_clear_feature(void)
+{
+ if (udd_g_ctrlreq.req.wLength) {
+ return false;
+ }
+
+ if (udd_g_ctrlreq.req.wValue == USB_DEV_FEATURE_REMOTE_WAKEUP) {
+ udc_device_status &= CPU_TO_LE16(~(uint32_t)USB_DEV_STATUS_REMOTEWAKEUP);
+#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \
+ == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP))
+ UDC_REMOTEWAKEUP_DISABLE();
+#endif
+ return true;
+ }
+ return false;
+}
+
+#if (0!=USB_DEVICE_MAX_EP)
+/**
+ * \brief Standard endpoint request to clear endpoint feature
+ *
+ * \return true if success
+ */
+static bool udc_req_std_ep_clear_feature(void)
+{
+ if (udd_g_ctrlreq.req.wLength) {
+ return false;
+ }
+
+ if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) {
+ return udd_ep_clear_halt(udd_g_ctrlreq.req.wIndex & 0xFF);
+ }
+ return false;
+}
+#endif
+
+/**
+ * \brief Standard device request to set a feature
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_set_feature(void)
+{
+ if (udd_g_ctrlreq.req.wLength) {
+ return false;
+ }
+
+ switch (udd_g_ctrlreq.req.wValue) {
+
+ case USB_DEV_FEATURE_REMOTE_WAKEUP:
+#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \
+ == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP))
+ udc_device_status |= CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP);
+ UDC_REMOTEWAKEUP_ENABLE();
+ return true;
+#else
+ return false;
+#endif
+
+#ifdef USB_DEVICE_HS_SUPPORT
+ case USB_DEV_FEATURE_TEST_MODE:
+ if (!udd_is_high_speed()) {
+ break;
+ }
+ if (udd_g_ctrlreq.req.wIndex & 0xff) {
+ break;
+ }
+ // Unconfigure the device, terminating all ongoing requests
+ udc_reset();
+ switch ((udd_g_ctrlreq.req.wIndex >> 8) & 0xFF) {
+ case USB_DEV_TEST_MODE_J:
+ udd_g_ctrlreq.callback = udd_test_mode_j;
+ return true;
+
+ case USB_DEV_TEST_MODE_K:
+ udd_g_ctrlreq.callback = udd_test_mode_k;
+ return true;
+
+ case USB_DEV_TEST_MODE_SE0_NAK:
+ udd_g_ctrlreq.callback = udd_test_mode_se0_nak;
+ return true;
+
+ case USB_DEV_TEST_MODE_PACKET:
+ udd_g_ctrlreq.callback = udd_test_mode_packet;
+ return true;
+
+ case USB_DEV_TEST_MODE_FORCE_ENABLE: // Only for downstream facing hub ports
+ default:
+ break;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ return false;
+}
+
+/**
+ * \brief Standard endpoint request to halt an endpoint
+ *
+ * \return true if success
+ */
+#if (0!=USB_DEVICE_MAX_EP)
+static bool udc_req_std_ep_set_feature(void)
+{
+ if (udd_g_ctrlreq.req.wLength) {
+ return false;
+ }
+ if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) {
+ udd_ep_abort(udd_g_ctrlreq.req.wIndex & 0xFF);
+ return udd_ep_set_halt(udd_g_ctrlreq.req.wIndex & 0xFF);
+ }
+ return false;
+}
+#endif
+
+/**
+ * \brief Change the address of device
+ * Callback called at the end of request set address
+ */
+static void udc_valid_address(void)
+{
+ udd_set_address(udd_g_ctrlreq.req.wValue & 0x7F);
+}
+
+/**
+ * \brief Standard device request to set device address
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_set_address(void)
+{
+ if (udd_g_ctrlreq.req.wLength) {
+ return false;
+ }
+
+ // The address must be changed at the end of setup request after the handshake
+ // then we use a callback to change address
+ udd_g_ctrlreq.callback = udc_valid_address;
+ return true;
+}
+
+/**
+ * \brief Standard device request to get device string descriptor
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_get_str_desc(void)
+{
+ uint8_t i;
+ const uint8_t *str;
+ uint8_t str_length = 0;
+
+ // Link payload pointer to the string corresponding at request
+ switch (udd_g_ctrlreq.req.wValue & 0xff) {
+ case 0:
+ udd_set_setup_payload((uint8_t *) &udc_string_desc_languageid,
+ sizeof(udc_string_desc_languageid));
+ break;
+
+#ifdef USB_DEVICE_MANUFACTURE_NAME
+ case 1:
+ str_length = USB_DEVICE_MANUFACTURE_NAME_SIZE;
+ str = udc_string_manufacturer_name;
+ break;
+#endif
+#ifdef USB_DEVICE_PRODUCT_NAME
+ case 2:
+ str_length = USB_DEVICE_PRODUCT_NAME_SIZE;
+ str = udc_string_product_name;
+ break;
+#endif
+#if defined USB_DEVICE_SERIAL_NAME || defined USB_DEVICE_GET_SERIAL_NAME_POINTER
+ case 3:
+ str_length = USB_DEVICE_SERIAL_NAME_SIZE;
+ str = udc_get_string_serial_name();
+ break;
+#endif
+ default:
+#ifdef UDC_GET_EXTRA_STRING
+ if (UDC_GET_EXTRA_STRING()) {
+ break;
+ }
+#endif
+ return false;
+ }
+
+ if (str_length) {
+ for(i = 0; i < str_length; i++) {
+ udc_string_desc.string[i] = cpu_to_le16((le16_t)str[i]);
+ }
+
+ udc_string_desc.header.bLength = 2 + (str_length) * 2;
+ udd_set_setup_payload(
+ (uint8_t *) &udc_string_desc,
+ udc_string_desc.header.bLength);
+ }
+
+ return true;
+}
+
+/**
+ * \brief Standard device request to get descriptors about USB device
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_get_descriptor(void)
+{
+ uint8_t conf_num;
+
+ conf_num = udd_g_ctrlreq.req.wValue & 0xff;
+
+ // Check descriptor ID
+ switch ((uint8_t) (udd_g_ctrlreq.req.wValue >> 8)) {
+ case USB_DT_DEVICE:
+ // Device descriptor requested
+#ifdef USB_DEVICE_HS_SUPPORT
+ if (!udd_is_high_speed()) {
+ udd_set_setup_payload(
+ (uint8_t *) udc_config.confdev_hs,
+ udc_config.confdev_hs->bLength);
+ } else
+#endif
+ {
+ udd_set_setup_payload(
+ (uint8_t *) udc_config.confdev_lsfs,
+ udc_config.confdev_lsfs->bLength);
+ }
+ break;
+
+ case USB_DT_CONFIGURATION:
+ // Configuration descriptor requested
+#ifdef USB_DEVICE_HS_SUPPORT
+ if (udd_is_high_speed()) {
+ // HS descriptor
+ if (conf_num >= udc_config.confdev_hs->
+ bNumConfigurations) {
+ return false;
+ }
+ udd_set_setup_payload(
+ (uint8_t *)udc_config.conf_hs[conf_num].desc,
+ le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength));
+ } else
+#endif
+ {
+ // FS descriptor
+ if (conf_num >= udc_config.confdev_lsfs->
+ bNumConfigurations) {
+ return false;
+ }
+ udd_set_setup_payload(
+ (uint8_t *)udc_config.conf_lsfs[conf_num].desc,
+ le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength));
+ }
+ ((usb_conf_desc_t *) udd_g_ctrlreq.payload)->bDescriptorType =
+ USB_DT_CONFIGURATION;
+ break;
+
+#ifdef USB_DEVICE_HS_SUPPORT
+ case USB_DT_DEVICE_QUALIFIER:
+ // Device qualifier descriptor requested
+ udd_set_setup_payload( (uint8_t *) udc_config.qualifier,
+ udc_config.qualifier->bLength);
+ break;
+
+ case USB_DT_OTHER_SPEED_CONFIGURATION:
+ // Other configuration descriptor requested
+ if (!udd_is_high_speed()) {
+ // HS descriptor
+ if (conf_num >= udc_config.confdev_hs->
+ bNumConfigurations) {
+ return false;
+ }
+ udd_set_setup_payload(
+ (uint8_t *)udc_config.conf_hs[conf_num].desc,
+ le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength));
+ } else {
+ // FS descriptor
+ if (conf_num >= udc_config.confdev_lsfs->
+ bNumConfigurations) {
+ return false;
+ }
+ udd_set_setup_payload(
+ (uint8_t *)udc_config.conf_lsfs[conf_num].desc,
+ le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength));
+ }
+ ((usb_conf_desc_t *) udd_g_ctrlreq.payload)->bDescriptorType =
+ USB_DT_OTHER_SPEED_CONFIGURATION;
+ break;
+#endif
+
+ case USB_DT_BOS:
+ // Device BOS descriptor requested
+ if (udc_config.conf_bos == NULL) {
+ return false;
+ }
+ udd_set_setup_payload( (uint8_t *) udc_config.conf_bos,
+ udc_config.conf_bos->wTotalLength);
+ break;
+
+ case USB_DT_STRING:
+ // String descriptor requested
+ if (!udc_req_std_dev_get_str_desc()) {
+ return false;
+ }
+ break;
+
+ default:
+ // Unknown descriptor requested
+ return false;
+ }
+ // if the descriptor is larger than length requested, then reduce it
+ if (udd_g_ctrlreq.req.wLength < udd_g_ctrlreq.payload_size) {
+ udd_g_ctrlreq.payload_size = udd_g_ctrlreq.req.wLength;
+ }
+ return true;
+}
+
+/**
+ * \brief Standard device request to get configuration number
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_get_configuration(void)
+{
+ if (udd_g_ctrlreq.req.wLength != 1) {
+ return false;
+ }
+
+ udd_set_setup_payload(&udc_num_configuration,1);
+ return true;
+}
+
+/**
+ * \brief Standard device request to enable a configuration
+ *
+ * \return true if success
+ */
+static bool udc_req_std_dev_set_configuration(void)
+{
+ uint8_t iface_num;
+
+ // Check request length
+ if (udd_g_ctrlreq.req.wLength) {
+ return false;
+ }
+ // Authorize configuration only if the address is valid
+ if (!udd_getaddress()) {
+ return false;
+ }
+ // Check the configuration number requested
+#ifdef USB_DEVICE_HS_SUPPORT
+ if (udd_is_high_speed()) {
+ // HS descriptor
+ if ((udd_g_ctrlreq.req.wValue & 0xFF) >
+ udc_config.confdev_hs->bNumConfigurations) {
+ return false;
+ }
+ } else
+#endif
+ {
+ // FS descriptor
+ if ((udd_g_ctrlreq.req.wValue & 0xFF) >
+ udc_config.confdev_lsfs->bNumConfigurations) {
+ return false;
+ }
+ }
+
+ // Reset current configuration
+ udc_reset();
+
+ // Enable new configuration
+ udc_num_configuration = udd_g_ctrlreq.req.wValue & 0xFF;
+ if (udc_num_configuration == 0) {
+ return true; // Default empty configuration requested
+ }
+ // Update pointer of the configuration descriptor
+#ifdef USB_DEVICE_HS_SUPPORT
+ if (udd_is_high_speed()) {
+ // HS descriptor
+ udc_ptr_conf = &udc_config.conf_hs[udc_num_configuration - 1];
+ } else
+#endif
+ {
+ // FS descriptor
+ udc_ptr_conf = &udc_config.conf_lsfs[udc_num_configuration - 1];
+ }
+ // Enable all interfaces of the selected configuration
+ for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces;
+ iface_num++) {
+ if (!udc_iface_enable(iface_num, 0)) {
+ return false;
+ }
+ }
+ return true;
+}
+
+/**
+ * \brief Standard interface request
+ * to get the alternate setting number of an interface
+ *
+ * \return true if success
+ */
+static bool udc_req_std_iface_get_setting(void)
+{
+ static uint8_t udc_iface_setting;
+ uint8_t iface_num;
+ udi_api_t UDC_DESC_STORAGE *udi_api;
+
+ if (udd_g_ctrlreq.req.wLength != 1) {
+ return false; // Error in request
+ }
+ if (!udc_num_configuration) {
+ return false; // The device is not is configured state yet
+ }
+
+ // Check the interface number included in the request
+ iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
+ if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) {
+ return false;
+ }
+
+ // Select first alternate setting of the interface to update udc_ptr_iface
+ // before call iface->getsetting()
+ if (!udc_update_iface_desc(iface_num, 0)) {
+ return false;
+ }
+ // Get alternate setting from UDI
+ udi_api = udc_ptr_conf->udi_apis[iface_num];
+ udc_iface_setting = udi_api->getsetting();
+
+ // Link value to payload pointer of request
+ udd_set_setup_payload(&udc_iface_setting,1);
+ return true;
+}
+
+/**
+ * \brief Standard interface request
+ * to set an alternate setting of an interface
+ *
+ * \return true if success
+ */
+static bool udc_req_std_iface_set_setting(void)
+{
+ uint8_t iface_num, setting_num;
+
+ if (udd_g_ctrlreq.req.wLength) {
+ return false; // Error in request
+ }
+ if (!udc_num_configuration) {
+ return false; // The device is not is configured state yet
+ }
+
+ iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
+ setting_num = udd_g_ctrlreq.req.wValue & 0xFF;
+
+ // Disable current setting
+ if (!udc_iface_disable(iface_num)) {
+ return false;
+ }
+
+ // Enable new setting
+ return udc_iface_enable(iface_num, setting_num);
+}
+
+/**
+ * \brief Main routine to manage the standard USB SETUP request
+ *
+ * \return true if the request is supported
+ */
+static bool udc_reqstd(void)
+{
+ if (Udd_setup_is_in()) {
+ // GET Standard Requests
+ if (udd_g_ctrlreq.req.wLength == 0) {
+ return false; // Error for USB host
+ }
+
+ if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) {
+ // Standard Get Device request
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_GET_STATUS:
+ return udc_req_std_dev_get_status();
+ case USB_REQ_GET_DESCRIPTOR:
+ return udc_req_std_dev_get_descriptor();
+ case USB_REQ_GET_CONFIGURATION:
+ return udc_req_std_dev_get_configuration();
+ default:
+ break;
+ }
+ }
+
+ if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) {
+ // Standard Get Interface request
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_GET_INTERFACE:
+ return udc_req_std_iface_get_setting();
+ default:
+ break;
+ }
+ }
+#if (0!=USB_DEVICE_MAX_EP)
+ if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) {
+ // Standard Get Endpoint request
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_GET_STATUS:
+ return udc_req_std_ep_get_status();
+ default:
+ break;
+ }
+ }
+#endif
+ } else {
+ // SET Standard Requests
+ if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) {
+ // Standard Set Device request
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ return udc_req_std_dev_set_address();
+ case USB_REQ_CLEAR_FEATURE:
+ return udc_req_std_dev_clear_feature();
+ case USB_REQ_SET_FEATURE:
+ return udc_req_std_dev_set_feature();
+ case USB_REQ_SET_CONFIGURATION:
+ return udc_req_std_dev_set_configuration();
+ case USB_REQ_SET_DESCRIPTOR:
+ /* Not supported (defined as optional by the USB 2.0 spec) */
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) {
+ // Standard Set Interface request
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_SET_INTERFACE:
+ return udc_req_std_iface_set_setting();
+ default:
+ break;
+ }
+ }
+#if (0!=USB_DEVICE_MAX_EP)
+ if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) {
+ // Standard Set Endpoint request
+ switch (udd_g_ctrlreq.req.bRequest) {
+ case USB_REQ_CLEAR_FEATURE:
+ return udc_req_std_ep_clear_feature();
+ case USB_REQ_SET_FEATURE:
+ return udc_req_std_ep_set_feature();
+ default:
+ break;
+ }
+ }
+#endif
+ }
+ return false;
+}
+
+/**
+ * \brief Send the SETUP interface request to UDI
+ *
+ * \return true if the request is supported
+ */
+static bool udc_req_iface(void)
+{
+ uint8_t iface_num;
+ udi_api_t UDC_DESC_STORAGE *udi_api;
+
+ if (0 == udc_num_configuration) {
+ return false; // The device is not is configured state yet
+ }
+ // Check interface number
+ iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
+ if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) {
+ return false;
+ }
+
+ //* To update udc_ptr_iface with the selected interface in request
+ // Select first alternate setting of interface to update udc_ptr_iface
+ // before calling udi_api->getsetting()
+ if (!udc_update_iface_desc(iface_num, 0)) {
+ return false;
+ }
+ // Select the interface with the current alternate setting
+ udi_api = udc_ptr_conf->udi_apis[iface_num];
+ if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) {
+ return false;
+ }
+
+ // Send the SETUP request to the UDI corresponding to the interface number
+ return udi_api->setup();
+}
+
+/**
+ * \brief Send the SETUP interface request to UDI
+ *
+ * \return true if the request is supported
+ */
+static bool udc_req_ep(void)
+{
+ uint8_t iface_num;
+ udi_api_t UDC_DESC_STORAGE *udi_api;
+
+ if (0 == udc_num_configuration) {
+ return false; // The device is not is configured state yet
+ }
+ // Send this request on all enabled interfaces
+ iface_num = udd_g_ctrlreq.req.wIndex & 0xFF;
+ for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces;
+ iface_num++) {
+ // Select the interface with the current alternate setting
+ udi_api = udc_ptr_conf->udi_apis[iface_num];
+ if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) {
+ return false;
+ }
+
+ // Send the SETUP request to the UDI
+ if (udi_api->setup()) {
+ return true;
+ }
+ }
+ return false;
+}
+
+/**
+ * \brief Main routine to manage the USB SETUP request.
+ *
+ * This function parses a USB SETUP request and submits an appropriate
+ * response back to the host or, in the case of SETUP OUT requests
+ * with data, sets up a buffer for receiving the data payload.
+ *
+ * The main standard requests defined by the USB 2.0 standard are handled
+ * internally. The interface requests are sent to UDI, and the specific request
+ * sent to a specific application callback.
+ *
+ * \return true if the request is supported, else the request is stalled by UDD
+ */
+bool udc_process_setup(void)
+{
+ // By default no data (receive/send) and no callbacks registered
+ udd_g_ctrlreq.payload_size = 0;
+ udd_g_ctrlreq.callback = NULL;
+ udd_g_ctrlreq.over_under_run = NULL;
+
+ if (Udd_setup_is_in()) {
+ if (udd_g_ctrlreq.req.wLength == 0) {
+ return false; // Error from USB host
+ }
+ }
+
+ // If standard request then try to decode it in UDC
+ if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) {
+ if (udc_reqstd()) {
+ return true;
+ }
+ }
+
+ // If interface request then try to decode it in UDI
+ if (Udd_setup_recipient() == USB_REQ_RECIP_INTERFACE) {
+ if (udc_req_iface()) {
+ return true;
+ }
+ }
+
+ // If endpoint request then try to decode it in UDI
+ if (Udd_setup_recipient() == USB_REQ_RECIP_ENDPOINT) {
+ if (udc_req_ep()) {
+ return true;
+ }
+ }
+
+ // Here SETUP request unknown by UDC and UDIs
+#ifdef USB_DEVICE_SPECIFIC_REQUEST
+ // Try to decode it in specific callback
+ return USB_DEVICE_SPECIFIC_REQUEST(); // Ex: Vendor request,...
+#else
+ return false;
+#endif
+}
+
+//! @}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc.h
new file mode 100755
index 0000000000000000000000000000000000000000..93c0cdd568f6eb131294119a4f2f8f0f448dd1c9
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc.h
@@ -0,0 +1,694 @@
+/**
+ * \file
+ *
+ * \brief Interface of the USB Device Controller (UDC)
+ *
+ * Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UDC_H_
+#define _UDC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "udc_desc.h"
+#include "udd.h"
+
+#if USB_DEVICE_VENDOR_ID == 0
+# error USB_DEVICE_VENDOR_ID cannot be equal to 0
+#endif
+
+#if USB_DEVICE_PRODUCT_ID == 0
+# error USB_DEVICE_PRODUCT_ID cannot be equal to 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup udc_group USB Device Controller (UDC)
+ *
+ * The UDC provides a high-level abstraction of the usb device.
+ * You can use these functions to control the main device state
+ * (start/attach/wakeup).
+ *
+ * \section USB_DEVICE_CONF USB Device Custom configuration
+ * The following USB Device configuration must be included in the conf_usb.h
+ * file of the application.
+ *
+ * USB_DEVICE_VENDOR_ID (Word)<br>
+ * Vendor ID provided by USB org (ATMEL 0x03EB).
+ *
+ * USB_DEVICE_PRODUCT_ID (Word)<br>
+ * Product ID (Referenced in usb_atmel.h).
+ *
+ * USB_DEVICE_MAJOR_VERSION (Byte)<br>
+ * Major version of the device
+ *
+ * USB_DEVICE_MINOR_VERSION (Byte)<br>
+ * Minor version of the device
+ *
+ * USB_DEVICE_MANUFACTURE_NAME (string)<br>
+ * ASCII name for the manufacture
+ *
+ * USB_DEVICE_PRODUCT_NAME (string)<br>
+ * ASCII name for the product
+ *
+ * USB_DEVICE_SERIAL_NAME (string)<br>
+ * ASCII name to enable and set a serial number
+ *
+ * USB_DEVICE_POWER (Numeric)<br>
+ * (unit mA) Maximum device power
+ *
+ * USB_DEVICE_ATTR (Byte)<br>
+ * USB attributes available:
+ * - USB_CONFIG_ATTR_SELF_POWERED
+ * - USB_CONFIG_ATTR_REMOTE_WAKEUP
+ * Note: if remote wake enabled then defines remotewakeup callbacks,
+ * see Table 5-2. External API from UDC - Callback
+ *
+ * USB_DEVICE_LOW_SPEED (Only defined)<br>
+ * Force the USB Device to run in low speed
+ *
+ * USB_DEVICE_HS_SUPPORT (Only defined)<br>
+ * Authorize the USB Device to run in high speed
+ *
+ * USB_DEVICE_MAX_EP (Byte)<br>
+ * Define the maximum endpoint number used by the USB Device.<br>
+ * This one is already defined in UDI default configuration.
+ * Ex:
+ * - When endpoint control 0x00, endpoint 0x01 and
+ * endpoint 0x82 is used then USB_DEVICE_MAX_EP=2
+ * - When only endpoint control 0x00 is used then USB_DEVICE_MAX_EP=0
+ * - When endpoint 0x01 and endpoint 0x81 is used then USB_DEVICE_MAX_EP=1<br>
+ * (configuration not possible on USBB interface)
+ * @{
+ */
+
+/**
+ * \brief Authorizes the VBUS event
+ *
+ * \return true, if the VBUS monitoring is possible.
+ *
+ * \section udc_vbus_monitoring VBus monitoring used cases
+ *
+ * The VBus monitoring is used only for USB SELF Power application.
+ *
+ * - By default the USB device is automatically attached when Vbus is high
+ * or when USB is start for devices without internal Vbus monitoring.
+ * conf_usb.h file does not contains define USB_DEVICE_ATTACH_AUTO_DISABLE.
+ * \code //#define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
+ *
+ * - Add custom VBUS monitoring. conf_usb.h file contains define
+ * USB_DEVICE_ATTACH_AUTO_DISABLE:
+ * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
+ * User C file contains:
+ * \code
+ // Authorize VBUS monitoring
+ if (!udc_include_vbus_monitoring()) {
+ // Implement custom VBUS monitoring via GPIO or other
+ }
+ Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other
+ {
+ // Attach USB Device
+ udc_attach();
+ }
+\endcode
+ *
+ * - Case of battery charging. conf_usb.h file contains define
+ * USB_DEVICE_ATTACH_AUTO_DISABLE:
+ * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
+ * User C file contains:
+ * \code
+ Event VBUS present() // VBUS interrupt or GPIO interrupt or ..
+ {
+ // Authorize battery charging, but wait key press to start USB.
+ }
+ Event Key press()
+ {
+ // Stop batteries charging
+ // Start USB
+ udc_attach();
+ }
+\endcode
+ */
+static inline bool udc_include_vbus_monitoring(void)
+{
+ return udd_include_vbus_monitoring();
+}
+
+/*! \brief Start the USB Device stack
+ */
+void udc_start(void);
+
+/*! \brief Stop the USB Device stack
+ */
+void udc_stop(void);
+
+/**
+ * \brief Attach device to the bus when possible
+ *
+ * \warning If a VBus control is included in driver,
+ * then it will attach device when an acceptable Vbus
+ * level from the host is detected.
+ */
+static inline void udc_attach(void)
+{
+ udd_attach();
+}
+
+
+/**
+ * \brief Detaches the device from the bus
+ *
+ * The driver must remove pull-up on USB line D- or D+.
+ */
+static inline void udc_detach(void)
+{
+ udd_detach();
+}
+
+
+/*! \brief The USB driver sends a resume signal called \e "Upstream Resume"
+ * This is authorized only when the remote wakeup feature is enabled by host.
+ */
+static inline void udc_remotewakeup(void)
+{
+ udd_send_remotewakeup();
+}
+
+
+/**
+ * \brief Returns a pointer on the current interface descriptor
+ *
+ * \return pointer on the current interface descriptor.
+ */
+usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void);
+
+//@}
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_device_group USB Stack Device
+ *
+ * This module includes USB Stack Device implementation.
+ * The stack is divided in three parts:
+ * - USB Device Controller (UDC) provides USB chapter 9 compliance
+ * - USB Device Interface (UDI) provides USB Class compliance
+ * - USB Device Driver (UDD) provides USB Driver for each Atmel MCU
+
+ * Many USB Device applications can be implemented on Atmel MCU.
+ * Atmel provides many application notes for different applications:
+ * - AVR4900, provides general information about Device Stack
+ * - AVR4901, explains how to create a new class
+ * - AVR4902, explains how to create a composite device
+ * - AVR49xx, all device classes provided in ASF have an application note
+ *
+ * A basic USB knowledge is required to understand the USB Device
+ * Class application notes (HID,MS,CDC,PHDC,...).
+ * Then, to create an USB device with
+ * only one class provided by ASF, refer directly to the application note
+ * corresponding to this USB class. The USB Device application note for
+ * New Class and Composite is dedicated to advanced USB users.
+ *
+ * @{
+ */
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_basic_use_case_setup_prereq USB Device Controller (UDC) - Prerequisites
+ * Common prerequisites for all USB devices.
+ *
+ * This module is based on USB device stack full interrupt driven, and supporting
+ * \ref sleepmgr_group sleepmgr. For AVR and SAM3/4 devices the \ref clk_group clock services
+ * is supported. For SAMD devices the \ref asfdoc_sam0_system_clock_group clock driver is supported.
+ *
+ * The following procedure must be executed to setup the project correctly:
+ * - Specify the clock configuration:
+ * - XMEGA USB devices need 48MHz clock input.\n
+ * XMEGA USB devices need CPU frequency higher than 12MHz.\n
+ * You can use either an internal RC48MHz auto calibrated by Start of Frames
+ * or an external OSC.
+ * - UC3 and SAM3/4 devices without USB high speed support need 48MHz clock input.\n
+ * You must use a PLL and an external OSC.
+ * - UC3 and SAM3/4 devices with USB high speed support need 12MHz clock input.\n
+ * You must use an external OSC.
+ * - UC3 devices with USBC hardware need CPU frequency higher than 25MHz.
+ * - SAMD devices without USB high speed support need 48MHz clock input.\n
+ * You should use DFLL with USBCRM.
+ * - In conf_board.h, the define CONF_BOARD_USB_PORT must be added to enable USB lines.
+ * (Not mandatory for all boards)
+ * - Enable interrupts
+ * - Initialize the clock service
+ *
+ * The usage of \ref sleepmgr_group sleepmgr service is optional, but recommended to reduce power
+ * consumption:
+ * - Initialize the sleep manager service
+ * - Activate sleep mode when the application is in IDLE state
+ *
+ * \subpage udc_conf_clock.
+ *
+ * for AVR and SAM3/4 devices, add to the initialization code:
+ * \code
+ sysclk_init();
+ irq_initialize_vectors();
+ cpu_irq_enable();
+ board_init();
+ sleepmgr_init(); // Optional
+\endcode
+ *
+ * For SAMD devices, add to the initialization code:
+ * \code
+ system_init();
+ irq_initialize_vectors();
+ cpu_irq_enable();
+ sleepmgr_init(); // Optional
+\endcode
+ * Add to the main IDLE loop:
+ * \code
+ sleepmgr_enter_sleep(); // Optional
+\endcode
+ *
+ */
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_basic_use_case_setup_code USB Device Controller (UDC) - Example code
+ * Common example code for all USB devices.
+ *
+ * Content of conf_usb.h:
+ * \code
+ #define USB_DEVICE_VENDOR_ID 0x03EB
+ #define USB_DEVICE_PRODUCT_ID 0xXXXX
+ #define USB_DEVICE_MAJOR_VERSION 1
+ #define USB_DEVICE_MINOR_VERSION 0
+ #define USB_DEVICE_POWER 100
+ #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+ void usb_init(void)
+ {
+ udc_start();
+ }
+\endcode
+ */
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_basic_use_case_setup_flow USB Device Controller (UDC) - Workflow
+ * Common workflow for all USB devices.
+ *
+ * -# Ensure that conf_usb.h is available and contains the following configuration
+ * which is the main USB device configuration:
+ * - \code // Vendor ID provided by USB org (ATMEL 0x03EB)
+ #define USB_DEVICE_VENDOR_ID 0x03EB // Type Word
+ // Product ID (Atmel PID referenced in usb_atmel.h)
+ #define USB_DEVICE_PRODUCT_ID 0xXXXX // Type Word
+ // Major version of the device
+ #define USB_DEVICE_MAJOR_VERSION 1 // Type Byte
+ // Minor version of the device
+ #define USB_DEVICE_MINOR_VERSION 0 // Type Byte
+ // Maximum device power (mA)
+ #define USB_DEVICE_POWER 100 // Type 9-bits
+ // USB attributes to enable features
+ #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED // Flags \endcode
+ * -# Call the USB device stack start function to enable stack and start USB:
+ * - \code udc_start(); \endcode
+ * \note In case of USB dual roles (Device and Host) managed through USB OTG connector
+ * (USB ID pin), the call of udc_start() must be removed and replaced by uhc_start().
+ * SeRefer to "AVR4950 section 6.1 Dual roles" for further information about dual roles.
+ */
+
+/**
+ * \page udc_conf_clock conf_clock.h examples with USB support
+ *
+ * Content of XMEGA conf_clock.h:
+ * \code
+ // Configuration based on internal RC:
+ // USB clock need of 48Mhz
+ #define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC
+ #define CONFIG_OSC_RC32_CAL 48000000UL
+ #define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_USBSOF
+ // CPU clock need of clock > 12MHz to run with USB (Here 24MHz)
+ #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC32MHZ
+ #define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2
+ #define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1
+\endcode
+ *
+ * Content of conf_clock.h for AT32UC3A0, AT32UC3A1, AT32UC3B devices (USBB):
+ * \code
+ // Configuration based on 12MHz external OSC:
+ #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
+ #define CONFIG_PLL1_MUL 8
+ #define CONFIG_PLL1_DIV 2
+ #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
+ #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div)
+\endcode
+ *
+ * Content of conf_clock.h for AT32UC3A3, AT32UC3A4 devices (USBB with high speed support):
+ * \code
+ // Configuration based on 12MHz external OSC:
+ #define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0
+ #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div)
+\endcode
+ *
+ * Content of conf_clock.h for AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U devices (USBC):
+ * \code
+ // Configuration based on 12MHz external OSC:
+ #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
+ #define CONFIG_PLL1_MUL 8
+ #define CONFIG_PLL1_DIV 2
+ #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
+ #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div)
+ // CPU clock need of clock > 25MHz to run with USBC
+ #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1
+\endcode
+ *
+ * Content of conf_clock.h for SAM3S, SAM3SD, SAM4S devices (UPD: USB Peripheral Device):
+ * \code
+ // PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
+ #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
+ #define CONFIG_PLL1_MUL 16
+ #define CONFIG_PLL1_DIV 2
+ // USB Clock Source Options (Fusb = FpllX / USB_div)
+ #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
+ #define CONFIG_USBCLK_DIV 2
+\endcode
+ *
+ * Content of conf_clock.h for SAM3U device (UPDHS: USB Peripheral Device High Speed):
+ * \code
+ // USB Clock Source fixed at UPLL.
+\endcode
+ *
+ * Content of conf_clock.h for SAM3X, SAM3A devices (UOTGHS: USB OTG High Speed):
+ * \code
+ // USB Clock Source fixed at UPLL.
+ #define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL
+ #define CONFIG_USBCLK_DIV 1
+\endcode
+ *
+ * Content of conf_clocks.h for SAMD devices (USB):
+ * \code
+ // System clock bus configuration
+ # define CONF_CLOCK_FLASH_WAIT_STATES 2
+
+ // USB Clock Source fixed at DFLL.
+ // SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop
+ # define CONF_CLOCK_DFLL_ENABLE true
+ # define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY
+ # define CONF_CLOCK_DFLL_ON_DEMAND true
+
+ // Set this to true to configure the GCLK when running clocks_init.
+ // If set to false, none of the GCLK generators will be configured in clocks_init().
+ # define CONF_CLOCK_CONFIGURE_GCLK true
+
+ // Configure GCLK generator 0 (Main Clock)
+ # define CONF_CLOCK_GCLK_0_ENABLE true
+ # define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true
+ # define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL
+ # define CONF_CLOCK_GCLK_0_PRESCALER 1
+ # define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
+\endcode
+ */
+
+/**
+ * \page udc_use_case_1 Change USB speed
+ *
+ * In this use case, the USB device is used with different USB speeds.
+ *
+ * \section udc_use_case_1_setup Setup steps
+ *
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_1_usage Usage steps
+ *
+ * \subsection udc_use_case_1_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #if // Low speed
+ #define USB_DEVICE_LOW_SPEED
+ // #define USB_DEVICE_HS_SUPPORT
+
+ #elif // Full speed
+ // #define USB_DEVICE_LOW_SPEED
+ // #define USB_DEVICE_HS_SUPPORT
+
+ #elif // High speed
+ // #define USB_DEVICE_LOW_SPEED
+ #define USB_DEVICE_HS_SUPPORT
+
+ #endif
+\endcode
+ *
+ * \subsection udc_use_case_1_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required for a USB device low speed (1.5Mbit/s):
+ * - \code #define USB_DEVICE_LOW_SPEED
+ //#define USB_DEVICE_HS_SUPPORT \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB device full speed (12Mbit/s):
+ * - \code //#define USB_DEVICE_LOW_SPEED
+ //#define USB_DEVICE_HS_SUPPORT \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB device high speed (480Mbit/s):
+ * - \code //#define USB_DEVICE_LOW_SPEED
+ #define USB_DEVICE_HS_SUPPORT \endcode
+ */
+
+/**
+ * \page udc_use_case_2 Use USB strings
+ *
+ * In this use case, the usual USB strings is added in the USB device.
+ *
+ * \section udc_use_case_2_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_2_usage Usage steps
+ *
+ * \subsection udc_use_case_2_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name"
+ #define USB_DEVICE_PRODUCT_NAME "Product name"
+ #define USB_DEVICE_SERIAL_NAME "12...EF"
+\endcode
+ *
+ * \subsection udc_use_case_2_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required to enable different USB strings:
+ * - \code // Static ASCII name for the manufacture
+ #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" \endcode
+ * - \code // Static ASCII name for the product
+ #define USB_DEVICE_PRODUCT_NAME "Product name" \endcode
+ * - \code // Static ASCII name to enable and set a serial number
+ #define USB_DEVICE_SERIAL_NAME "12...EF" \endcode
+ */
+
+/**
+ * \page udc_use_case_3 Use USB remote wakeup feature
+ *
+ * In this use case, the USB remote wakeup feature is enabled.
+ *
+ * \section udc_use_case_3_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_3_usage Usage steps
+ *
+ * \subsection udc_use_case_3_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #define USB_DEVICE_ATTR \
+ (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED)
+ #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable()
+ extern void my_callback_remotewakeup_enable(void);
+ #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable()
+ extern void my_callback_remotewakeup_disable(void);
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+ void my_callback_remotewakeup_enable(void)
+ {
+ // Enable application wakeup events (e.g. enable GPIO interrupt)
+ }
+ void my_callback_remotewakeup_disable(void)
+ {
+ // Disable application wakeup events (e.g. disable GPIO interrupt)
+ }
+
+ void my_interrupt_event(void)
+ {
+ udc_remotewakeup();
+ }
+\endcode
+ *
+ * \subsection udc_use_case_3_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required to enable remote wakeup feature:
+ * - \code // Authorizes the remote wakeup feature
+ #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) \endcode
+ * - \code // Define callback called when the host enables the remotewakeup feature
+ #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable()
+ extern void my_callback_remotewakeup_enable(void); \endcode
+ * - \code // Define callback called when the host disables the remotewakeup feature
+ #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable()
+ extern void my_callback_remotewakeup_disable(void); \endcode
+ * -# Send a remote wakeup (USB upstream):
+ * - \code udc_remotewakeup(); \endcode
+ */
+
+/**
+ * \page udc_use_case_5 Bus power application recommendations
+ *
+ * In this use case, the USB device BUS power feature is enabled.
+ * This feature requires a correct power consumption management.
+ *
+ * \section udc_use_case_5_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_5_usage Usage steps
+ *
+ * \subsection udc_use_case_5_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED)
+ #define UDC_SUSPEND_EVENT() user_callback_suspend_action()
+ extern void user_callback_suspend_action(void)
+ #define UDC_RESUME_EVENT() user_callback_resume_action()
+ extern void user_callback_resume_action(void)
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+ void user_callback_suspend_action(void)
+ {
+ // Disable hardware component to reduce power consumption
+ }
+ void user_callback_resume_action(void)
+ {
+ // Re-enable hardware component
+ }
+\endcode
+ *
+ * \subsection udc_use_case_5_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters:
+ * - \code // Authorizes the BUS power feature
+ #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) \endcode
+ * - \code // Define callback called when the host suspend the USB line
+ #define UDC_SUSPEND_EVENT() user_callback_suspend_action()
+ extern void user_callback_suspend_action(void); \endcode
+ * - \code // Define callback called when the host or device resume the USB line
+ #define UDC_RESUME_EVENT() user_callback_resume_action()
+ extern void user_callback_resume_action(void); \endcode
+ * -# Reduce power consumption in suspend mode (max. 2.5mA on Vbus):
+ * - \code void user_callback_suspend_action(void)
+ {
+ turn_off_components();
+ } \endcode
+ */
+
+/**
+ * \page udc_use_case_6 USB dynamic serial number
+ *
+ * In this use case, the USB serial strings is dynamic.
+ * For a static serial string refer to \ref udc_use_case_2.
+ *
+ * \section udc_use_case_6_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_6_usage Usage steps
+ *
+ * \subsection udc_use_case_6_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+ #define USB_DEVICE_SERIAL_NAME
+ #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number
+ #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12
+ extern uint8_t serial_number[];
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+ uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
+
+ void init_build_usb_serial_number(void)
+ {
+ serial_number[0] = 'A';
+ serial_number[1] = 'B';
+ ...
+ serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C';
+ } \endcode
+ *
+ * \subsection udc_use_case_6_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required to enable a USB serial number strings dynamically:
+ * - \code #define USB_DEVICE_SERIAL_NAME // Define this empty
+ #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number // Give serial array pointer
+ #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 // Give size of serial array
+ extern uint8_t serial_number[]; // Declare external serial array \endcode
+ * -# Before start USB stack, initialize the serial array
+ * - \code
+ uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
+
+ void init_build_usb_serial_number(void)
+ {
+ serial_number[0] = 'A';
+ serial_number[1] = 'B';
+ ...
+ serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C';
+ } \endcode
+ */
+
+
+
+#endif // _UDC_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc_desc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc_desc.h
new file mode 100755
index 0000000000000000000000000000000000000000..2ce527463c73bb92d6e83b36f9ef370ee768c03b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udc_desc.h
@@ -0,0 +1,132 @@
+/**
+ * \file
+ *
+ * \brief Common API for USB Device Interface
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UDC_DESC_H_
+#define _UDC_DESC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "udi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_desc_group USB Device Descriptor
+ *
+ * @{
+ */
+
+/**
+ * \brief Defines the memory's location of USB descriptors
+ *
+ * By default the Descriptor is stored in RAM
+ * (UDC_DESC_STORAGE is defined empty).
+ *
+ * If you have need to free RAM space,
+ * it is possible to put descriptor in flash in following case:
+ * - USB driver authorize flash transfer (USBB on UC3 and USB on Mega)
+ * - USB Device is not high speed (UDC no need to change USB descriptors)
+ *
+ * For UC3 application used "const".
+ *
+ * For Mega application used "code".
+ */
+#define UDC_DESC_STORAGE
+ // Descriptor storage in internal RAM
+#if (defined UDC_DATA_USE_HRAM_SUPPORT)
+# if defined(__GNUC__)
+# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
+# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0")))
+# elif defined(__ICCAVR32__)
+# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32
+# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32
+# endif
+#else
+# define UDC_DATA(x) COMPILER_ALIGNED(x)
+# define UDC_BSS(x) COMPILER_ALIGNED(x)
+#endif
+
+
+
+/**
+ * \brief Configuration descriptor and UDI link for one USB speed
+ */
+typedef struct {
+ //! USB configuration descriptor
+ usb_conf_desc_t UDC_DESC_STORAGE *desc;
+ //! Array of UDI API pointer
+ udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis;
+} udc_config_speed_t;
+
+
+/**
+ * \brief All information about the USB Device
+ */
+typedef struct {
+ //! USB device descriptor for low or full speed
+ usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs;
+ //! USB configuration descriptor and UDI API pointers for low or full speed
+ udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs;
+#ifdef USB_DEVICE_HS_SUPPORT
+ //! USB device descriptor for high speed
+ usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs;
+ //! USB device qualifier, only use in high speed mode
+ usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier;
+ //! USB configuration descriptor and UDI API pointers for high speed
+ udc_config_speed_t UDC_DESC_STORAGE *conf_hs;
+#endif
+ usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos;
+} udc_config_t;
+
+//! Global variables of USB Device Descriptor and UDI links
+extern UDC_DESC_STORAGE udc_config_t udc_config;
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDC_DESC_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udd.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udd.h
new file mode 100755
index 0000000000000000000000000000000000000000..85df46fd47f6db779264b11e2dc6208b6f78da19
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udd.h
@@ -0,0 +1,393 @@
+/**
+ * \file
+ *
+ * \brief Common API for USB Device Drivers (UDD)
+ *
+ * Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UDD_H_
+#define _UDD_H_
+
+#include "usb_protocol.h"
+#include "udc_desc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup udd_group USB Device Driver (UDD)
+ *
+ * The UDD driver provides a low-level abstraction of the device
+ * controller hardware. Most events coming from the hardware such as
+ * interrupts, which may cause the UDD to call into the UDC and UDI.
+ *
+ * @{
+ */
+
+//! \brief Endpoint identifier
+typedef uint8_t udd_ep_id_t;
+
+//! \brief Endpoint transfer status
+//! Returned in parameters of callback register via udd_ep_run routine.
+typedef enum {
+ UDD_EP_TRANSFER_OK = 0,
+ UDD_EP_TRANSFER_ABORT = 1,
+} udd_ep_status_t;
+
+/**
+ * \brief Global variable to give and record information of the setup request management
+ *
+ * This global variable allows to decode and response a setup request.
+ * It can be updated by udc_process_setup() from UDC or *setup() from UDIs.
+ */
+typedef struct {
+ //! Data received in USB SETUP packet
+ //! Note: The swap of "req.wValues" from uin16_t to le16_t is done by UDD.
+ usb_setup_req_t req;
+
+ //! Point to buffer to send or fill with data following SETUP packet
+ //! This buffer must be word align for DATA IN phase (use prefix COMPILER_WORD_ALIGNED for buffer)
+ uint8_t *payload;
+
+ //! Size of buffer to send or fill, and content the number of byte transfered
+ uint16_t payload_size;
+
+ //! Callback called after reception of ZLP from setup request
+ void (*callback) (void);
+
+ //! Callback called when the buffer given (.payload) is full or empty.
+ //! This one return false to abort data transfer, or true with a new buffer in .payload.
+ bool(*over_under_run) (void);
+} udd_ctrl_request_t;
+extern udd_ctrl_request_t udd_g_ctrlreq;
+
+//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer
+#define Udd_setup_is_in() \
+ (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
+
+//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer
+#define Udd_setup_is_out() \
+ (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
+
+//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype.
+#define Udd_setup_type() \
+ (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
+
+//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient
+#define Udd_setup_recipient() \
+ (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
+
+/**
+ * \brief End of halt callback function type.
+ * Registered by routine udd_ep_wait_stall_clear()
+ * Callback called when endpoint stall is cleared.
+ */
+typedef void (*udd_callback_halt_cleared_t) (void);
+
+/**
+ * \brief End of transfer callback function type.
+ * Registered by routine udd_ep_run()
+ * Callback called by USB interrupt after data transfer or abort (reset,...).
+ *
+ * \param status UDD_EP_TRANSFER_OK, if transfer is complete
+ * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted
+ * \param n number of data transfered
+ */
+typedef void (*udd_callback_trans_t) (udd_ep_status_t status,
+ iram_size_t nb_transfered, udd_ep_id_t ep);
+
+/**
+ * \brief Authorizes the VBUS event
+ *
+ * \return true, if the VBUS monitoring is possible.
+ */
+bool udd_include_vbus_monitoring(void);
+
+/**
+ * \brief Enables the USB Device mode
+ */
+void udd_enable(void);
+
+/**
+ * \brief Disables the USB Device mode
+ */
+void udd_disable(void);
+
+/**
+ * \brief Attach device to the bus when possible
+ *
+ * \warning If a VBus control is included in driver,
+ * then it will attach device when an acceptable Vbus
+ * level from the host is detected.
+ */
+void udd_attach(void);
+
+/**
+ * \brief Detaches the device from the bus
+ *
+ * The driver must remove pull-up on USB line D- or D+.
+ */
+void udd_detach(void);
+
+/**
+ * \brief Test whether the USB Device Controller is running at high
+ * speed or not.
+ *
+ * \return \c true if the Device is running at high speed mode, otherwise \c false.
+ */
+bool udd_is_high_speed(void);
+
+/**
+ * \brief Changes the USB address of device
+ *
+ * \param address New USB address
+ */
+void udd_set_address(uint8_t address);
+
+/**
+ * \brief Returns the USB address of device
+ *
+ * \return USB address
+ */
+uint8_t udd_getaddress(void);
+
+/**
+ * \brief Returns the current start of frame number
+ *
+ * \return current start of frame number.
+ */
+uint16_t udd_get_frame_number(void);
+
+/**
+ * \brief Returns the current micro start of frame number
+ *
+ * \return current micro start of frame number required in high speed mode.
+ */
+uint16_t udd_get_micro_frame_number(void);
+
+/*! \brief The USB driver sends a resume signal called Upstream Resume
+ */
+void udd_send_remotewakeup(void);
+
+/**
+ * \brief Load setup payload
+ *
+ * \param payload Pointer on payload
+ * \param payload_size Size of payload
+ */
+void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size );
+
+
+/**
+ * \name Endpoint Management
+ *
+ * The following functions allow drivers to create and remove
+ * endpoints, as well as set, clear and query their "halted" and
+ * "wedged" states.
+ */
+//@{
+
+#if (USB_DEVICE_MAX_EP != 0)
+
+/**
+ * \brief Configures and enables an endpoint
+ *
+ * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
+ * \param bmAttributes Attributes of endpoint declared in the descriptor.
+ * \param MaxEndpointSize Endpoint maximum size
+ *
+ * \return \c 1 if the endpoint is enabled, otherwise \c 0.
+ */
+bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes,
+ uint16_t MaxEndpointSize);
+
+/**
+ * \brief Disables an endpoint
+ *
+ * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
+ */
+void udd_ep_free(udd_ep_id_t ep);
+
+/**
+ * \brief Check if the endpoint \a ep is halted.
+ *
+ * \param ep The ID of the endpoint to check.
+ *
+ * \return \c 1 if \a ep is halted, otherwise \c 0.
+ */
+bool udd_ep_is_halted(udd_ep_id_t ep);
+
+/**
+ * \brief Set the halted state of the endpoint \a ep
+ *
+ * After calling this function, any transaction on \a ep will result
+ * in a STALL handshake being sent. Any pending transactions will be
+ * performed first, however.
+ *
+ * \param ep The ID of the endpoint to be halted
+ *
+ * \return \c 1 if \a ep is halted, otherwise \c 0.
+ */
+bool udd_ep_set_halt(udd_ep_id_t ep);
+
+/**
+ * \brief Clear the halted state of the endpoint \a ep
+ *
+ * After calling this function, any transaction on \a ep will
+ * be handled normally, i.e. a STALL handshake will not be sent, and
+ * the data toggle sequence will start at DATA0.
+ *
+ * \param ep The ID of the endpoint to be un-halted
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool udd_ep_clear_halt(udd_ep_id_t ep);
+
+/**
+ * \brief Registers a callback to call when endpoint halt is cleared
+ *
+ * \param ep The ID of the endpoint to use
+ * \param callback NULL or function to call when endpoint halt is cleared
+ *
+ * \warning if the endpoint is not halted then the \a callback is called immediately.
+ *
+ * \return \c 1 if the register is accepted, otherwise \c 0.
+ */
+bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
+ udd_callback_halt_cleared_t callback);
+
+/**
+ * \brief Allows to receive or send data on an endpoint
+ *
+ * The driver uses a specific DMA USB to transfer data
+ * from internal RAM to endpoint, if this one is available.
+ * When the transfer is finished or aborted (stall, reset, ...), the \a callback is called.
+ * The \a callback returns the transfer status and eventually the number of byte transfered.
+ * Note: The control endpoint is not authorized.
+ *
+ * \param ep The ID of the endpoint to use
+ * \param b_shortpacket Enabled automatic short packet
+ * \param buf Buffer on Internal RAM to send or fill.
+ * It must be align, then use COMPILER_WORD_ALIGNED.
+ * \param buf_size Buffer size to send or fill
+ * \param callback NULL or function to call at the end of transfer
+ *
+ * \warning About \a b_shortpacket, for IN endpoint it means that a short packet
+ * (or a Zero Length Packet) will be sent to the USB line to properly close the usb
+ * transfer at the end of the data transfer.
+ * For Bulk and Interrupt OUT endpoint, it will automatically stop the transfer
+ * at the end of the data transfer (received short packet).
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
+ uint8_t * buf, iram_size_t buf_size,
+ udd_callback_trans_t callback);
+/**
+ * \brief Aborts transfer on going on endpoint
+ *
+ * If a transfer is on going, then it is stopped and
+ * the callback registered is called to signal the end of transfer.
+ * Note: The control endpoint is not authorized.
+ *
+ * \param ep Endpoint to abort
+ */
+void udd_ep_abort(udd_ep_id_t ep);
+
+#endif
+
+//@}
+
+
+/**
+ * \name High speed test mode management
+ *
+ * The following functions allow the device to jump to a specific test mode required in high speed mode.
+ */
+//@{
+void udd_test_mode_j(void);
+void udd_test_mode_k(void);
+void udd_test_mode_se0_nak(void);
+void udd_test_mode_packet(void);
+//@}
+
+
+/**
+ * \name UDC callbacks to provide for UDD
+ *
+ * The following callbacks are used by UDD.
+ */
+//@{
+
+/**
+ * \brief Decodes and manages a setup request
+ *
+ * The driver call it when a SETUP packet is received.
+ * The \c udd_g_ctrlreq contains the data of SETUP packet.
+ * If this callback accepts the setup request then it must
+ * return \c 1 and eventually update \c udd_g_ctrlreq to send or receive data.
+ *
+ * \return \c 1 if the request is accepted, otherwise \c 0.
+ */
+extern bool udc_process_setup(void);
+
+/**
+ * \brief Reset the UDC
+ *
+ * The UDC must reset all configuration.
+ */
+extern void udc_reset(void);
+
+/**
+ * \brief To signal that a SOF is occurred
+ *
+ * The UDC must send the signal to all UDIs enabled
+ */
+extern void udc_sof_notify(void);
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDD_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udi.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udi.h
new file mode 100755
index 0000000000000000000000000000000000000000..48287f2792aed27aee1330d282862a88d2bb9a36
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/udc/udi.h
@@ -0,0 +1,130 @@
+/**
+ * \file
+ *
+ * \brief Common API for USB Device Interface
+ *
+ * Copyright (c) 2009 - 2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UDI_H_
+#define _UDI_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup udi_group USB Device Interface (UDI)
+ * The UDI provides a common API for all classes,
+ * and this is used by UDC for the main control of USB Device interface.
+ * @{
+ */
+
+/**
+ * \brief UDI API.
+ *
+ * The callbacks within this structure are called only by
+ * USB Device Controller (UDC)
+ *
+ * The udc_get_interface_desc() can be use by UDI to know the interface descriptor
+ * selected by UDC.
+ */
+typedef struct {
+ /**
+ * \brief Enable the interface.
+ *
+ * This function is called when the host selects a configuration
+ * to which this interface belongs through a Set Configuration
+ * request, and when the host selects an alternate setting of
+ * this interface through a Set Interface request.
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+ bool(*enable) (void);
+
+ /**
+ * \brief Disable the interface.
+ *
+ * This function is called when this interface is currently
+ * active, and
+ * - the host selects any configuration through a Set
+ * Configuration request, or
+ * - the host issues a USB reset, or
+ * - the device is detached from the host (i.e. Vbus is no
+ * longer present)
+ */
+ void (*disable) (void);
+
+ /**
+ * \brief Handle a control request directed at an interface.
+ *
+ * This function is called when this interface is currently
+ * active and the host sends a SETUP request
+ * with this interface as the recipient.
+ *
+ * Use udd_g_ctrlreq to decode and response to SETUP request.
+ *
+ * \return \c 1 if this interface supports the SETUP request, otherwise \c 0.
+ */
+ bool(*setup) (void);
+
+ /**
+ * \brief Returns the current setting of the selected interface.
+ *
+ * This function is called when UDC when know alternate setting of selected interface.
+ *
+ * \return alternate setting of selected interface
+ */
+ uint8_t(*getsetting) (void);
+
+ /**
+ * \brief To signal that a SOF is occurred
+ */
+ void(*sof_notify) (void);
+} udi_api_t;
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDI_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/usb_atmel.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/usb_atmel.h
new file mode 100755
index 0000000000000000000000000000000000000000..3178aadfd72aee7c0eb7b51165d3e3020aec0b67
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/usb_atmel.h
@@ -0,0 +1,187 @@
+/**
+ * \file
+ *
+ * \brief All USB VIDs and PIDs from Atmel USB applications
+ *
+ * Copyright (c) 2009-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _USB_ATMEL_H_
+#define _USB_ATMEL_H_
+
+/**
+ * \defgroup usb_group USB Stack
+ *
+ * This stack includes the USB Device Stack, USB Host Stack and common
+ * definitions.
+ * @{
+ */
+
+//! @}
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_atmel_ids_group Atmel USB Identifiers
+ *
+ * This module defines Atmel PID and VIDs constants.
+ *
+ * @{
+ */
+
+//! \name Vendor Identifier assigned by USB org to ATMEL
+#define USB_VID_ATMEL 0x03EB
+
+
+//! \name Product Identifier assigned by ATMEL to AVR applications
+//! @{
+
+//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others.
+//! @{
+#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013
+#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017
+#define USB_PID_ATMEL_MEGA_CDC 0x2018
+#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019
+#define USB_PID_ATMEL_MEGA_MS 0x201A
+#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B
+#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C
+#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D
+#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E
+#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022
+#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023
+#define USB_PID_ATMEL_MEGA_MS_2 0x2029
+#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A
+#define USB_PID_ATMEL_MEGA_MS_3 0x2032
+#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050
+//! @}
+
+//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools.
+//! @{
+#define USB_PID_ATMEL_XPLAINED 0x2122
+#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A
+#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B
+//! @}
+
+//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=>
+//! @{
+#define USB_PID_ATMEL_UC3_ENUM 0x2300
+#define USB_PID_ATMEL_UC3_MS 0x2301
+#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302
+#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303
+#define USB_PID_ATMEL_UC3_HID 0x2304
+#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305
+#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306
+#define USB_PID_ATMEL_UC3_CDC 0x2307
+#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308
+#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx
+#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311
+#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312
+//! @}
+
+//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications
+//! @{
+#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400
+#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401
+#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402
+#define USB_PID_ATMEL_ASF_MSC 0x2403
+#define USB_PID_ATMEL_ASF_CDC 0x2404
+#define USB_PID_ATMEL_ASF_PHDC 0x2405
+#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420
+#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421
+#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422
+#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423
+#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424
+#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425
+#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426
+#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430
+#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431
+#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432
+#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433
+#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434
+//! @}
+
+//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders
+//! Note, !!!! don't use this range for demos or examples !!!!
+//! @{
+#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6
+#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7
+#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8
+#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9
+#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA
+#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB
+#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC
+#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD
+#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE
+
+#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF
+#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0
+#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1
+#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2
+#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3
+#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4
+#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5
+#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6
+#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7
+#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8
+#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9
+#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA
+#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB
+#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC
+#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED
+#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE
+#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF
+#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0
+#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1
+#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2
+#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3
+#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4
+#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5
+#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6
+#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7
+#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8
+#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9
+#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA
+#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB
+// 2FFCh to 2FFFh used by C51 family products
+//! @}
+
+//! @}
+
+//! @}
+
+
+#endif // _USB_ATMEL_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/usb_protocol.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/usb_protocol.h
new file mode 100755
index 0000000000000000000000000000000000000000..c65c0f7cd1b495e8906b0949ce143af0fc74b632
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/services/usb/usb_protocol.h
@@ -0,0 +1,502 @@
+/**
+ * \file
+ *
+ * \brief USB protocol definitions.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _USB_PROTOCOL_H_
+#define _USB_PROTOCOL_H_
+
+#include "usb_atmel.h"
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_protocol_group USB Protocol Definitions
+ *
+ * This module defines constants and data structures provided by the USB
+ * 2.0 specification.
+ *
+ * @{
+ */
+
+//! Value for field bcdUSB
+#define USB_V2_0 0x0200 //!< USB Specification version 2.00
+#define USB_V2_1 0x0201 //!< USB Specification version 2.01
+
+/*! \name Generic definitions (Class, subclass and protocol)
+ */
+//! @{
+#define NO_CLASS 0x00
+#define CLASS_VENDOR_SPECIFIC 0xFF
+#define NO_SUBCLASS 0x00
+#define NO_PROTOCOL 0x00
+//! @}
+
+//! \name IAD (Interface Association Descriptor) constants
+//! @{
+#define CLASS_IAD 0xEF
+#define SUB_CLASS_IAD 0x02
+#define PROTOCOL_IAD 0x01
+//! @}
+
+/**
+ * \brief USB request data transfer direction (bmRequestType)
+ */
+#define USB_REQ_DIR_OUT (0<<7) //!< Host to device
+#define USB_REQ_DIR_IN (1<<7) //!< Device to host
+#define USB_REQ_DIR_MASK (1<<7) //!< Mask
+
+/**
+ * \brief USB request types (bmRequestType)
+ */
+#define USB_REQ_TYPE_STANDARD (0<<5) //!< Standard request
+#define USB_REQ_TYPE_CLASS (1<<5) //!< Class-specific request
+#define USB_REQ_TYPE_VENDOR (2<<5) //!< Vendor-specific request
+#define USB_REQ_TYPE_MASK (3<<5) //!< Mask
+
+/**
+ * \brief USB recipient codes (bmRequestType)
+ */
+#define USB_REQ_RECIP_DEVICE (0<<0) //!< Recipient device
+#define USB_REQ_RECIP_INTERFACE (1<<0) //!< Recipient interface
+#define USB_REQ_RECIP_ENDPOINT (2<<0) //!< Recipient endpoint
+#define USB_REQ_RECIP_OTHER (3<<0) //!< Recipient other
+#define USB_REQ_RECIP_MASK (0x1F) //!< Mask
+
+/**
+ * \brief Standard USB requests (bRequest)
+ */
+enum usb_reqid {
+ USB_REQ_GET_STATUS = 0,
+ USB_REQ_CLEAR_FEATURE = 1,
+ USB_REQ_SET_FEATURE = 3,
+ USB_REQ_SET_ADDRESS = 5,
+ USB_REQ_GET_DESCRIPTOR = 6,
+ USB_REQ_SET_DESCRIPTOR = 7,
+ USB_REQ_GET_CONFIGURATION = 8,
+ USB_REQ_SET_CONFIGURATION = 9,
+ USB_REQ_GET_INTERFACE = 10,
+ USB_REQ_SET_INTERFACE = 11,
+ USB_REQ_SYNCH_FRAME = 12,
+};
+
+/**
+ * \brief Standard USB device status flags
+ *
+ */
+enum usb_device_status {
+ USB_DEV_STATUS_BUS_POWERED = 0,
+ USB_DEV_STATUS_SELF_POWERED = 1,
+ USB_DEV_STATUS_REMOTEWAKEUP = 2
+};
+
+/**
+ * \brief Standard USB Interface status flags
+ *
+ */
+enum usb_interface_status {
+ USB_IFACE_STATUS_RESERVED = 0
+};
+
+/**
+ * \brief Standard USB endpoint status flags
+ *
+ */
+enum usb_endpoint_status {
+ USB_EP_STATUS_HALTED = 1,
+};
+
+/**
+ * \brief Standard USB device feature flags
+ *
+ * \note valid for SetFeature request.
+ */
+enum usb_device_feature {
+ USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled
+ USB_DEV_FEATURE_TEST_MODE = 2, //!< USB test mode
+ USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3,
+ USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4,
+ USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5
+};
+
+/**
+ * \brief Test Mode possible on HS USB device
+ *
+ * \note valid for USB_DEV_FEATURE_TEST_MODE request.
+ */
+enum usb_device_hs_test_mode {
+ USB_DEV_TEST_MODE_J = 1,
+ USB_DEV_TEST_MODE_K = 2,
+ USB_DEV_TEST_MODE_SE0_NAK = 3,
+ USB_DEV_TEST_MODE_PACKET = 4,
+ USB_DEV_TEST_MODE_FORCE_ENABLE = 5,
+};
+
+/**
+ * \brief Standard USB endpoint feature/status flags
+ */
+enum usb_endpoint_feature {
+ USB_EP_FEATURE_HALT = 0,
+};
+
+/**
+ * \brief Standard USB Test Mode Selectors
+ */
+enum usb_test_mode_selector {
+ USB_TEST_J = 0x01,
+ USB_TEST_K = 0x02,
+ USB_TEST_SE0_NAK = 0x03,
+ USB_TEST_PACKET = 0x04,
+ USB_TEST_FORCE_ENABLE = 0x05,
+};
+
+/**
+ * \brief Standard USB descriptor types
+ */
+enum usb_descriptor_type {
+ USB_DT_DEVICE = 1,
+ USB_DT_CONFIGURATION = 2,
+ USB_DT_STRING = 3,
+ USB_DT_INTERFACE = 4,
+ USB_DT_ENDPOINT = 5,
+ USB_DT_DEVICE_QUALIFIER = 6,
+ USB_DT_OTHER_SPEED_CONFIGURATION = 7,
+ USB_DT_INTERFACE_POWER = 8,
+ USB_DT_OTG = 9,
+ USB_DT_IAD = 0x0B,
+ USB_DT_BOS = 0x0F,
+ USB_DT_DEVICE_CAPABILITY = 0x10,
+};
+
+/**
+ * \brief USB Device Capability types
+ */
+enum usb_capability_type {
+ USB_DC_USB20_EXTENSION = 0x02,
+};
+
+/**
+ * \brief USB Device Capability - USB 2.0 Extension
+ * To fill bmAttributes field of usb_capa_ext_desc_t structure.
+ */
+enum usb_capability_extension_attr {
+ USB_DC_EXT_LPM = 0x00000002,
+ USB_DC_EXT_BESL = 0x00000004,
+ USB_DC_EXT_BESL_BASELINE_VALID = 0x00000008,
+ USB_DC_EXT_BESL_DEEP_VALID = 0x00000010,
+};
+#define USB_DC_EXT_BESL_DEEP_OFFSET 8
+#define USB_DC_EXT_BESL_DEEP(besl) ((besl & 0xF) << USB_DC_EXT_BESL_DEEP_OFFSET)
+#define USB_DC_EXT_BESL_BASELINE_OFFSET 12
+#define USB_DC_EXT_BESL_BASELINE(besl) ((besl & 0xF) << USB_DC_EXT_BESL_BASELINE_OFFSET)
+
+#define BESL_125_US 0
+#define BESL_150_US 1
+#define BESL_200_US 2
+#define BESL_300_US 3
+#define BESL_400_US 4
+#define BESL_500_US 5
+#define BESL_1000_US 6
+#define BESL_2000_US 7
+#define BESL_3000_US 8
+#define BESL_4000_US 9
+#define BESL_5000_US 10
+#define BESL_6000_US 11
+#define BESL_7000_US 12
+#define BESL_8000_US 13
+#define BESL_9000_US 14
+#define BESL_10000_US 15
+
+/** Fields definition from a LPM TOKEN */
+#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0)
+#define USB_LPM_ATTRIBUT_BESL_MASK (0xF << 4)
+#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8)
+#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0)
+#define USB_LPM_ATTRIBUT_BESL(value) ((value & 0xF) << 4)
+#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8)
+#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1)
+
+/**
+ * \brief Standard USB endpoint transfer types
+ */
+enum usb_ep_type {
+ USB_EP_TYPE_CONTROL = 0x00,
+ USB_EP_TYPE_ISOCHRONOUS = 0x01,
+ USB_EP_TYPE_BULK = 0x02,
+ USB_EP_TYPE_INTERRUPT = 0x03,
+ USB_EP_TYPE_MASK = 0x03,
+};
+
+/**
+ * \brief Standard USB language IDs for string descriptors
+ */
+enum usb_langid {
+ USB_LANGID_EN_US = 0x0409, //!< English (United States)
+};
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define USB_EP_ADDR_MASK 0x0f
+
+//! \brief USB address identifier
+typedef uint8_t usb_add_t;
+
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define USB_EP_DIR_IN 0x80
+
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define USB_EP_DIR_OUT 0x00
+
+//! \brief Endpoint identifier
+typedef uint8_t usb_ep_t;
+
+/**
+ * \brief Maximum length in bytes of a USB descriptor
+ *
+ * The maximum length of a USB descriptor is limited by the 8-bit
+ * bLength field.
+ */
+#define USB_MAX_DESC_LEN 255
+
+/*
+ * 2-byte alignment requested for all USB structures.
+ */
+COMPILER_PACK_SET(1)
+
+/**
+ * \brief A USB Device SETUP request
+ *
+ * The data payload of SETUP packets always follows this structure.
+ */
+typedef struct {
+ uint8_t bmRequestType;
+ uint8_t bRequest;
+ le16_t wValue;
+ le16_t wIndex;
+ le16_t wLength;
+} usb_setup_req_t;
+
+/**
+ * \brief Standard USB device descriptor structure
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ le16_t idVendor;
+ le16_t idProduct;
+ le16_t bcdDevice;
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} usb_dev_desc_t;
+
+/**
+ * \brief Standard USB device qualifier descriptor structure
+ *
+ * This descriptor contains information about the device when running at
+ * the "other" speed (i.e. if the device is currently operating at high
+ * speed, this descriptor can be used to determine what would change if
+ * the device was operating at full speed.)
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ uint8_t bNumConfigurations;
+ uint8_t bReserved;
+} usb_dev_qual_desc_t;
+
+/**
+ * \brief USB Device BOS descriptor structure
+ *
+ * The BOS descriptor (Binary device Object Store) defines a root
+ * descriptor that is similar to the configuration descriptor, and is
+ * the base descriptor for accessing a family of related descriptors.
+ * A host can read a BOS descriptor and learn from the wTotalLength field
+ * the entire size of the device-level descriptor set, or it can read in
+ * the entire BOS descriptor set of device capabilities.
+ * The host accesses this descriptor using the GetDescriptor() request.
+ * The descriptor type in the GetDescriptor() request is set to BOS.
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t wTotalLength;
+ uint8_t bNumDeviceCaps;
+} usb_dev_bos_desc_t;
+
+
+/**
+ * \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure
+ *
+ * Defines the set of USB 1.1-specific device level capabilities.
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bDevCapabilityType;
+ le32_t bmAttributes;
+} usb_dev_capa_ext_desc_t;
+
+/**
+ * \brief USB Device LPM Descriptor structure
+ *
+ * The BOS descriptor and capabilities descriptors for LPM.
+ */
+typedef struct {
+ usb_dev_bos_desc_t bos;
+ usb_dev_capa_ext_desc_t capa_ext;
+} usb_dev_lpm_desc_t;
+
+/**
+ * \brief Standard USB Interface Association Descriptor structure
+ */
+typedef struct {
+ uint8_t bLength; //!< size of this descriptor in bytes
+ uint8_t bDescriptorType; //!< INTERFACE descriptor type
+ uint8_t bFirstInterface; //!< Number of interface
+ uint8_t bInterfaceCount; //!< value to select alternate setting
+ uint8_t bFunctionClass; //!< Class code assigned by the USB
+ uint8_t bFunctionSubClass;//!< Sub-class code assigned by the USB
+ uint8_t bFunctionProtocol;//!< Protocol code assigned by the USB
+ uint8_t iFunction; //!< Index of string descriptor
+} usb_association_desc_t;
+
+
+/**
+ * \brief Standard USB configuration descriptor structure
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t iConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} usb_conf_desc_t;
+
+
+#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set
+#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered
+#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered
+#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) //!< remote wakeup supported
+
+#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) //!< Max power in mA
+
+/**
+ * \brief Standard USB association descriptor structure
+ */
+typedef struct {
+ uint8_t bLength; //!< Size of this descriptor in bytes
+ uint8_t bDescriptorType; //!< Interface descriptor type
+ uint8_t bFirstInterface; //!< Number of interface
+ uint8_t bInterfaceCount; //!< value to select alternate setting
+ uint8_t bFunctionClass; //!< Class code assigned by the USB
+ uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB
+ uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB
+ uint8_t iFunction; //!< Index of string descriptor
+} usb_iad_desc_t;
+
+/**
+ * \brief Standard USB interface descriptor structure
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} usb_iface_desc_t;
+
+/**
+ * \brief Standard USB endpoint descriptor structure
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ le16_t wMaxPacketSize;
+ uint8_t bInterval;
+} usb_ep_desc_t;
+
+
+/**
+ * \brief A standard USB string descriptor structure
+ */
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+} usb_str_desc_t;
+
+typedef struct {
+ usb_str_desc_t desc;
+ le16_t string[1];
+} usb_str_lgid_desc_t;
+
+COMPILER_PACK_RESET()
+
+//! @}
+
+#endif /* _USB_PROTOCOL_H_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt.h
new file mode 100755
index 0000000000000000000000000000000000000000..3613a26c5b899153204e665033ea7a69ddb88b0b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt.h
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA || TINY
+# include "interrupt/interrupt_avr8.h"
+#elif UC3
+# include "interrupt/interrupt_avr32.h"
+#elif SAM
+# include "interrupt/interrupt_sam_nvic.h"
+#else
+# error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+# define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
new file mode 100755
index 0000000000000000000000000000000000000000..ee93274e199d42a0275e8726c960d0e4af8e5186
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
@@ -0,0 +1,83 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+ if (cpu_irq_critical_section_counter == 0) {
+ if (cpu_irq_is_enabled()) {
+ cpu_irq_disable();
+ cpu_irq_prev_interrupt_state = true;
+ } else {
+ /* Make sure the to save the prev state as false */
+ cpu_irq_prev_interrupt_state = false;
+ }
+
+ }
+
+ cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+ /* Check if the user is trying to leave a critical section when not in a critical section */
+ Assert(cpu_irq_critical_section_counter > 0);
+
+ cpu_irq_critical_section_counter--;
+
+ /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+ was enabled when entering critical state */
+ if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+ cpu_irq_enable();
+ }
+}
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
new file mode 100755
index 0000000000000000000000000000000000000000..1b23b08577707d90656f0d70ac87b8728596a0f6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
@@ -0,0 +1,186 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ * add to vector table in binary generation, so there is no service
+ * register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+ ISR(foo_irq_handler)
+ {
+ // Function definition
+ ...
+ }
+\endcode
+ *
+ * \param func Name for the function.
+ */
+# define ISR(func) \
+ void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+# define irq_initialize_vectors() \
+ do { \
+ } while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+ irq_initialize_vectors();
+ irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ * files (exceptions.h).
+ */
+# define irq_register_handler(int_num, int_prio) \
+ NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
+ NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
+ NVIC_EnableIRQ( (IRQn_Type)int_num); \
+
+//@}
+
+# define cpu_irq_enable() \
+ do { \
+ g_interrupt_enabled = true; \
+ __DMB(); \
+ __enable_irq(); \
+ } while (0)
+# define cpu_irq_disable() \
+ do { \
+ __disable_irq(); \
+ __DMB(); \
+ g_interrupt_enabled = false; \
+ } while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+ irqflags_t flags = cpu_irq_is_enabled();
+ cpu_irq_disable();
+ return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+ return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+ if (cpu_irq_is_enabled_flags(flags))
+ cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt() cpu_irq_enable()
+#define Disable_global_interrupt() cpu_irq_disable()
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/parts.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/parts.h
new file mode 100755
index 0000000000000000000000000000000000000000..3304a74139f7d45bdf144b583e0c77d4b8c22204
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/common/utils/parts.h
@@ -0,0 +1,1242 @@
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+/**
+ * \defgroup part_macros_group Atmel part identification macros
+ *
+ * This collection of macros identify which series and families that the various
+ * Atmel parts belong to. These can be used to select part-dependent sections of
+ * code at compile time.
+ *
+ * @{
+ */
+
+/**
+ * \name Convenience macros for part checking
+ * @{
+ */
+/* ! Check GCC and IAR part definition for 8-bit AVR */
+#define AVR8_PART_IS_DEFINED(part) \
+ (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for 32-bit AVR */
+#define AVR32_PART_IS_DEFINED(part) \
+ (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
+
+/* ! Check GCC and IAR part definition for SAM */
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
+/** @} */
+
+/**
+ * \defgroup uc3_part_macros_group AVR UC3 parts
+ * @{
+ */
+
+/**
+ * \name AVR UC3 A series
+ * @{
+ */
+#define UC3A0 ( \
+ AVR32_PART_IS_DEFINED(UC3A0128) || \
+ AVR32_PART_IS_DEFINED(UC3A0256) || \
+ AVR32_PART_IS_DEFINED(UC3A0512) \
+ )
+
+#define UC3A1 ( \
+ AVR32_PART_IS_DEFINED(UC3A1128) || \
+ AVR32_PART_IS_DEFINED(UC3A1256) || \
+ AVR32_PART_IS_DEFINED(UC3A1512) \
+ )
+
+#define UC3A3 ( \
+ AVR32_PART_IS_DEFINED(UC3A364) || \
+ AVR32_PART_IS_DEFINED(UC3A364S) || \
+ AVR32_PART_IS_DEFINED(UC3A3128) || \
+ AVR32_PART_IS_DEFINED(UC3A3128S) || \
+ AVR32_PART_IS_DEFINED(UC3A3256) || \
+ AVR32_PART_IS_DEFINED(UC3A3256S) \
+ )
+
+#define UC3A4 ( \
+ AVR32_PART_IS_DEFINED(UC3A464) || \
+ AVR32_PART_IS_DEFINED(UC3A464S) || \
+ AVR32_PART_IS_DEFINED(UC3A4128) || \
+ AVR32_PART_IS_DEFINED(UC3A4128S) || \
+ AVR32_PART_IS_DEFINED(UC3A4256) || \
+ AVR32_PART_IS_DEFINED(UC3A4256S) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 B series
+ * @{
+ */
+#define UC3B0 ( \
+ AVR32_PART_IS_DEFINED(UC3B064) || \
+ AVR32_PART_IS_DEFINED(UC3B0128) || \
+ AVR32_PART_IS_DEFINED(UC3B0256) || \
+ AVR32_PART_IS_DEFINED(UC3B0512) \
+ )
+
+#define UC3B1 ( \
+ AVR32_PART_IS_DEFINED(UC3B164) || \
+ AVR32_PART_IS_DEFINED(UC3B1128) || \
+ AVR32_PART_IS_DEFINED(UC3B1256) || \
+ AVR32_PART_IS_DEFINED(UC3B1512) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 C series
+ * @{
+ */
+#define UC3C0 ( \
+ AVR32_PART_IS_DEFINED(UC3C064C) || \
+ AVR32_PART_IS_DEFINED(UC3C0128C) || \
+ AVR32_PART_IS_DEFINED(UC3C0256C) || \
+ AVR32_PART_IS_DEFINED(UC3C0512C) \
+ )
+
+#define UC3C1 ( \
+ AVR32_PART_IS_DEFINED(UC3C164C) || \
+ AVR32_PART_IS_DEFINED(UC3C1128C) || \
+ AVR32_PART_IS_DEFINED(UC3C1256C) || \
+ AVR32_PART_IS_DEFINED(UC3C1512C) \
+ )
+
+#define UC3C2 ( \
+ AVR32_PART_IS_DEFINED(UC3C264C) || \
+ AVR32_PART_IS_DEFINED(UC3C2128C) || \
+ AVR32_PART_IS_DEFINED(UC3C2256C) || \
+ AVR32_PART_IS_DEFINED(UC3C2512C) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 D series
+ * @{
+ */
+#define UC3D3 ( \
+ AVR32_PART_IS_DEFINED(UC64D3) || \
+ AVR32_PART_IS_DEFINED(UC128D3) \
+ )
+
+#define UC3D4 ( \
+ AVR32_PART_IS_DEFINED(UC64D4) || \
+ AVR32_PART_IS_DEFINED(UC128D4) \
+ )
+/** @} */
+
+/**
+ * \name AVR UC3 L series
+ * @{
+ */
+#define UC3L0 ( \
+ AVR32_PART_IS_DEFINED(UC3L016) || \
+ AVR32_PART_IS_DEFINED(UC3L032) || \
+ AVR32_PART_IS_DEFINED(UC3L064) \
+ )
+
+#define UC3L0128 ( \
+ AVR32_PART_IS_DEFINED(UC3L0128) \
+ )
+
+#define UC3L0256 ( \
+ AVR32_PART_IS_DEFINED(UC3L0256) \
+ )
+
+#define UC3L3 ( \
+ AVR32_PART_IS_DEFINED(UC64L3U) || \
+ AVR32_PART_IS_DEFINED(UC128L3U) || \
+ AVR32_PART_IS_DEFINED(UC256L3U) \
+ )
+
+#define UC3L4 ( \
+ AVR32_PART_IS_DEFINED(UC64L4U) || \
+ AVR32_PART_IS_DEFINED(UC128L4U) || \
+ AVR32_PART_IS_DEFINED(UC256L4U) \
+ )
+
+#define UC3L3_L4 (UC3L3 || UC3L4)
+/** @} */
+
+/**
+ * \name AVR UC3 families
+ * @{
+ */
+/** AVR UC3 A family */
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
+
+/** AVR UC3 B family */
+#define UC3B (UC3B0 || UC3B1)
+
+/** AVR UC3 C family */
+#define UC3C (UC3C0 || UC3C1 || UC3C2)
+
+/** AVR UC3 D family */
+#define UC3D (UC3D3 || UC3D4)
+
+/** AVR UC3 L family */
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
+/** @} */
+
+/** AVR UC3 product line */
+#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)
+
+/** @} */
+
+/**
+ * \defgroup xmega_part_macros_group AVR XMEGA parts
+ * @{
+ */
+
+/**
+ * \name AVR XMEGA A series
+ * @{
+ */
+#define XMEGA_A1 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A1) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A1) \
+ )
+
+#define XMEGA_A3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A3) || \
+ AVR8_PART_IS_DEFINED(ATxmega192A3) || \
+ AVR8_PART_IS_DEFINED(ATxmega256A3) \
+ )
+
+#define XMEGA_A3B ( \
+ AVR8_PART_IS_DEFINED(ATxmega256A3B) \
+ )
+
+#define XMEGA_A4 ( \
+ AVR8_PART_IS_DEFINED(ATxmega16A4) || \
+ AVR8_PART_IS_DEFINED(ATxmega32A4) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA AU series
+ * @{
+ */
+#define XMEGA_A1U ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A1U) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A1U) \
+ )
+
+#define XMEGA_A3U ( \
+ AVR8_PART_IS_DEFINED(ATxmega64A3U) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
+ AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
+ AVR8_PART_IS_DEFINED(ATxmega256A3U) \
+ )
+
+#define XMEGA_A3BU ( \
+ AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
+ )
+
+#define XMEGA_A4U ( \
+ AVR8_PART_IS_DEFINED(ATxmega16A4U) || \
+ AVR8_PART_IS_DEFINED(ATxmega32A4U) || \
+ AVR8_PART_IS_DEFINED(ATxmega64A4U) || \
+ AVR8_PART_IS_DEFINED(ATxmega128A4U) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA B series
+ * @{
+ */
+#define XMEGA_B1 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64B1) || \
+ AVR8_PART_IS_DEFINED(ATxmega128B1) \
+ )
+
+#define XMEGA_B3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega64B3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128B3) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA C series
+ * @{
+ */
+#define XMEGA_C3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega384C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega256C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega192C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega64C3) || \
+ AVR8_PART_IS_DEFINED(ATxmega32C3) \
+ )
+
+#define XMEGA_C4 ( \
+ AVR8_PART_IS_DEFINED(ATxmega32C4) || \
+ AVR8_PART_IS_DEFINED(ATxmega16C4) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA D series
+ * @{
+ */
+#define XMEGA_D3 ( \
+ AVR8_PART_IS_DEFINED(ATxmega32D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega64D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega128D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega192D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega256D3) || \
+ AVR8_PART_IS_DEFINED(ATxmega384D3) \
+ )
+
+#define XMEGA_D4 ( \
+ AVR8_PART_IS_DEFINED(ATxmega16D4) || \
+ AVR8_PART_IS_DEFINED(ATxmega32D4) || \
+ AVR8_PART_IS_DEFINED(ATxmega64D4) || \
+ AVR8_PART_IS_DEFINED(ATxmega128D4) \
+ )
+/** @} */
+
+/**
+ * \name AVR XMEGA E series
+ * @{
+ */
+#define XMEGA_E5 ( \
+ AVR8_PART_IS_DEFINED(ATxmega8E5) || \
+ AVR8_PART_IS_DEFINED(ATxmega16E5) || \
+ AVR8_PART_IS_DEFINED(ATxmega32E5) \
+ )
+/** @} */
+
+
+/**
+ * \name AVR XMEGA families
+ * @{
+ */
+/** AVR XMEGA A family */
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
+
+/** AVR XMEGA AU family */
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
+
+/** AVR XMEGA B family */
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
+
+/** AVR XMEGA C family */
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
+
+/** AVR XMEGA D family */
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
+
+/** AVR XMEGA E family */
+#define XMEGA_E (XMEGA_E5)
+/** @} */
+
+
+/** AVR XMEGA product line */
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
+
+/** @} */
+
+/**
+ * \defgroup mega_part_macros_group megaAVR parts
+ *
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the
+ * part header files. They are not names of official megaAVR device series or
+ * families.
+ *
+ * @{
+ */
+
+/**
+ * \name ATmegaxx0/xx1 subgroups
+ * @{
+ */
+#define MEGA_XX0 ( \
+ AVR8_PART_IS_DEFINED(ATmega640) || \
+ AVR8_PART_IS_DEFINED(ATmega1280) || \
+ AVR8_PART_IS_DEFINED(ATmega2560) \
+ )
+
+#define MEGA_XX1 ( \
+ AVR8_PART_IS_DEFINED(ATmega1281) || \
+ AVR8_PART_IS_DEFINED(ATmega2561) \
+ )
+/** @} */
+
+/**
+ * \name megaAVR groups
+ * @{
+ */
+/** ATmegaxx0/xx1 group */
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
+
+/** ATmegaxx4 group */
+#define MEGA_XX4 ( \
+ AVR8_PART_IS_DEFINED(ATmega164A) || \
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \
+ AVR8_PART_IS_DEFINED(ATmega324A) || \
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \
+ AVR8_PART_IS_DEFINED(ATmega644) || \
+ AVR8_PART_IS_DEFINED(ATmega644A) || \
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \
+ AVR8_PART_IS_DEFINED(ATmega1284P) || \
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+ )
+
+/** ATmegaxx4 group */
+#define MEGA_XX4_A ( \
+ AVR8_PART_IS_DEFINED(ATmega164A) || \
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \
+ AVR8_PART_IS_DEFINED(ATmega324A) || \
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \
+ AVR8_PART_IS_DEFINED(ATmega644A) || \
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \
+ AVR8_PART_IS_DEFINED(ATmega1284P) \
+ )
+
+/** ATmegaxx8 group */
+#define MEGA_XX8 ( \
+ AVR8_PART_IS_DEFINED(ATmega48) || \
+ AVR8_PART_IS_DEFINED(ATmega48A) || \
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \
+ AVR8_PART_IS_DEFINED(ATmega88) || \
+ AVR8_PART_IS_DEFINED(ATmega88A) || \
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \
+ AVR8_PART_IS_DEFINED(ATmega168) || \
+ AVR8_PART_IS_DEFINED(ATmega168A) || \
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \
+ AVR8_PART_IS_DEFINED(ATmega328) || \
+ AVR8_PART_IS_DEFINED(ATmega328P) \
+ )
+
+/** ATmegaxx8A/P/PA group */
+#define MEGA_XX8_A ( \
+ AVR8_PART_IS_DEFINED(ATmega48A) || \
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \
+ AVR8_PART_IS_DEFINED(ATmega88A) || \
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \
+ AVR8_PART_IS_DEFINED(ATmega168A) || \
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \
+ AVR8_PART_IS_DEFINED(ATmega328P) \
+ )
+
+/** ATmegaxx group */
+#define MEGA_XX ( \
+ AVR8_PART_IS_DEFINED(ATmega16) || \
+ AVR8_PART_IS_DEFINED(ATmega16A) || \
+ AVR8_PART_IS_DEFINED(ATmega32) || \
+ AVR8_PART_IS_DEFINED(ATmega32A) || \
+ AVR8_PART_IS_DEFINED(ATmega64) || \
+ AVR8_PART_IS_DEFINED(ATmega64A) || \
+ AVR8_PART_IS_DEFINED(ATmega128) || \
+ AVR8_PART_IS_DEFINED(ATmega128A) \
+ )
+
+/** ATmegaxxA/P/PA group */
+#define MEGA_XX_A ( \
+ AVR8_PART_IS_DEFINED(ATmega16A) || \
+ AVR8_PART_IS_DEFINED(ATmega32A) || \
+ AVR8_PART_IS_DEFINED(ATmega64A) || \
+ AVR8_PART_IS_DEFINED(ATmega128A) \
+ )
+/** ATmegaxxRFA1 group */
+#define MEGA_RFA1 ( \
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+ )
+
+/** ATmegaxxRFR2 group */
+#define MEGA_RFR2 ( \
+ AVR8_PART_IS_DEFINED(ATmega64RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega128RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega256RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega644RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
+ AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
+ )
+
+
+/** ATmegaxxRFxx group */
+#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
+
+/**
+ * \name ATmegaxx_un0/un1/un2 subgroups
+ * @{
+ */
+#define MEGA_XX_UN0 ( \
+ AVR8_PART_IS_DEFINED(ATmega16) || \
+ AVR8_PART_IS_DEFINED(ATmega16A) || \
+ AVR8_PART_IS_DEFINED(ATmega32) || \
+ AVR8_PART_IS_DEFINED(ATmega32A) \
+ )
+
+/** ATmegaxx group without power reduction and
+ * And interrupt sense register.
+ */
+#define MEGA_XX_UN1 ( \
+ AVR8_PART_IS_DEFINED(ATmega64) || \
+ AVR8_PART_IS_DEFINED(ATmega64A) || \
+ AVR8_PART_IS_DEFINED(ATmega128) || \
+ AVR8_PART_IS_DEFINED(ATmega128A) \
+ )
+
+/** ATmegaxx group without power reduction and
+ * And interrupt sense register.
+ */
+#define MEGA_XX_UN2 ( \
+ AVR8_PART_IS_DEFINED(ATmega169P) || \
+ AVR8_PART_IS_DEFINED(ATmega169PA) || \
+ AVR8_PART_IS_DEFINED(ATmega329P) || \
+ AVR8_PART_IS_DEFINED(ATmega329PA) \
+ )
+
+/** Devices added to complete megaAVR offering.
+ * Please do not use this group symbol as it is not intended
+ * to be permanent: the devices should be regrouped.
+ */
+#define MEGA_UNCATEGORIZED ( \
+ AVR8_PART_IS_DEFINED(AT90CAN128) || \
+ AVR8_PART_IS_DEFINED(AT90CAN32) || \
+ AVR8_PART_IS_DEFINED(AT90CAN64) || \
+ AVR8_PART_IS_DEFINED(AT90PWM1) || \
+ AVR8_PART_IS_DEFINED(AT90PWM216) || \
+ AVR8_PART_IS_DEFINED(AT90PWM2B) || \
+ AVR8_PART_IS_DEFINED(AT90PWM316) || \
+ AVR8_PART_IS_DEFINED(AT90PWM3B) || \
+ AVR8_PART_IS_DEFINED(AT90PWM81) || \
+ AVR8_PART_IS_DEFINED(AT90USB1286) || \
+ AVR8_PART_IS_DEFINED(AT90USB1287) || \
+ AVR8_PART_IS_DEFINED(AT90USB162) || \
+ AVR8_PART_IS_DEFINED(AT90USB646) || \
+ AVR8_PART_IS_DEFINED(AT90USB647) || \
+ AVR8_PART_IS_DEFINED(AT90USB82) || \
+ AVR8_PART_IS_DEFINED(ATmega1284) || \
+ AVR8_PART_IS_DEFINED(ATmega162) || \
+ AVR8_PART_IS_DEFINED(ATmega164P) || \
+ AVR8_PART_IS_DEFINED(ATmega165A) || \
+ AVR8_PART_IS_DEFINED(ATmega165P) || \
+ AVR8_PART_IS_DEFINED(ATmega165PA) || \
+ AVR8_PART_IS_DEFINED(ATmega168P) || \
+ AVR8_PART_IS_DEFINED(ATmega169A) || \
+ AVR8_PART_IS_DEFINED(ATmega16M1) || \
+ AVR8_PART_IS_DEFINED(ATmega16U2) || \
+ AVR8_PART_IS_DEFINED(ATmega16U4) || \
+ AVR8_PART_IS_DEFINED(ATmega256RFA2) || \
+ AVR8_PART_IS_DEFINED(ATmega324P) || \
+ AVR8_PART_IS_DEFINED(ATmega325) || \
+ AVR8_PART_IS_DEFINED(ATmega3250) || \
+ AVR8_PART_IS_DEFINED(ATmega3250A) || \
+ AVR8_PART_IS_DEFINED(ATmega3250P) || \
+ AVR8_PART_IS_DEFINED(ATmega3250PA) || \
+ AVR8_PART_IS_DEFINED(ATmega325A) || \
+ AVR8_PART_IS_DEFINED(ATmega325P) || \
+ AVR8_PART_IS_DEFINED(ATmega325PA) || \
+ AVR8_PART_IS_DEFINED(ATmega329) || \
+ AVR8_PART_IS_DEFINED(ATmega3290) || \
+ AVR8_PART_IS_DEFINED(ATmega3290A) || \
+ AVR8_PART_IS_DEFINED(ATmega3290P) || \
+ AVR8_PART_IS_DEFINED(ATmega3290PA) || \
+ AVR8_PART_IS_DEFINED(ATmega329A) || \
+ AVR8_PART_IS_DEFINED(ATmega32M1) || \
+ AVR8_PART_IS_DEFINED(ATmega32U2) || \
+ AVR8_PART_IS_DEFINED(ATmega32U4) || \
+ AVR8_PART_IS_DEFINED(ATmega48P) || \
+ AVR8_PART_IS_DEFINED(ATmega644P) || \
+ AVR8_PART_IS_DEFINED(ATmega645) || \
+ AVR8_PART_IS_DEFINED(ATmega6450) || \
+ AVR8_PART_IS_DEFINED(ATmega6450A) || \
+ AVR8_PART_IS_DEFINED(ATmega6450P) || \
+ AVR8_PART_IS_DEFINED(ATmega645A) || \
+ AVR8_PART_IS_DEFINED(ATmega645P) || \
+ AVR8_PART_IS_DEFINED(ATmega649) || \
+ AVR8_PART_IS_DEFINED(ATmega6490) || \
+ AVR8_PART_IS_DEFINED(ATmega6490A) || \
+ AVR8_PART_IS_DEFINED(ATmega6490P) || \
+ AVR8_PART_IS_DEFINED(ATmega649A) || \
+ AVR8_PART_IS_DEFINED(ATmega649P) || \
+ AVR8_PART_IS_DEFINED(ATmega64M1) || \
+ AVR8_PART_IS_DEFINED(ATmega64RFA2) || \
+ AVR8_PART_IS_DEFINED(ATmega8) || \
+ AVR8_PART_IS_DEFINED(ATmega8515) || \
+ AVR8_PART_IS_DEFINED(ATmega8535) || \
+ AVR8_PART_IS_DEFINED(ATmega88P) || \
+ AVR8_PART_IS_DEFINED(ATmega8A) || \
+ AVR8_PART_IS_DEFINED(ATmega8U2) \
+ )
+
+/** Unspecified group */
+#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
+ MEGA_UNCATEGORIZED)
+
+/** @} */
+
+/** megaAVR product line */
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
+ MEGA_UNSPECIFIED)
+
+/** @} */
+
+/**
+ * \defgroup tiny_part_macros_group tinyAVR parts
+ *
+ * @{
+ */
+
+/**
+ * \name tinyAVR groups
+ * @{
+ */
+
+/** Devices added to complete tinyAVR offering.
+ * Please do not use this group symbol as it is not intended
+ * to be permanent: the devices should be regrouped.
+ */
+#define TINY_UNCATEGORIZED ( \
+ AVR8_PART_IS_DEFINED(ATtiny10) || \
+ AVR8_PART_IS_DEFINED(ATtiny13) || \
+ AVR8_PART_IS_DEFINED(ATtiny13A) || \
+ AVR8_PART_IS_DEFINED(ATtiny1634) || \
+ AVR8_PART_IS_DEFINED(ATtiny167) || \
+ AVR8_PART_IS_DEFINED(ATtiny20) || \
+ AVR8_PART_IS_DEFINED(ATtiny2313) || \
+ AVR8_PART_IS_DEFINED(ATtiny2313A) || \
+ AVR8_PART_IS_DEFINED(ATtiny24) || \
+ AVR8_PART_IS_DEFINED(ATtiny24A) || \
+ AVR8_PART_IS_DEFINED(ATtiny25) || \
+ AVR8_PART_IS_DEFINED(ATtiny26) || \
+ AVR8_PART_IS_DEFINED(ATtiny261) || \
+ AVR8_PART_IS_DEFINED(ATtiny261A) || \
+ AVR8_PART_IS_DEFINED(ATtiny4) || \
+ AVR8_PART_IS_DEFINED(ATtiny40) || \
+ AVR8_PART_IS_DEFINED(ATtiny4313) || \
+ AVR8_PART_IS_DEFINED(ATtiny43U) || \
+ AVR8_PART_IS_DEFINED(ATtiny44) || \
+ AVR8_PART_IS_DEFINED(ATtiny44A) || \
+ AVR8_PART_IS_DEFINED(ATtiny45) || \
+ AVR8_PART_IS_DEFINED(ATtiny461) || \
+ AVR8_PART_IS_DEFINED(ATtiny461A) || \
+ AVR8_PART_IS_DEFINED(ATtiny48) || \
+ AVR8_PART_IS_DEFINED(ATtiny5) || \
+ AVR8_PART_IS_DEFINED(ATtiny828) || \
+ AVR8_PART_IS_DEFINED(ATtiny84) || \
+ AVR8_PART_IS_DEFINED(ATtiny84A) || \
+ AVR8_PART_IS_DEFINED(ATtiny85) || \
+ AVR8_PART_IS_DEFINED(ATtiny861) || \
+ AVR8_PART_IS_DEFINED(ATtiny861A) || \
+ AVR8_PART_IS_DEFINED(ATtiny87) || \
+ AVR8_PART_IS_DEFINED(ATtiny88) || \
+ AVR8_PART_IS_DEFINED(ATtiny9) \
+ )
+
+/** @} */
+
+/** tinyAVR product line */
+#define TINY (TINY_UNCATEGORIZED)
+
+/** @} */
+
+/**
+ * \defgroup sam_part_macros_group SAM parts
+ * @{
+ */
+
+/**
+ * \name SAM3S series
+ * @{
+ */
+#define SAM3S1 ( \
+ SAM_PART_IS_DEFINED(SAM3S1A) || \
+ SAM_PART_IS_DEFINED(SAM3S1B) || \
+ SAM_PART_IS_DEFINED(SAM3S1C) \
+ )
+
+#define SAM3S2 ( \
+ SAM_PART_IS_DEFINED(SAM3S2A) || \
+ SAM_PART_IS_DEFINED(SAM3S2B) || \
+ SAM_PART_IS_DEFINED(SAM3S2C) \
+ )
+
+#define SAM3S4 ( \
+ SAM_PART_IS_DEFINED(SAM3S4A) || \
+ SAM_PART_IS_DEFINED(SAM3S4B) || \
+ SAM_PART_IS_DEFINED(SAM3S4C) \
+ )
+
+#define SAM3S8 ( \
+ SAM_PART_IS_DEFINED(SAM3S8B) || \
+ SAM_PART_IS_DEFINED(SAM3S8C) \
+ )
+
+#define SAM3SD8 ( \
+ SAM_PART_IS_DEFINED(SAM3SD8B) || \
+ SAM_PART_IS_DEFINED(SAM3SD8C) \
+ )
+/** @} */
+
+/**
+ * \name SAM3U series
+ * @{
+ */
+#define SAM3U1 ( \
+ SAM_PART_IS_DEFINED(SAM3U1C) || \
+ SAM_PART_IS_DEFINED(SAM3U1E) \
+ )
+
+#define SAM3U2 ( \
+ SAM_PART_IS_DEFINED(SAM3U2C) || \
+ SAM_PART_IS_DEFINED(SAM3U2E) \
+ )
+
+#define SAM3U4 ( \
+ SAM_PART_IS_DEFINED(SAM3U4C) || \
+ SAM_PART_IS_DEFINED(SAM3U4E) \
+ )
+/** @} */
+
+/**
+ * \name SAM3N series
+ * @{
+ */
+#define SAM3N00 ( \
+ SAM_PART_IS_DEFINED(SAM3N00A) || \
+ SAM_PART_IS_DEFINED(SAM3N00B) \
+ )
+
+#define SAM3N0 ( \
+ SAM_PART_IS_DEFINED(SAM3N0A) || \
+ SAM_PART_IS_DEFINED(SAM3N0B) || \
+ SAM_PART_IS_DEFINED(SAM3N0C) \
+ )
+
+#define SAM3N1 ( \
+ SAM_PART_IS_DEFINED(SAM3N1A) || \
+ SAM_PART_IS_DEFINED(SAM3N1B) || \
+ SAM_PART_IS_DEFINED(SAM3N1C) \
+ )
+
+#define SAM3N2 ( \
+ SAM_PART_IS_DEFINED(SAM3N2A) || \
+ SAM_PART_IS_DEFINED(SAM3N2B) || \
+ SAM_PART_IS_DEFINED(SAM3N2C) \
+ )
+
+#define SAM3N4 ( \
+ SAM_PART_IS_DEFINED(SAM3N4A) || \
+ SAM_PART_IS_DEFINED(SAM3N4B) || \
+ SAM_PART_IS_DEFINED(SAM3N4C) \
+ )
+/** @} */
+
+/**
+ * \name SAM3X series
+ * @{
+ */
+#define SAM3X4 ( \
+ SAM_PART_IS_DEFINED(SAM3X4C) || \
+ SAM_PART_IS_DEFINED(SAM3X4E) \
+ )
+
+#define SAM3X8 ( \
+ SAM_PART_IS_DEFINED(SAM3X8C) || \
+ SAM_PART_IS_DEFINED(SAM3X8E) || \
+ SAM_PART_IS_DEFINED(SAM3X8H) \
+ )
+/** @} */
+
+/**
+ * \name SAM3A series
+ * @{
+ */
+#define SAM3A4 ( \
+ SAM_PART_IS_DEFINED(SAM3A4C) \
+ )
+
+#define SAM3A8 ( \
+ SAM_PART_IS_DEFINED(SAM3A8C) \
+ )
+/** @} */
+
+/**
+ * \name SAM4S series
+ * @{
+ */
+#define SAM4S2 ( \
+ SAM_PART_IS_DEFINED(SAM4S2A) || \
+ SAM_PART_IS_DEFINED(SAM4S2B) || \
+ SAM_PART_IS_DEFINED(SAM4S2C) \
+ )
+
+#define SAM4S4 ( \
+ SAM_PART_IS_DEFINED(SAM4S4A) || \
+ SAM_PART_IS_DEFINED(SAM4S4B) || \
+ SAM_PART_IS_DEFINED(SAM4S4C) \
+ )
+
+#define SAM4S8 ( \
+ SAM_PART_IS_DEFINED(SAM4S8B) || \
+ SAM_PART_IS_DEFINED(SAM4S8C) \
+ )
+
+#define SAM4S16 ( \
+ SAM_PART_IS_DEFINED(SAM4S16B) || \
+ SAM_PART_IS_DEFINED(SAM4S16C) \
+ )
+
+#define SAM4SA16 ( \
+ SAM_PART_IS_DEFINED(SAM4SA16B) || \
+ SAM_PART_IS_DEFINED(SAM4SA16C) \
+ )
+
+#define SAM4SD16 ( \
+ SAM_PART_IS_DEFINED(SAM4SD16B) || \
+ SAM_PART_IS_DEFINED(SAM4SD16C) \
+ )
+
+#define SAM4SD32 ( \
+ SAM_PART_IS_DEFINED(SAM4SD32B) || \
+ SAM_PART_IS_DEFINED(SAM4SD32C) \
+ )
+/** @} */
+
+/**
+ * \name SAM4L series
+ * @{
+ */
+#define SAM4LS ( \
+ SAM_PART_IS_DEFINED(SAM4LS2A) || \
+ SAM_PART_IS_DEFINED(SAM4LS2B) || \
+ SAM_PART_IS_DEFINED(SAM4LS2C) || \
+ SAM_PART_IS_DEFINED(SAM4LS4A) || \
+ SAM_PART_IS_DEFINED(SAM4LS4B) || \
+ SAM_PART_IS_DEFINED(SAM4LS4C) || \
+ SAM_PART_IS_DEFINED(SAM4LS8A) || \
+ SAM_PART_IS_DEFINED(SAM4LS8B) || \
+ SAM_PART_IS_DEFINED(SAM4LS8C) \
+ )
+
+#define SAM4LC ( \
+ SAM_PART_IS_DEFINED(SAM4LC2A) || \
+ SAM_PART_IS_DEFINED(SAM4LC2B) || \
+ SAM_PART_IS_DEFINED(SAM4LC2C) || \
+ SAM_PART_IS_DEFINED(SAM4LC4A) || \
+ SAM_PART_IS_DEFINED(SAM4LC4B) || \
+ SAM_PART_IS_DEFINED(SAM4LC4C) || \
+ SAM_PART_IS_DEFINED(SAM4LC8A) || \
+ SAM_PART_IS_DEFINED(SAM4LC8B) || \
+ SAM_PART_IS_DEFINED(SAM4LC8C) \
+ )
+/** @} */
+
+/**
+ * \name SAMD20 series
+ * @{
+ */
+#define SAMD20J ( \
+ SAM_PART_IS_DEFINED(SAMD20J14) || \
+ SAM_PART_IS_DEFINED(SAMD20J15) || \
+ SAM_PART_IS_DEFINED(SAMD20J16) || \
+ SAM_PART_IS_DEFINED(SAMD20J17) || \
+ SAM_PART_IS_DEFINED(SAMD20J18) \
+ )
+
+#define SAMD20G ( \
+ SAM_PART_IS_DEFINED(SAMD20G14) || \
+ SAM_PART_IS_DEFINED(SAMD20G15) || \
+ SAM_PART_IS_DEFINED(SAMD20G16) || \
+ SAM_PART_IS_DEFINED(SAMD20G17) || \
+ SAM_PART_IS_DEFINED(SAMD20G17U) || \
+ SAM_PART_IS_DEFINED(SAMD20G18) || \
+ SAM_PART_IS_DEFINED(SAMD20G18U) \
+ )
+
+#define SAMD20E ( \
+ SAM_PART_IS_DEFINED(SAMD20E14) || \
+ SAM_PART_IS_DEFINED(SAMD20E15) || \
+ SAM_PART_IS_DEFINED(SAMD20E16) || \
+ SAM_PART_IS_DEFINED(SAMD20E17) || \
+ SAM_PART_IS_DEFINED(SAMD20E18) || \
+ SAM_PART_IS_DEFINED(SAMD20E1F) \
+ )
+/** @} */
+
+/**
+ * \name SAMD21 series
+ * @{
+ */
+#define SAMD21J ( \
+ SAM_PART_IS_DEFINED(SAMD21J15A) || \
+ SAM_PART_IS_DEFINED(SAMD21J16A) || \
+ SAM_PART_IS_DEFINED(SAMD21J17A) || \
+ SAM_PART_IS_DEFINED(SAMD21J18A) \
+ )
+
+#define SAMD21G ( \
+ SAM_PART_IS_DEFINED(SAMD21G15A) || \
+ SAM_PART_IS_DEFINED(SAMD21G16A) || \
+ SAM_PART_IS_DEFINED(SAMD21G17A) || \
+ SAM_PART_IS_DEFINED(SAMD21G18A) \
+ )
+
+#define SAMD21E ( \
+ SAM_PART_IS_DEFINED(SAMD21E15A) || \
+ SAM_PART_IS_DEFINED(SAMD21E16A) || \
+ SAM_PART_IS_DEFINED(SAMD21E17A) || \
+ SAM_PART_IS_DEFINED(SAMD21E18A) \
+ )
+/** @} */
+
+/**
+ * \name SAMR21 series
+ * @{
+ */
+#define SAMR21G ( \
+ SAM_PART_IS_DEFINED(SAMR21G16A) || \
+ SAM_PART_IS_DEFINED(SAMR21G17A) || \
+ SAM_PART_IS_DEFINED(SAMR21G18A) \
+ )
+
+#define SAMR21E ( \
+ SAM_PART_IS_DEFINED(SAMR21E16A) || \
+ SAM_PART_IS_DEFINED(SAMR21E17A) || \
+ SAM_PART_IS_DEFINED(SAMR21E18A) \
+ )
+/** @} */
+
+/**
+ * \name SAMD10 series
+ * @{
+ */
+#define SAMD10C ( \
+ SAM_PART_IS_DEFINED(SAMD10C12A) || \
+ SAM_PART_IS_DEFINED(SAMD10C13A) || \
+ SAM_PART_IS_DEFINED(SAMD10C14A) \
+ )
+
+#define SAMD10DS ( \
+ SAM_PART_IS_DEFINED(SAMD10D12AS) || \
+ SAM_PART_IS_DEFINED(SAMD10D13AS) || \
+ SAM_PART_IS_DEFINED(SAMD10D14AS) \
+ )
+
+#define SAMD10DM ( \
+ SAM_PART_IS_DEFINED(SAMD10D12AM) || \
+ SAM_PART_IS_DEFINED(SAMD10D13AM) || \
+ SAM_PART_IS_DEFINED(SAMD10D14AM) \
+ )
+/** @} */
+
+/**
+ * \name SAMD11 series
+ * @{
+ */
+#define SAMD11C ( \
+ SAM_PART_IS_DEFINED(SAMD11C14A) \
+ )
+
+#define SAMD11DS ( \
+ SAM_PART_IS_DEFINED(SAMD11D14AS) \
+ )
+
+#define SAMD11DM ( \
+ SAM_PART_IS_DEFINED(SAMD11D14AM) \
+ )
+/** @} */
+
+/**
+ * \name SAM4E series
+ * @{
+ */
+#define SAM4E8 ( \
+ SAM_PART_IS_DEFINED(SAM4E8C) || \
+ SAM_PART_IS_DEFINED(SAM4E8E) \
+ )
+
+#define SAM4E16 ( \
+ SAM_PART_IS_DEFINED(SAM4E16C) || \
+ SAM_PART_IS_DEFINED(SAM4E16E) \
+ )
+/** @} */
+
+/**
+ * \name SAM4N series
+ * @{
+ */
+#define SAM4N8 ( \
+ SAM_PART_IS_DEFINED(SAM4N8A) || \
+ SAM_PART_IS_DEFINED(SAM4N8B) || \
+ SAM_PART_IS_DEFINED(SAM4N8C) \
+ )
+
+#define SAM4N16 ( \
+ SAM_PART_IS_DEFINED(SAM4N16B) || \
+ SAM_PART_IS_DEFINED(SAM4N16C) \
+ )
+/** @} */
+
+/**
+ * \name SAM4C series
+ * @{
+ */
+#define SAM4C8_0 ( \
+ SAM_PART_IS_DEFINED(SAM4C8C_0) \
+ )
+
+#define SAM4C8_1 ( \
+ SAM_PART_IS_DEFINED(SAM4C8C_1) \
+ )
+
+#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
+
+#define SAM4C16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4C16C_0) \
+ )
+
+#define SAM4C16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4C16C_1) \
+ )
+
+#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
+
+#define SAM4C32_0 ( \
+ SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
+ SAM_PART_IS_DEFINED(SAM4C32E_0) \
+ )
+
+#define SAM4C32_1 ( \
+ SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
+ SAM_PART_IS_DEFINED(SAM4C32E_1) \
+ )
+
+
+#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CM series
+ * @{
+ */
+#define SAM4CMP8_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
+ )
+
+#define SAM4CMP8_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
+ )
+
+#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
+
+#define SAM4CMP16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
+ )
+
+#define SAM4CMP16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
+ )
+
+#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
+
+#define SAM4CMP32_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
+ )
+
+#define SAM4CMP32_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
+ )
+
+#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
+
+#define SAM4CMS8_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
+ )
+
+#define SAM4CMS8_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
+ )
+
+#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
+
+#define SAM4CMS16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
+ )
+
+#define SAM4CMS16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
+ )
+
+#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
+
+#define SAM4CMS32_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
+ )
+
+#define SAM4CMS32_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
+ )
+
+#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
+
+/** @} */
+
+/**
+ * \name SAM4CP series
+ * @{
+ */
+#define SAM4CP16_0 ( \
+ SAM_PART_IS_DEFINED(SAM4CP16B_0) \
+ )
+
+#define SAM4CP16_1 ( \
+ SAM_PART_IS_DEFINED(SAM4CP16B_1) \
+ )
+
+#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
+/** @} */
+
+/**
+ * \name SAMG series
+ * @{
+ */
+#define SAMG51 ( \
+ SAM_PART_IS_DEFINED(SAMG51G18) \
+ )
+
+#define SAMG53 ( \
+ SAM_PART_IS_DEFINED(SAMG53G19) ||\
+ SAM_PART_IS_DEFINED(SAMG53N19) \
+ )
+
+#define SAMG54 ( \
+ SAM_PART_IS_DEFINED(SAMG54G19) ||\
+ SAM_PART_IS_DEFINED(SAMG54J19) ||\
+ SAM_PART_IS_DEFINED(SAMG54N19) \
+)
+/** @} */
+/**
+ * \name SAM families
+ * @{
+ */
+/** SAM3S Family */
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
+
+/** SAM3U Family */
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
+
+/** SAM3N Family */
+#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
+
+/** SAM3XA Family */
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
+
+/** SAM4S Family */
+#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
+
+/** SAM4L Family */
+#define SAM4L (SAM4LS || SAM4LC)
+
+/** SAMD20 Family */
+#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
+
+/** SAMD21 Family */
+#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
+
+/** SAMD10 Family */
+#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM)
+
+/** SAMD11 Family */
+#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM)
+
+/** SAMD Family */
+#define SAMD (SAMD20 || SAMD21 || SAMD10 || SAMD11)
+
+/** SAMR21 Family */
+#define SAMR21 (SAMR21G || SAMR21E)
+
+/** SAM4E Family */
+#define SAM4E (SAM4E8 || SAM4E16)
+
+/** SAM4N Family */
+#define SAM4N (SAM4N8 || SAM4N16)
+
+/** SAM4C Family */
+#define SAM4C_0 (SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
+#define SAM4C_1 (SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
+#define SAM4C (SAM4C8 || SAM4C16 || SAM4C32)
+
+/** SAM4CM Family */
+#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || SAM4CMS8_0 || \
+ SAM4CMS16_0 || SAM4CMS32_0)
+#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || SAM4CMS8_1 || \
+ SAM4CMS16_1 || SAM4CMS32_1)
+#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || SAM4CMS8 || \
+ SAM4CMS16 || SAM4CMS32)
+
+/** SAM4CP Family */
+#define SAM4CP_0 (SAM4CP16_0)
+#define SAM4CP_1 (SAM4CP16_1)
+#define SAM4CP (SAM4CP16)
+
+/** SAMG Family */
+#define SAMG (SAMG51 || SAMG53 || SAMG54)
+
+/** SAM0 product line (cortex-m0+) */
+#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11)
+
+/** @} */
+
+/** SAM product line */
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
+ SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG)
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* ATMEL_PARTS_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
new file mode 100755
index 0000000000000000000000000000000000000000..44c8c1f8a9781b0367c762bd1dec7ef159affbc1
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board initialization
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <port.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+# pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+ struct port_config pin_conf;
+ port_get_config_defaults(&pin_conf);
+
+ /* Configure LEDs as outputs, turn them off */
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ port_pin_set_config(LED_0_PIN, &pin_conf);
+ port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ port_pin_set_config(LED_L_PIN, &pin_conf);
+ port_pin_set_output_level(LED_L_PIN, LED_0_INACTIVE);
+
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ port_pin_set_config(LED_RX_PIN, &pin_conf);
+ port_pin_set_output_level(LED_RX_PIN, LED_RX_INACTIVE);
+
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ port_pin_set_config(LED_TX_PIN, &pin_conf);
+ port_pin_set_output_level(LED_RX_PIN, LED_RX_INACTIVE);
+
+ /* Set buttons as inputs */
+ pin_conf.direction = PORT_PIN_DIR_INPUT;
+ pin_conf.input_pull = PORT_PIN_PULL_UP;
+ port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+
+#ifdef CONF_BOARD_AT86RFX
+ port_get_config_defaults(&pin_conf);
+ pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+ port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+ port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+ port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+ port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+ port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+ port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+ port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+ port_pin_set_output_level(AT86RFX_SPI_CS, true);
+ port_pin_set_output_level(AT86RFX_RST_PIN, true);
+ port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+ pin_conf.direction = PORT_PIN_DIR_INPUT;
+ port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+#endif
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
new file mode 100755
index 0000000000000000000000000000000000000000..7fcb2203bcd7a6899604bf8cb169cca12ee1e895
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
@@ -0,0 +1,756 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board definition
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
+#define SAMD21_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samd21_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME "SAMD21_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ * @{ */
+#define BOARD_FREQ_SLCK_XTAL (32768U)
+#define BOARD_FREQ_SLCK_BYPASS (32768U)
+#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
+#define BOARD_MCK CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US 15625
+/** @} */
+
+/** \name LED definitions
+ * @{ */
+#define LED0_PIN PIN_PA17 // only for compatibility, this pin is used also by L LED
+#define LED0_ACTIVE false
+#define LED0_INACTIVE !LED0_ACTIVE
+
+#define LEDL_PIN PIN_PA17 //defining LED L PORT PIN
+#define LEDL_ACTIVE true
+#define LEDL_INACTIVE !LEDL_ACTIVE
+
+#define LEDRX_PIN PIN_PB03 //defining LED RX PORT PIN
+#define LEDRX_ACTIVE false
+#define LEDRX_INACTIVE !LEDRX_ACTIVE
+
+#define LEDTX_PIN PIN_PA27 //defining LED TX PORT PIN
+#define LEDTX_ACTIVE false
+#define LEDTX_INACTIVE !LEDTX_ACTIVE
+
+/** @} */
+
+/** \name SW0 definitions
+ * @{ */
+#define SW0_PIN PIN_PA15
+#define SW0_ACTIVE false
+#define SW0_INACTIVE !SW0_ACTIVE
+#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
+#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_LINE 15
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * LED L, LED RX and LED TX are used by Arduino srl SAM D21 based boards. LED 0 remain only for compatibility.
+ *
+ * @{ */
+#define LED_0_NAME "LED0 (yellow)"
+#define LED_0_PIN LED0_PIN
+#define LED_0_ACTIVE LED0_ACTIVE
+#define LED_0_INACTIVE LED0_INACTIVE
+#define LED0_GPIO LED0_PIN
+#define LED0 LED0_PIN
+
+#define LED_L_NAME "LED L"
+#define LED_L_PIN LEDL_PIN
+#define LED_L_ACTIVE LEDL_ACTIVE
+#define LED_L_INACTIVE LEDL_INACTIVE
+#define LEDL_GPIO LEDL_PIN
+#define LEDL LEDL_PIN
+
+#define LED_RX_NAME "LED RX"
+#define LED_RX_PIN LEDRX_PIN
+#define LED_RX_ACTIVE LEDRX_ACTIVE
+#define LED_RX_INACTIVE LEDRX_INACTIVE
+#define LEDRX_GPIO LEDRX_PIN
+#define LEDRX LEDRX_PIN
+
+#define LED_TX_NAME "LED L"
+#define LED_TX_PIN LEDTX_PIN
+#define LED_TX_ACTIVE LEDTX_ACTIVE
+#define LED_TX_INACTIVE LEDTX_INACTIVE
+#define LEDTX_GPIO LEDTX_PIN
+#define LEDTX LEDTX_PIN
+
+#define LED_0_PWM4CTRL_MODULE TCC0
+#define LED_0_PWM4CTRL_CHANNEL 0
+#define LED_0_PWM4CTRL_OUTPUT 0
+#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT 1
+
+/**
+ * \name Serialflash definitions
+ *
+ * On board Serialflash definitions.
+ *
+ * @{ */
+#define SERIALFLASH_SPI_MODULE SERCOM5
+#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
+#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define SERIALFLASH_SPI_CS PIN_PA13
+/** @} */
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * button 0 is used only for compatibility purpose, and are not used in Arduino srl SAM D21 Based Boards.
+ * @{ */
+#define BUTTON_0_NAME "SW0"
+#define BUTTON_0_PIN SW0_PIN
+#define BUTTON_0_ACTIVE SW0_ACTIVE
+#define BUTTON_0_INACTIVE SW0_INACTIVE
+#define BUTTON_0_EIC_PIN SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ * @{
+ */
+#define EXT1_PIN_3 PIN_PB00
+#define EXT1_PIN_4 PIN_PB01
+#define EXT1_PIN_5 PIN_PB06
+#define EXT1_PIN_6 PIN_PB07
+#define EXT1_PIN_7 PIN_PB02
+#define EXT1_PIN_8 PIN_PB03
+#define EXT1_PIN_9 PIN_PB04
+#define EXT1_PIN_10 PIN_PB05
+#define EXT1_PIN_11 PIN_PA08
+#define EXT1_PIN_12 PIN_PA09
+#define EXT1_PIN_13 PIN_PB09
+#define EXT1_PIN_14 PIN_PB08
+#define EXT1_PIN_15 PIN_PA05
+#define EXT1_PIN_16 PIN_PA06
+#define EXT1_PIN_17 PIN_PA04
+#define EXT1_PIN_18 PIN_PA07
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ * @{
+ */
+#define EXT1_PIN_ADC_0 EXT1_PIN_3
+#define EXT1_PIN_ADC_1 EXT1_PIN_4
+#define EXT1_PIN_GPIO_0 EXT1_PIN_5
+#define EXT1_PIN_GPIO_1 EXT1_PIN_6
+#define EXT1_PIN_PWM_0 EXT1_PIN_7
+#define EXT1_PIN_PWM_1 EXT1_PIN_8
+#define EXT1_PIN_IRQ EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL EXT1_PIN_12
+#define EXT1_PIN_UART_RX EXT1_PIN_13
+#define EXT1_PIN_UART_TX EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ * @{
+ */
+#define EXT1_ADC_MODULE ADC
+#define EXT1_ADC_0_CHANNEL 8
+#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
+#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
+#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
+#define EXT1_ADC_1_CHANNEL 9
+#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
+#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
+#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ * @{
+ */
+#define EXT1_PWM_MODULE TC6
+#define EXT1_PWM_0_CHANNEL 0
+#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
+#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
+#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
+#define EXT1_PWM_1_CHANNEL 1
+#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
+#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
+#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT1_IRQ_MODULE EIC
+#define EXT1_IRQ_INPUT 4
+#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ * @{
+ */
+#define EXT1_I2C_MODULE SERCOM2
+#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ * @{
+ */
+#define EXT1_UART_MODULE SERCOM4
+#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ * @{
+ */
+#define EXT1_SPI_MODULE SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 pin definitions
+ * @{
+ */
+#define EXT2_PIN_3 PIN_PA10
+#define EXT2_PIN_4 PIN_PA11
+#define EXT2_PIN_5 PIN_PA20
+#define EXT2_PIN_6 PIN_PA21
+#define EXT2_PIN_7 PIN_PB12
+#define EXT2_PIN_8 PIN_PB13
+#define EXT2_PIN_9 PIN_PB14
+#define EXT2_PIN_10 PIN_PB15
+#define EXT2_PIN_11 PIN_PA08
+#define EXT2_PIN_12 PIN_PA09
+#define EXT2_PIN_13 PIN_PB11
+#define EXT2_PIN_14 PIN_PB10
+#define EXT2_PIN_15 PIN_PA17
+#define EXT2_PIN_16 PIN_PA18
+#define EXT2_PIN_17 PIN_PA16
+#define EXT2_PIN_18 PIN_PA19
+/** @} */
+
+/** \name Extension header #2 pin definitions by function
+ * @{
+ */
+#define EXT2_PIN_ADC_0 EXT2_PIN_3
+#define EXT2_PIN_ADC_1 EXT2_PIN_4
+#define EXT2_PIN_GPIO_0 EXT2_PIN_5
+#define EXT2_PIN_GPIO_1 EXT2_PIN_6
+#define EXT2_PIN_PWM_0 EXT2_PIN_7
+#define EXT2_PIN_PWM_1 EXT2_PIN_8
+#define EXT2_PIN_IRQ EXT2_PIN_9
+#define EXT2_PIN_I2C_SDA EXT2_PIN_11
+#define EXT2_PIN_I2C_SCL EXT2_PIN_12
+#define EXT2_PIN_UART_RX EXT2_PIN_13
+#define EXT2_PIN_UART_TX EXT2_PIN_14
+#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
+#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
+#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
+#define EXT2_PIN_SPI_MISO EXT2_PIN_17
+#define EXT2_PIN_SPI_SCK EXT2_PIN_18
+/** @} */
+
+/** \name Extension header #2 ADC definitions
+ * @{
+ */
+#define EXT2_ADC_MODULE ADC
+#define EXT2_ADC_0_CHANNEL 18
+#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
+#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
+#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
+#define EXT2_ADC_1_CHANNEL 19
+#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
+#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
+#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
+/** @} */
+
+/** \name Extension header #2 PWM definitions
+ * @{
+ */
+#define EXT2_PWM_MODULE TC4
+#define EXT2_PWM_0_CHANNEL 0
+#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
+#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
+#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
+#define EXT2_PWM_1_CHANNEL 1
+#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
+#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
+#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
+/** @} */
+
+/** \name Extension header #2 PWM for Control definitions
+ * @{
+ */
+#define EXT2_PWM4CTRL_MODULE TCC0
+#define EXT2_PWM4CTRL_0_CHANNEL 2
+#define EXT2_PWM4CTRL_0_OUTPUT 6
+#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_1_CHANNEL 3
+#define EXT2_PWM4CTRL_1_OUTPUT 7
+#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
+/** @} */
+
+/** \name Extension header #2 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT2_IRQ_MODULE EIC
+#define EXT2_IRQ_INPUT 14
+#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
+/** @} */
+
+ /** \name Extension header #2 I2C definitions
+ * @{
+ */
+#define EXT2_I2C_MODULE SERCOM2
+#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 UART definitions
+ * @{
+ */
+#define EXT2_UART_MODULE SERCOM4
+#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
+#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
+#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
+#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 SPI definitions
+ * @{
+ */
+#define EXT2_SPI_MODULE SERCOM1
+#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
+#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
+#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
+#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
+#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
+#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ * @{
+ */
+#define EXT3_PIN_3 PIN_PA02
+#define EXT3_PIN_4 PIN_PA03
+#define EXT3_PIN_5 PIN_PB30
+#define EXT3_PIN_6 PIN_PA15
+#define EXT3_PIN_7 PIN_PA12
+#define EXT3_PIN_8 PIN_PA13
+#define EXT3_PIN_9 PIN_PA28
+#define EXT3_PIN_10 PIN_PA27
+#define EXT3_PIN_11 PIN_PA08
+#define EXT3_PIN_12 PIN_PA09
+#define EXT3_PIN_13 PIN_PB11
+#define EXT3_PIN_14 PIN_PB10
+#define EXT3_PIN_15 PIN_PB17
+#define EXT3_PIN_16 PIN_PB22
+#define EXT3_PIN_17 PIN_PB16
+#define EXT3_PIN_18 PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ * @{
+ */
+#define EXT3_PIN_ADC_0 EXT3_PIN_3
+#define EXT3_PIN_ADC_1 EXT3_PIN_4
+#define EXT3_PIN_GPIO_0 EXT3_PIN_5
+#define EXT3_PIN_GPIO_1 EXT3_PIN_6
+#define EXT3_PIN_PWM_0 EXT3_PIN_7
+#define EXT3_PIN_PWM_1 EXT3_PIN_8
+#define EXT3_PIN_IRQ EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL EXT3_PIN_12
+#define EXT3_PIN_UART_RX EXT3_PIN_13
+#define EXT3_PIN_UART_TX EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ * @{
+ */
+#define EXT3_ADC_MODULE ADC
+#define EXT3_ADC_0_CHANNEL 0
+#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
+#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
+#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
+#define EXT3_ADC_1_CHANNEL 1
+#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
+#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
+#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
+/** @} */
+
+/** \name Extension header #3 PWM for Control definitions
+ * @{
+ */
+#define EXT3_PWM4CTRL_MODULE TCC2
+#define EXT3_PWM4CTRL_0_CHANNEL 0
+#define EXT3_PWM4CTRL_0_OUTPUT 0
+#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_1_CHANNEL 1
+#define EXT3_PWM4CTRL_1_OUTPUT 1
+#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT3_IRQ_MODULE EIC
+#define EXT3_IRQ_INPUT 8
+#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ * @{
+ */
+#define EXT3_I2C_MODULE SERCOM2
+#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ * @{
+ */
+#define EXT3_UART_MODULE SERCOM4
+#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
+#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
+#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ * @{
+ */
+#define EXT3_SPI_MODULE SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
+#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 Dataflash
+ * @{
+ */
+#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
+#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN PIN_PA14
+#define USB_VBUS_EIC_LINE 14
+#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
+#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
+//#define USB_ID_PIN PIN_PA03
+#define USB_ID_EIC_LINE 3
+#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
+#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN PIN_PA27
+#define EDBG_GPIO1_PIN PIN_PA28
+#define EDBG_GPIO2_PIN PIN_PA20
+#define EDBG_GPIO3_PIN PIN_PA21
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE SERCOM2
+#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
+#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE SERCOM3
+#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
+/** @} */
+
+/** @} */
+
+/** \name 802.15.4 TRX Interface definitions
+ * @{
+ */
+
+#define AT86RFX_SPI EXT1_SPI_MODULE
+#define AT86RFX_RST_PIN EXT1_PIN_7
+#define AT86RFX_MISC_PIN EXT1_PIN_12
+#define AT86RFX_IRQ_PIN EXT1_PIN_9
+#define AT86RFX_SLP_PIN EXT1_PIN_10
+#define AT86RFX_SPI_CS EXT1_PIN_15
+#define AT86RFX_SPI_MOSI EXT1_PIN_16
+#define AT86RFX_SPI_MISO EXT1_PIN_17
+#define AT86RFX_SPI_SCK EXT1_PIN_18
+#define AT86RFX_CSD EXT1_PIN_5
+#define AT86RFX_CPS EXT1_PIN_8
+
+
+#define AT86RFX_SPI_CONFIG(config) \
+ config.mux_setting = EXT1_SPI_SERCOM_MUX_SETTING; \
+ config.mode_specific.master.baudrate = AT86RFX_SPI_BAUDRATE; \
+ config.pinmux_pad0 = EXT1_SPI_SERCOM_PINMUX_PAD0; \
+ config.pinmux_pad1 = PINMUX_UNUSED; \
+ config.pinmux_pad2 = EXT1_SPI_SERCOM_PINMUX_PAD2; \
+ config.pinmux_pad3 = EXT1_SPI_SERCOM_PINMUX_PAD3;
+
+#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
+#define AT86RFX_INTC_INIT() \
+ struct extint_chan_conf eint_chan_conf; \
+ extint_chan_get_config_defaults(&eint_chan_conf); \
+ eint_chan_conf.gpio_pin = AT86RFX_IRQ_PIN; \
+ eint_chan_conf.gpio_pin_mux = EXT1_IRQ_PINMUX; \
+ eint_chan_conf.gpio_pin_pull = EXTINT_PULL_NONE; \
+ eint_chan_conf.wake_if_sleeping = true; \
+ eint_chan_conf.filter_input_signal = false; \
+ eint_chan_conf.detection_criteria = EXTINT_DETECT_RISING; \
+ extint_chan_set_config(AT86RFX_IRQ_CHAN, &eint_chan_conf); \
+ extint_register_callback(AT86RFX_ISR, AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT);\
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT);
+
+
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ() \
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ() \
+ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ() \
+ extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION() \
+ { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ * This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION() \
+ extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/** @} */
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/port.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/port.c
new file mode 100755
index 0000000000000000000000000000000000000000..945c541547dfce15b671f261f21a7cea218c01d6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/port.c
@@ -0,0 +1,106 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <port.h>
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure.
+ * \param[in] config Configuration settings for the pin.
+ */
+void port_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct port_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ struct system_pinmux_config pinmux_config;
+ system_pinmux_get_config_defaults(&pinmux_config);
+
+ pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+ pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
+ pinmux_config.powersave = config->powersave;
+
+ system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ * \brief Writes a Port group configuration group to the hardware module.
+ *
+ * Writes out a given configuration of a Port group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[out] port Base of the PORT module to write to.
+ * \param[in] mask Mask of the port pin(s) to configure.
+ * \param[in] config Configuration settings for the pin group.
+ */
+void port_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct port_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(port);
+ Assert(config);
+
+ struct system_pinmux_config pinmux_config;
+ system_pinmux_get_config_defaults(&pinmux_config);
+
+ pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+ pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
+ pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
+ pinmux_config.powersave = config->powersave;
+
+ system_pinmux_group_set_config(port, mask, &pinmux_config);
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/port.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/port.h
new file mode 100755
index 0000000000000000000000000000000000000000..414da88526012cc6b62edd666c00590c10b9628e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/port.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef PORT_H_INCLUDED
+#define PORT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_port_group SAM Port Driver (PORT)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of the device's General Purpose Input/Output (GPIO) pin
+ * functionality, for manual pin state reading and writing.
+ *
+ * The following peripherals are used by this module:
+ * - PORT (GPIO Management)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_port_prerequisites
+ * - \ref asfdoc_sam0_port_module_overview
+ * - \ref asfdoc_sam0_port_special_considerations
+ * - \ref asfdoc_sam0_port_extra_info
+ * - \ref asfdoc_sam0_port_examples
+ * - \ref asfdoc_sam0_port_api_overview
+ *
+ *
+ * \section asfdoc_sam0_port_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_port_module_overview Module Overview
+ *
+ * The device GPIO (PORT) module provides an interface between the user
+ * application logic and external hardware peripherals, when general pin state
+ * manipulation is required. This driver provides an easy-to-use interface to
+ * the physical pin input samplers and output drivers, so that pins can be read
+ * from or written to for general purpose external hardware control.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical, and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_port_module_int_connections
+ * \dot
+ * digraph overview {
+ * node [label="Port Pad" shape=square] pad;
+ *
+ * subgraph driver {
+ * node [label="Peripheral Mux" shape=trapezium] pinmux;
+ * node [label="GPIO Module" shape=ellipse] gpio;
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ * }
+ *
+ * pinmux -> gpio;
+ * pad -> pinmux;
+ * pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_port_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampler can be disabled when the pin is configured
+ * in pure output mode to save power; reading the pin state of a pin configured
+ * in output-only mode will read the logical output state that was last set.
+ *
+ * \section asfdoc_sam0_port_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_port_extra. This includes:
+ * - \ref asfdoc_sam0_port_extra_acronyms
+ * - \ref asfdoc_sam0_port_extra_dependencies
+ * - \ref asfdoc_sam0_port_extra_errata
+ * - \ref asfdoc_sam0_port_extra_history
+ *
+ *
+ * \section asfdoc_sam0_port_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_port_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_port_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \name PORT Alias Macros
+ * @{
+ */
+
+/** Convenience definition for GPIO module group A on the device (if
+ * available). */
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
+# define PORTA PORT->Group[0]
+#endif
+
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group B on the device (if
+ * available). */
+# define PORTB PORT->Group[1]
+#endif
+
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group C on the device (if
+ * available). */
+# define PORTC PORT->Group[2]
+#endif
+
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group D on the device (if
+ * available). */
+# define PORTD PORT->Group[3]
+#endif
+
+/** @} */
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum port_pin_dir {
+ /** The pin's input buffer should be enabled, so that the pin state can
+ * be read. */
+ PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,
+ /** The pin's output buffer should be enabled, so that the pin state can
+ * be set. */
+ PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+ /** The pin's output and input buffers should be enabled, so that the pin
+ * state can be set and read back. */
+ PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum port_pin_pull {
+ /** No logical pull should be applied to the pin. */
+ PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+ /** Pin should be pulled up when idle. */
+ PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
+ /** Pin should be pulled down when idle. */
+ PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should be
+ * initialized by the \ref port_get_config_defaults() function before being
+ * modified by the user application.
+ */
+struct port_config {
+ /** Port buffer input/output direction. */
+ enum port_pin_dir direction;
+
+ /** Port pull-up/pull-down for input pins. */
+ enum port_pin_pull input_pull;
+
+ /** Enable lowest possible powerstate on the pin
+ *
+ * \note All other configurations will be ignored, the pin will be disabled
+ */
+ bool powersave;
+};
+
+/** \name State reading/writing (physical group orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to convert.
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* port_get_group_from_gpio_pin(
+ const uint8_t gpio_pin)
+{
+ return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+}
+
+/**
+ * \brief Retrieves the state of a group of port pins that are configured as inputs.
+ *
+ * Reads the current logic level of a port module's pins and returns the
+ * current levels as a bitmask.
+ *
+ * \param[in] port Base of the PORT module to read from.
+ * \param[in] mask Mask of the port pin(s) to read.
+ *
+ * \return Status of the port pin(s) input buffers.
+ */
+static inline uint32_t port_group_get_input_level(
+ const PortGroup *const port,
+ const uint32_t mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ return (port->IN.reg & mask);
+}
+
+/**
+ * \brief Retrieves the state of a group of port pins that are configured as outputs.
+ *
+ * Reads the current logical output level of a port module's pins and returns
+ * the current levels as a bitmask.
+ *
+ * \param[in] port Base of the PORT module to read from.
+ * \param[in] mask Mask of the port pin(s) to read.
+ *
+ * \return Status of the port pin(s) output buffers.
+ */
+static inline uint32_t port_group_get_output_level(
+ const PortGroup *const port,
+ const uint32_t mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ return (port->OUT.reg & mask);
+}
+
+/**
+ * \brief Sets the state of a group of port pins that are configured as outputs.
+ *
+ * Sets the current output level of a port module's pins to a given logic
+ * level.
+ *
+ * \param[out] port Base of the PORT module to write to.
+ * \param[in] mask Mask of the port pin(s) to change.
+ * \param[in] level_mask Mask of the port level(s) to set.
+ */
+static inline void port_group_set_output_level(
+ PortGroup *const port,
+ const uint32_t mask,
+ const uint32_t level_mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ port->OUTSET.reg = (mask & level_mask);
+ port->OUTCLR.reg = (mask & ~level_mask);
+}
+
+/**
+ * \brief Toggles the state of a group of port pins that are configured as an outputs.
+ *
+ * Toggles the current output levels of a port module's pins.
+ *
+ * \param[out] port Base of the PORT module to write to.
+ * \param[in] mask Mask of the port pin(s) to toggle.
+ */
+static inline void port_group_toggle_output_level(
+ PortGroup *const port,
+ const uint32_t mask)
+{
+ /* Sanity check arguments */
+ Assert(port);
+
+ port->OUTTGL.reg = mask;
+}
+
+/** @} */
+
+/** \name Configuration and initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin/group configuration structure to defaults.
+ *
+ * Initializes a given Port pin/group configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input mode with internal pullup enabled
+ *
+ * \param[out] config Configuration structure to initialize to default values.
+ */
+static inline void port_get_config_defaults(
+ struct port_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->direction = PORT_PIN_DIR_INPUT;
+ config->input_pull = PORT_PIN_PULL_UP;
+ config->powersave = false;
+}
+
+void port_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct port_config *const config);
+
+void port_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct port_config *const config);
+
+/** @} */
+
+/** \name State reading/writing (logical pin orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the state of a port pin that is configured as an input.
+ *
+ * Reads the current logic level of a port pin and returns the current
+ * level as a boolean value.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to read.
+ *
+ * \return Status of the port pin's input buffer.
+ */
+static inline bool port_pin_get_input_level(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ return (port_base->IN.reg & pin_mask);
+}
+
+/**
+ * \brief Retrieves the state of a port pin that is configured as an output.
+ *
+ * Reads the current logical output level of a port pin and returns the current
+ * level as a boolean value.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to read.
+ *
+ * \return Status of the port pin's output buffer.
+ */
+static inline bool port_pin_get_output_level(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ return (port_base->OUT.reg & pin_mask);
+}
+
+/**
+ * \brief Sets the state of a port pin that is configured as an output.
+ *
+ * Sets the current output level of a port pin to a given logic level.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to write to.
+ * \param[in] level Logical level to set the given pin to.
+ */
+static inline void port_pin_set_output_level(
+ const uint8_t gpio_pin,
+ const bool level)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ /* Set the pin to high or low atomically based on the requested level */
+ if (level) {
+ port_base->OUTSET.reg = pin_mask;
+ } else {
+ port_base->OUTCLR.reg = pin_mask;
+ }
+}
+
+/**
+ * \brief Toggles the state of a port pin that is configured as an output.
+ *
+ * Toggles the current output level of a port pin.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to toggle.
+ */
+static inline void port_pin_toggle_output_level(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ /* Toggle pin output level */
+ port_base->OUTTGL.reg = pin_mask;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
+ *
+ * \section asfdoc_sam0_port_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>GPIO</td>
+ * <td>General Purpose Input/Output</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_port_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_port_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_port_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_port_basic_use_case
+ *
+ * \page asfdoc_sam0_port_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>04/2014</td>
+ * <td>Added support for SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>02/2014</td>
+ * <td>Added support for SAMR21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h
new file mode 100755
index 0000000000000000000000000000000000000000..39414b2b333ff5d7da3bf7b48410ab5b3e176770
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
+ *
+ * In this use case, the PORT module is configured for:
+ * \li One pin in input mode, with pull-up enabled
+ * \li One pin in output mode
+ *
+ * This use case sets up the PORT to read the current state of a GPIO pin set as
+ * an input, and mirrors the opposite logical state on a pin configured as an
+ * output.
+ *
+ * \section asfdoc_sam0_port_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_port_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_port_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
+ * -# Create a PORT module pin configuration struct, which can be filled out to
+ * adjust the configuration of a single port pin.
+ * \snippet qs_port_basic.c setup_1
+ * -# Initialize the pin configuration struct with the module's default values.
+ * \snippet qs_port_basic.c setup_2
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Adjust the configuration struct to request an input pin.
+ * \snippet qs_port_basic.c setup_3
+ * -# Configure push button pin with the initialized pin configuration struct, to enable
+ * the input sampler on the pin.
+ * \snippet qs_port_basic.c setup_4
+ * -# Adjust the configuration struct to request an output pin.
+ * \snippet qs_port_basic.c setup_5
+ * \note The existing configuration struct may be re-used, as long as any
+ * values that have been altered from the default settings are taken
+ * into account by the user application.
+ *
+ * -# Configure LED pin with the initialized pin configuration struct, to enable
+ * the output driver on the pin.
+ * \snippet qs_port_basic.c setup_6
+ *
+ * \section asfdoc_sam0_port_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_port_basic.c main
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
+ * -# Read in the current input sampler state of push button pin, which has been
+ * configured as an input in the use-case setup code.
+ * \snippet qs_port_basic.c main_1
+ * -# Write the inverted pin level state to LED pin, which has been configured as
+ * an output in the use-case setup code.
+ * \snippet qs_port_basic.c main_2
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/quick_start_count/qs_rtc_count_basic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/quick_start_count/qs_rtc_count_basic.h
new file mode 100755
index 0000000000000000000000000000000000000000..f4c6b36169217e05634da0253cd18b512ca97697
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/quick_start_count/qs_rtc_count_basic.h
@@ -0,0 +1,117 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Count Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_rtc_count_basic_use_case Quick Start Guide for RTC (COUNT) - Basic
+ * In this use case, the RTC is set up in count mode. The example configures the
+ * RTC in 16 bit mode, with continuous updates to the COUNT register, together
+ * with a set compare register value. Every 2000ms a LED on the board is
+ * toggled.
+ *
+ * \section asfdoc_sam0_rtc_count_basic_use_case_prereq Prerequisites
+ * The Generic Clock Generator for the RTC should be configured and enabled; if
+ * you are using the System Clock driver, this may be done via \c conf_clocks.h.
+ *
+ * \subsection asfdoc_sam0_rtc_count_basic_use_case_setup_clocks Clocks and Oscillators
+ * The \c conf_clock.h file needs to be changed with the following values to
+ * configure the clocks and oscillators for the module.
+ *
+ * The following oscillator settings are needed:
+ * \snippet conf_clocks.h oscillator_settings
+ * The following generic clock settings are needed:
+ * \snippet conf_clocks.h gclk_settings
+ *
+ * \section asfdoc_sam0_rtc_count_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_rtc_count_basic_use_case_init_code Initialization Code
+ * Create a rtc_module struct and add to the main application source file,
+ * outside of any functions:
+ * \snippet qs_rtc_count_basic.c rtc_module_instance
+ *
+ * Copy-paste the following setup code to your applications \c main():
+ * \snippet qs_rtc_count_basic.c initiate
+ *
+ * \subsection asfdoc_sam0_rtc_count_basic_use_case_main_code Add to Main
+ * Add the following to your \c main().
+ * \snippet qs_rtc_count_basic.c add_main
+ *
+ * \subsection rtc_count_basic_use_workflow Workflow
+ * -# Create a RTC configuration structure to hold the desired RTC driver
+ * settings.
+ * \snippet qs_rtc_count_basic.c set_conf
+ * -# Fill the configuration structure with the default driver configuration.
+ * \snippet qs_rtc_count_basic.c get_default
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Alter the RTC driver configuration to run in 16-bit counting mode, with
+ * continuous counter register updates.
+ * \snippet qs_rtc_count_basic.c set_config
+ * -# Initialize the RTC module.
+ * \snippet qs_rtc_count_basic.c init_rtc
+ * -# Enable the RTC module, so that it may begin counting.
+ * \snippet qs_rtc_count_basic.c enable
+ *
+ * \section asfdoc_sam0_rtc_count_basic_use_case_implement Implementation
+ * Code used to implement the initialized module.
+ *
+ * \subsection asfdoc_sam0_rtc_count_basic_use_case_imp_code Code
+ * Add after initialization in main().
+ * \snippet qs_rtc_count_basic.c implementation_code
+ *
+ * \subsection asfdoc_sam0_rtc_count_basic_use_case_imp_workflow Workflow
+ * -# Set RTC period to 2000ms (2 seconds) so that it will overflow and reset
+ * back to zero every two seconds.
+ * \snippet qs_rtc_count_basic.c period
+ * -# Enter an infinite loop to poll the RTC driver to check when a comparison
+ * match occurs.
+ * \snippet qs_rtc_count_basic.c main_loop
+ * -# Check if the RTC driver has found a match on compare channel 0 against the
+ * current RTC count value.
+ * \snippet qs_rtc_count_basic.c check_match
+ * -# Once a compare match occurs, perform the desired user action.
+ * \snippet qs_rtc_count_basic.c compare_match_action
+ * -# Clear the compare match, so that future matches may occur.
+ * \snippet qs_rtc_count_basic.c clear_compare_match
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/quick_start_count_callback/qs_rtc_count_callback.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/quick_start_count_callback/qs_rtc_count_callback.h
new file mode 100755
index 0000000000000000000000000000000000000000..7eb7a9eb8ac3a03d5045ee4fb4f947dacd0e789a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/quick_start_count_callback/qs_rtc_count_callback.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Count Quick Start
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_rtc_count_callback_use_case Quick Start Guide for RTC (COUNT) - Callback
+ *
+ * In this use case, the RTC is set up in count mode. The quick start
+ * configures the RTC in 16 bit mode and to continuously update COUNT register.
+ * The rest of the configuration is according to the
+ * \ref rtc_count_get_config_defaults "default".
+ * A callback is implemented for when the RTC overflows.
+ *
+ * \section asfdoc_sam0_rtc_count_callback_use_case_prereq Prerequisites
+ * The Generic Clock Generator for the RTC should be configured and enabled; if
+ * you are using the System Clock driver, this may be done via \c conf_clocks.h.
+ *
+ * \subsection asfdoc_sam0_rtc_count_callback_use_case_setup_clocks Clocks and Oscillators
+ * The \c conf_clock.h file needs to be changed with the following values to
+ * configure the clocks and oscillators for the module.
+ *
+ * The following oscillator settings are needed:
+ * \snippet conf_clocks.h oscillator_settings
+ * The following generic clock settings are needed:
+ * \snippet conf_clocks.h gclk_settings
+ *
+ * \section asfdoc_sam0_rtc_count_callback_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_rtc_count_callback_use_case_setup_code Code
+ * Create a rtc_module struct and add to the main application source file,
+ * outside of any functions:
+ * \snippet qs_rtc_count_callback.c rtc_module_instance
+ * The following must be added to the user application:
+ *
+ * Function for setting up the module:
+ * \snippet qs_rtc_count_callback.c initialize_rtc
+ *
+ * Callback function:
+ * \snippet qs_rtc_count_callback.c callback
+ *
+ * Function for setting up the callback functionality of the driver:
+ * \snippet qs_rtc_count_callback.c setup_callback
+*
+ * Add to user application main():
+ * \snippet qs_rtc_count_callback.c run_initialize_rtc
+ *
+ * \subsection asfdoc_sam0_rtc_count_callback_use_case_setup_workflow Workflow
+ * -# Initialize system.
+ * \snippet qs_rtc_count_callback.c system_init
+ * -# Configure and enable module.
+ * \snippet qs_rtc_count_callback.c run_conf
+ * -# Create a RTC configuration structure to hold the desired RTC driver
+ * settings and fill it with the default driver configuration values.
+ * \snippet qs_rtc_count_callback.c init_conf
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Alter the RTC driver configuration to run in 16-bit counting mode, with
+ * continuous counter register updates and a compare value of 1000ms.
+ * \snippet qs_rtc_count_callback.c set_config
+ * -# Initialize the RTC module.
+ * \snippet qs_rtc_count_callback.c init_rtc
+ * -# Enable the RTC module, so that it may begin counting.
+ * \snippet qs_rtc_count_callback.c enable
+ * -# Configure callback functionality.
+ * \snippet qs_rtc_count_callback.c run_callback
+ * -# Register overflow callback.
+ * \snippet qs_rtc_count_callback.c reg_callback
+ * -# Enable overflow callback.
+ * \snippet qs_rtc_count_callback.c en_callback
+ * -# Set period.
+ * \snippet qs_rtc_count_callback.c period
+ *
+ * \section asfdoc_sam0_rtc_count_callback_use_case_implementation Implementation
+ *
+ * \subsection asfdoc_sam0_rtc_count_callback_use_case_implementation_code Code
+ * Add to user application main:
+ * \snippet qs_rtc_count_callback.c while
+ * \subsection asfdoc_sam0_rtc_count_callback_use_case_implementation_workflow Workflow
+ * -# Infinite while loop while waiting for callbacks.
+ * \snippet qs_rtc_count_callback.c while
+ *
+ * \section asfdoc_sam0_rtc_count_callback_use_case_callback Callback
+ * Each time the RTC counter overflows, the callback function will be called.
+ * \subsection asfdoc_sam0_rtc_count_callback_use_case_callback_workflow Workflow
+ * -# Perform the desired user action for each RTC overflow:
+ * \snippet qs_rtc_count_callback.c overflow_act
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count.c
new file mode 100755
index 0000000000000000000000000000000000000000..80f91ca69cc17075daf216b82d79ab3855c2855e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count.c
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Mode)
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "rtc_count.h"
+#include <gclk.h>
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+/**
+ * \brief Resets the RTC module.
+ * Resets the RTC to hardware defaults.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ */
+void rtc_count_reset(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Disable module before reset. */
+ rtc_count_disable(module);
+
+#if RTC_COUNT_ASYNC == true
+ module->registered_callback = 0;
+ module->enabled_callback = 0;
+#endif
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Initiate software reset. */
+ rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST;
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * hardware module
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] config Pointer to the configuration structure.
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK RTC configurations was set successfully.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given.
+ */
+static enum status_code _rtc_count_set_config(
+ struct rtc_module *const module,
+ const struct rtc_count_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler;
+
+ /* Set mode and clear on match if applicable. */
+ switch (config->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Set 32bit mode and clear on match if applicable. */
+ rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0);
+
+ /* Check if clear on compare match should be set. */
+ if (config->clear_on_match) {
+ /* Set clear on match. */
+ rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR;
+ }
+ /* Set compare values. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) {
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ rtc_count_set_compare(module, config->compare_values[i],
+ (enum rtc_count_compare)i);
+ }
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Set 16bit mode. */
+ rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1);
+
+ /* Check if match on clear is set, and return invalid
+ * argument if set. */
+ if (config->clear_on_match) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+ /* Set compare values. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ rtc_count_set_compare(module, config->compare_values[i],
+ (enum rtc_count_compare)i);
+ }
+ break;
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check to set continuously clock read update mode. */
+ if (config->continuously_update) {
+ /* Set continuously mode. */
+ rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT;
+ }
+
+ /* Return status OK if everything was configured. */
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module Pointer to the software instance struct
+ * \param[in] hw Pointer to hardware instance
+ * \param[in] config Pointer to the configuration structure.
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK If the initialization was run stressfully.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given.
+ */
+enum status_code rtc_count_init(
+ struct rtc_module *const module,
+ Rtc *const hw,
+ const struct rtc_count_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(hw);
+ Assert(config);
+
+ /* Initialize device instance */
+ module->hw = hw;
+
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
+
+ /* Set up GCLK */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
+ system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
+ system_gclk_chan_enable(RTC_GCLK_ID);
+
+ /* Reset module to hardware defaults. */
+ rtc_count_reset(module);
+
+ /* Save conf_struct internally for continued use. */
+ module->mode = config->mode;
+ module->continuously_update = config->continuously_update;
+
+# if (RTC_INST_NUM == 1)
+ _rtc_instance[0] = module;
+# else
+ /* Register this instance for callbacks*/
+ _rtc_instance[_rtc_get_inst_index(hw)] = module;
+# endif
+
+ /* Set config and return status. */
+ return _rtc_count_set_config(module, config);
+}
+
+/**
+ * \brief Set the current count value to desired value.
+ *
+ * Sets the value of the counter to the specified value.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] count_value The value to be set in count register.
+ *
+ * \return Status of setting the register.
+ * \retval STATUS_OK If everything was executed correctly.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ */
+enum status_code rtc_count_set_count(
+ struct rtc_module *const module,
+ const uint32_t count_value)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set count according to mode */
+ switch(module->mode){
+ case RTC_COUNT_MODE_32BIT:
+ /* Write value to register. */
+ rtc_module->MODE0.COUNT.reg = count_value;
+
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Check if 16 bit value is provided. */
+ if(count_value > 0xffff){
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Write value to register. */
+ rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
+
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+ return STATUS_OK;
+}
+
+/**
+ * \brief Get the current count value.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ *
+ * Returns the current count value.
+ *
+ * \return The current counter value as a 32 bit unsigned integer.
+ */
+uint32_t rtc_count_get_count(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Initialize return value. */
+ uint32_t ret_val;
+
+ /* Change of read method based on value of continuously_update value in
+ * the configuration structure. */
+ if(!(module->continuously_update)) {
+ /* Request read on count register. */
+ rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ;
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+ }
+
+ /* Read value based on mode. */
+ switch (module->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Return count value in 32 bit mode. */
+ ret_val = rtc_module->MODE0.COUNT.reg;
+
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Return count value in 16 bit mode. */
+ ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
+
+ break;
+
+ default:
+ Assert(false);
+ /* Counter not initialized. Assume counter value 0.*/
+ ret_val = 0;
+ break;
+ }
+
+ return ret_val;
+}
+
+/**
+ * \brief Set the compare value for the specified compare.
+ *
+ * Sets the value specified by the implementer to the requested compare.
+ *
+ * \note Compare 4 and 5 are only available in 16 bit mode.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] comp_value The value to be written to the compare.
+ * \param[in] comp_index Index of the compare to set.
+ *
+ * \return Status indicating if compare was successfully set.
+ * \retval STATUS_OK If compare was successfully set.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode.
+ */
+enum status_code rtc_count_set_compare(
+ struct rtc_module *const module,
+ const uint32_t comp_value,
+ const enum rtc_count_compare comp_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set compare values based on operation mode. */
+ switch (module->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Check sanity of comp_index. */
+ if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Set compare value for COMP. */
+ rtc_module->MODE0.COMP[comp_index].reg = comp_value;
+
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Check sanity of comp_index. */
+ if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check that 16 bit value is provided. */
+ if (comp_value > 0xffff) {
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Set compare value for COMP. */
+ rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
+
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_BAD_FORMAT;
+ }
+
+ /* Return status if everything is OK. */
+ return STATUS_OK;
+}
+
+/**
+ * \brief Get the current compare value of specified compare.
+ *
+ * Retrieves the current value of the specified compare.
+ *
+ * \note Compare 4 and 5 are only available in 16 bit mode.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[out] comp_value Pointer to 32 bit integer that will be populated with
+ * the current compare value.
+ * \param[in] comp_index Index of compare to check.
+ *
+ * \return Status of the reading procedure.
+ * \retval STATUS_OK If the value was read correctly.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode.
+ */
+enum status_code rtc_count_get_compare(
+ struct rtc_module *const module,
+ uint32_t *const comp_value,
+ const enum rtc_count_compare comp_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ switch (module->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Check sanity of comp_index. */
+ if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Get compare value for COMP. */
+ *comp_value = rtc_module->MODE0.COMP[comp_index].reg;
+
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Check sanity of comp_index. */
+ if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Get compare value for COMP. */
+ *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
+
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_BAD_FORMAT;
+ }
+ /* Return status showing everything is OK. */
+ return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the value of period.
+ *
+ * Retrieves the value of the period for the 16 bit mode counter.
+ *
+ * \note Only available in 16 bit mode.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[out] period_value Pointer to value for return argument.
+ *
+ * \return Status of getting the period value.
+ * \retval STATUS_OK If the period value was read correctly.
+ * \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set.
+ */
+enum status_code rtc_count_get_period(
+ struct rtc_module *const module,
+ uint16_t *const period_value)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Check that correct mode is set. */
+ if (module->mode != RTC_COUNT_MODE_16BIT) {
+ return STATUS_ERR_UNSUPPORTED_DEV;
+ }
+
+ /* Returns the value. */
+ *period_value = rtc_module->MODE1.PER.reg;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Set the given value to the period.
+ *
+ * Sets the given value to the period.
+ *
+ * \note Only available in 16 bit mode.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] period_value The value to set to the period.
+ *
+ * \return Status of setting the period value.
+ * \retval STATUS_OK If the period was set correctly.
+ * \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16 bit mode.
+ */
+enum status_code rtc_count_set_period(
+ struct rtc_module *const module,
+ const uint16_t period_value)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Check that correct mode is set. */
+ if (module->mode != RTC_COUNT_MODE_16BIT) {
+ return STATUS_ERR_UNSUPPORTED_DEV;
+ }
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Write value to register. */
+ rtc_module->MODE1.PER.reg = period_value;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Check if RTC compare match has occurred.
+ *
+ * Checks the compare flag to see if a match has occurred. The compare flag is
+ * set when there is a compare match between counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16 bit mode.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] comp_index Index of compare to check current flag.
+ */
+bool rtc_count_is_compare_match(
+ struct rtc_module *const module,
+ const enum rtc_count_compare comp_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Check sanity. */
+ switch (module->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Check sanity for 32 bit mode. */
+ if (comp_index > RTC_NUM_OF_COMP32) {
+ return false;
+ }
+
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Check sanity for 16 bit mode. */
+ if (comp_index > RTC_NUM_OF_COMP16) {
+ return false;
+ }
+
+ break;
+
+ default:
+ Assert(false);
+ return false;
+ }
+
+ /* Set status of INTFLAG as return argument. */
+ return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index));
+}
+
+/**
+ * \brief Clears RTC compare match flag.
+ *
+ * Clears the compare flag. The compare flag is set when there is a compare
+ * match between the counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16 bit mode.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] comp_index Index of compare to check current flag.
+ *
+ * \return Status indicating if flag was successfully cleared.
+ * \retval STATUS_OK If flag was successfully cleared.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode.
+ */
+enum status_code rtc_count_clear_compare_match(
+ struct rtc_module *const module,
+ const enum rtc_count_compare comp_index)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Check sanity. */
+ switch (module->mode){
+ case RTC_COUNT_MODE_32BIT:
+ /* Check sanity for 32 bit mode. */
+ if (comp_index > RTC_NUM_OF_COMP32) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ break;
+
+ case RTC_COUNT_MODE_16BIT:
+ /* Check sanity for 16 bit mode. */
+ if (comp_index > RTC_NUM_OF_COMP16) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_BAD_FORMAT;
+ }
+
+ /* Clear INTFLAG. */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between 0 and 127, allowing for a maximum 127 PPM correction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated in 1Hz.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] value Ranging from -127 to 127 used for the correction.
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK If calibration was executed correctly.
+ * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
+ */
+enum status_code rtc_count_frequency_correction(
+ struct rtc_module *const module,
+ const int8_t value)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Check if valid argument. */
+ if (abs(value) > 0x7F) {
+ /* Value bigger than allowed, return invalid argument. */
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ uint32_t new_correction_value;
+
+ /* Load the new correction value as a positive value, sign added later */
+ new_correction_value = abs(value);
+
+ /* Convert to positive value and adjust register sign bit. */
+ if (value < 0) {
+ new_correction_value |= RTC_FREQCORR_SIGN;
+ }
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Set value. */
+ rtc_module->MODE0.FREQCORR.reg = new_correction_value;
+
+ return STATUS_OK;
+}
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count.h
new file mode 100755
index 0000000000000000000000000000000000000000..90724f66dc795d1847b5c1b05fde836831fe3fca
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count.h
@@ -0,0 +1,935 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Mode)
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef RTC_COUNT_H_INCLUDED
+#define RTC_COUNT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_rtc_count_group SAM RTC Count Driver (RTC COUNT)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of the device's Real Time Clock functionality in Count
+ * operating mode, for the configuration and retrieval of the current RTC
+ * counter value. The following driver API modes are covered by this
+ * manual:
+ *
+ * - Polled APIs
+ * \if RTC_COUNT_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ * - RTC (Real Time Clock)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_rtc_count_prerequisites
+ * - \ref asfdoc_sam0_rtc_count_module_overview
+ * - \ref asfdoc_sam0_rtc_count_special_considerations
+ * - \ref asfdoc_sam0_rtc_count_extra_info
+ * - \ref asfdoc_sam0_rtc_count_examples
+ * - \ref asfdoc_sam0_rtc_count_api_overview
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_module_overview Module Overview
+ *
+ * The RTC module in the SAM devices is a 32-bit counter, with a 10-bit
+ * programmable prescaler. Typically, the RTC clock is run continuously,
+ * including in the device's low-power sleep modes, to track the current time
+ * and date information. The RTC can be used as a source to wake up the system
+ * at a scheduled time or periodically using the alarm functions.
+ *
+ * In this driver, the RTC is operated in Count mode. This allows for an
+ * easy integration of an asynchronous counter into a user application, which is
+ * capable of operating while the device is in sleep mode.
+ *
+ * Whilst operating in Count mode, the RTC features:
+ * - 16-bit counter mode
+ * - Selectable counter period
+ * - Up to 6 configurable compare values
+ * - 32-bit counter mode
+ * - Clear counter value on match
+ * - Up to 4 configurable compare values
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_module_overview_compares Compare and Overflow
+ * The RTC can be used with up to 4/6 compare values (depending on selected
+ * operation mode). These compare values will trigger on match with the current
+ * RTC counter value, and can be set up to trigger an interrupt, event, or both.
+ * The RTC can also be configured to clear the counter value on compare match
+ * in 32-bit mode, resetting the count value back to zero.
+ *
+ * If the RTC is operated without the Clear on Match option enabled, or in
+ * 16-bit mode, the RTC counter value will instead be cleared on overflow once
+ * the maximum count value has been reached:
+ *
+ * \f[ COUNT_{MAX} = 2^{32}-1 \f] for 32-bit counter mode, and
+ * \f[ COUNT_{MAX} = 2^{16}-1 \f] for 16-bit counter mode.
+ *
+ * When running in 16-bit mode, the overflow value is selectable with a period
+ * value. The counter overflow will then occur when the counter value reaches
+ * the specified period value.
+ *
+ * \subsection asfdoc_sam0_rtc_count_module_overview_periodic Periodic Events
+ * The RTC can generate events at periodic intervals, allowing for direct
+ * peripheral actions without CPU intervention. The periodic events can be
+ * generated on the upper 8 bits of the RTC prescaler, and will be generated on
+ * the rising edge transition of the specified bit. The resulting periodic
+ * frequency can be calculated by the following formula:
+ *
+ * \f[ f_{PERIODIC}=\frac{f_{ASY}}{2^{n+3}} \f]
+ *
+ * Where \f$f_{ASY}\f$ refers to the \e asynchronous clock set up in the RTC
+ * module configuration. The \b n parameter is the event source generator index
+ * of the RTC module. If the asynchronous clock is operated at the recommended
+ * frequency of 1 KHz, the formula results in the values shown in
+ * \ref asfdoc_sam0_rtc_count_module_rtc_hz "the table below".
+ *
+ * \anchor asfdoc_sam0_rtc_count_module_rtc_hz
+ * <table>
+ * <caption>RTC event frequencies for each prescaler bit using a 1KHz clock</caption>
+ * <tr>
+ * <th>n</th> <th>Periodic event</th>
+ * </tr>
+ * <tr>
+ * <td>7</td> <td>1 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>6</td> <td>2 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>5</td> <td>4 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>4</td> <td>8 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>3</td> <td>16 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>2</td> <td>32 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>1</td> <td>64 Hz</td>
+ * </tr>
+ * <tr>
+ * <td>0</td> <td>128 Hz</td>
+ * </tr>
+ * </table>
+ *
+ * \note The connection of events between modules requires the use of the
+ * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ * to route output event of one module to the the input event of another.
+ * For more information on event routing, refer to the event driver
+ * documentation.
+ *
+ * \subsection asfdoc_sam0_rtc_count_module_overview_correction Digital Frequency Correction
+ * The RTC module contains Digital Frequency Correction logic to compensate for
+ * inaccurate source clock frequencies which would otherwise result in skewed
+ * time measurements. The correction scheme requires that at least two bits
+ * in the RTC module prescaler are reserved by the correction logic. As a
+ * result of this implementation, frequency correction is only available when
+ * the RTC is running from a 1 Hz reference clock.
+ *
+ * The correction procedure is implemented by subtracting or adding a single
+ * cycle from the RTC prescaler every 1024 RTC GCLK cycles. The adjustment is
+ * applied the specified number of time (max 127) over 976 of these periods. The
+ * corresponding correction in PPM will be given by:
+ *
+ * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
+ *
+ * The RTC clock will tick faster if provided with a positive correction value,
+ * and slower when given a negative correction value.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_rtc_count_special_considerations_clock Clock Setup
+ * The RTC is typically clocked by a specialized GCLK generator that has a
+ * smaller prescaler than the others. By default the RTC clock is on, selected
+ * to use the internal 32 KHz RC-oscillator with a prescaler of 32, giving a
+ * resulting clock frequency of 1 KHz to the RTC. When the internal RTC
+ * prescaler is set to 1024, this yields an end-frequency of 1 Hz.
+ *
+ * The implementer also has the option to set other end-frequencies.
+ * \ref asfdoc_sam0_rtc_count_rtc_out_freq "The table below" lists the
+ * available RTC frequencies for each possible GCLK and RTC input prescaler
+ * options.
+ *
+ * \anchor asfdoc_sam0_rtc_count_rtc_out_freq
+ * <table>
+ * <caption>RTC output frequencies from allowable input clocks</caption>
+ * <tr>
+ * <th>End-frequency</th>
+ * <th>GCLK prescaler</th>
+ * <th>RTC Prescaler</th>
+ * </tr>
+ * <tr>
+ * <td>32 KHz</td>
+ * <td>1</td>
+ * <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1 KHz</td>
+ * <td>32</td>
+ * <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>1 Hz</td>
+ * <td>32</td>
+ * <td>1024</td>
+ * </tr>
+ * </table>
+ *
+ * The overall RTC module clocking scheme is shown in
+ * \ref asfdoc_sam0_rtc_count_rtc_clock_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_rtc_count_rtc_clock_fig
+ * \dot
+ * digraph clocking_scheme {
+ * rankdir=LR;
+ * GCLK [shape="record", label="<f0> GCLK | <f1> RTC_GCLK",
+ * bgcolor="lightgray", style="filled"];
+ * RTCPRE [shape="record" label="<f0> RTC | <f1> RTC PRESCALER"];
+ * RTC [shape="record", label="<f0> RTC | <f1> RTC CLOCK"];
+ *
+ * GCLK:f1 -> RTCPRE:f1;
+ * RTCPRE:f1 -> RTC:f1;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_rtc_count_extra. This includes:
+ * - \ref asfdoc_sam0_rtc_count_extra_acronyms
+ * - \ref asfdoc_sam0_rtc_count_extra_dependencies
+ * - \ref asfdoc_sam0_rtc_count_extra_errata
+ * - \ref asfdoc_sam0_rtc_count_extra_history
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_rtc_count_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <conf_clocks.h>
+
+#if RTC_COUNT_ASYNC == true
+# include <system_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Available operation modes for the RTC.
+ *
+ * RTC Count operating modes, to select the counting width and associated module
+ * operation.
+ */
+enum rtc_count_mode {
+ /** RTC Count module operates in 16-bit mode. */
+ RTC_COUNT_MODE_16BIT = 0,
+ /** RTC Count module operates in 32-bit mode. */
+ RTC_COUNT_MODE_32BIT = 1,
+};
+
+/**
+ * \brief Available compare channels.
+ *
+ * \note Not all compare channels are available in all devices and modes.
+ */
+enum rtc_count_compare {
+ /** Compare channel 0. */
+ RTC_COUNT_COMPARE_0 = 0,
+#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+ /** Compare channel 1. */
+ RTC_COUNT_COMPARE_1 = 1,
+#endif
+#if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+ /** Compare channel 2. */
+ RTC_COUNT_COMPARE_2 = 2,
+#endif
+#if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+ /** Compare channel 3. */
+ RTC_COUNT_COMPARE_3 = 3,
+#endif
+#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+ /** Compare channel 4. */
+ RTC_COUNT_COMPARE_4 = 4,
+#endif
+#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+ /** Compare channel 5. */
+ RTC_COUNT_COMPARE_5 = 5,
+#endif
+};
+
+#if RTC_COUNT_ASYNC == true
+/**
+ * \brief Callback types
+ *
+ * The available callback types for the RTC count module.
+ */
+enum rtc_count_callback {
+ /** Callback for compare channel 0 */
+ RTC_COUNT_CALLBACK_COMPARE_0 = 0,
+# if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+ /** Callback for compare channel 1 */
+ RTC_COUNT_CALLBACK_COMPARE_1,
+# endif
+# if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+ /** Callback for compare channel 2 */
+ RTC_COUNT_CALLBACK_COMPARE_2,
+# endif
+# if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+ /** Callback for compare channel 3 */
+ RTC_COUNT_CALLBACK_COMPARE_3,
+# endif
+# if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+ /** Callback for compare channel 4 */
+ RTC_COUNT_CALLBACK_COMPARE_4,
+# endif
+# if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+ /** Callback for compare channel 5 */
+ RTC_COUNT_CALLBACK_COMPARE_5,
+# endif
+ /** Callback for overflow */
+ RTC_COUNT_CALLBACK_OVERFLOW,
+# if !defined(__DOXYGEN__)
+ /** Total number of callbacks */
+ _RTC_COUNT_CALLBACK_N
+# endif
+};
+
+# if !defined(__DOXYGEN__)
+typedef void (*rtc_count_callback_t)(void);
+# endif
+#endif
+
+/**
+ * \brief RTC input clock prescaler settings
+ *
+ * The available input clock prescaler values for the RTC count module.
+ */
+enum rtc_count_prescaler {
+ /** RTC input clock frequency is prescaled by a factor of 1. */
+ RTC_COUNT_PRESCALER_DIV_1 = RTC_MODE0_CTRL_PRESCALER_DIV1,
+ /** RTC input clock frequency is prescaled by a factor of 2. */
+ RTC_COUNT_PRESCALER_DIV_2 = RTC_MODE0_CTRL_PRESCALER_DIV2,
+ /** RTC input clock frequency is prescaled by a factor of 4. */
+ RTC_COUNT_PRESCALER_DIV_4 = RTC_MODE0_CTRL_PRESCALER_DIV4,
+ /** RTC input clock frequency is prescaled by a factor of 8. */
+ RTC_COUNT_PRESCALER_DIV_8 = RTC_MODE0_CTRL_PRESCALER_DIV8,
+ /** RTC input clock frequency is prescaled by a factor of 16. */
+ RTC_COUNT_PRESCALER_DIV_16 = RTC_MODE0_CTRL_PRESCALER_DIV16,
+ /** RTC input clock frequency is prescaled by a factor of 32. */
+ RTC_COUNT_PRESCALER_DIV_32 = RTC_MODE0_CTRL_PRESCALER_DIV32,
+ /** RTC input clock frequency is prescaled by a factor of 64. */
+ RTC_COUNT_PRESCALER_DIV_64 = RTC_MODE0_CTRL_PRESCALER_DIV64,
+ /** RTC input clock frequency is prescaled by a factor of 128. */
+ RTC_COUNT_PRESCALER_DIV_128 = RTC_MODE0_CTRL_PRESCALER_DIV128,
+ /** RTC input clock frequency is prescaled by a factor of 256. */
+ RTC_COUNT_PRESCALER_DIV_256 = RTC_MODE0_CTRL_PRESCALER_DIV256,
+ /** RTC input clock frequency is prescaled by a factor of 512. */
+ RTC_COUNT_PRESCALER_DIV_512 = RTC_MODE0_CTRL_PRESCALER_DIV512,
+ /** RTC input clock frequency is prescaled by a factor of 1024. */
+ RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRL_PRESCALER_DIV1024,
+};
+
+/**
+ * \brief RTC Count event enable/disable structure.
+ *
+ * Event flags for the \ref rtc_count_enable_events() and
+ * \ref rtc_count_disable_events().
+ */
+struct rtc_count_events {
+ /** Generate an output event on each overflow of the RTC count. */
+ bool generate_event_on_overflow;
+ /** Generate an output event on a compare channel match against the RTC
+ * count. */
+ bool generate_event_on_compare[RTC_NUM_OF_COMP16];
+ /** Generate an output event periodically at a binary division of the RTC
+ * counter frequency (see
+ * \ref asfdoc_sam0_rtc_count_module_overview_periodic).
+ */
+ bool generate_event_on_periodic[8];
+};
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Device structure.
+ */
+struct rtc_module {
+ /** RTC hardware module */
+ Rtc *hw;
+ /** Operation mode of count. */
+ enum rtc_count_mode mode;
+ /** Set if counter value should be continuously updated. */
+ bool continuously_update;
+# if RTC_COUNT_ASYNC == true
+ /** Pointers to callback functions */
+ volatile rtc_count_callback_t callbacks[_RTC_COUNT_CALLBACK_N];
+ /** Mask for registered callbacks */
+ volatile uint8_t registered_callback;
+ /** Mask for enabled callbacks */
+ volatile uint8_t enabled_callback;
+# endif
+};
+#endif
+
+/**
+ * \brief RTC Count configuration structure
+ *
+ * Configuration structure for the RTC instance. This structure should
+ * be initialized using the \ref rtc_count_get_config_defaults() before any
+ * user configurations are set.
+ */
+struct rtc_count_config {
+ /** Input clock prescaler for the RTC module. */
+ enum rtc_count_prescaler prescaler;
+ /** Select the operation mode of the RTC.*/
+ enum rtc_count_mode mode;
+ /** If true, clears the counter value on compare match. Only available
+ * whilst running in 32-bit mode. */
+ bool clear_on_match;
+ /** Continuously update the counter value so no synchronization is
+ * needed for reading. */
+ bool continuously_update;
+ /** Array of Compare values. Not all Compare values are available in 32-bit
+ * mode. */
+ uint32_t compare_values[RTC_NUM_OF_COMP16];
+};
+
+
+/**
+ * \name Configuration and initialization
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module has completed synchronization
+ * \retval false if the module synchronization is ongoing
+ */
+static inline bool rtc_count_is_syncing(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * \brief Gets the RTC default configurations.
+ *
+ * Initializes the configuration structure to default values. This
+ * function should be called at the start of any RTC initialization.
+ *
+ * The default configuration is as follows:
+ * - Input clock divided by a factor of 1024.
+ * - RTC in 32 bit mode.
+ * - Clear on compare match off.
+ * - Continuously sync count register off.
+ * - No event source on.
+ * - All compare values equal 0.
+ *
+ * \param[out] config Configuration structure to be initialized to default
+ * values.
+ */
+static inline void rtc_count_get_config_defaults(
+ struct rtc_count_config *const config)
+{
+ /* Sanity check argument */
+ Assert(config);
+
+ /* Set default into configuration structure */
+ config->prescaler = RTC_COUNT_PRESCALER_DIV_1024;
+ config->mode = RTC_COUNT_MODE_32BIT;
+ config->clear_on_match = false;
+ config->continuously_update = false;
+ for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+ config->compare_values[i] = 0;
+ }
+}
+
+void rtc_count_reset(struct rtc_module *const module);
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module RTC hardware module
+ */
+static inline void rtc_count_enable(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+ system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Enable RTC module. */
+ rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out] module RTC hardware module
+ */
+static inline void rtc_count_disable(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+ system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+ while (rtc_count_is_syncing(module)) {
+ /* Wait for synchronization */
+ }
+
+ /* Disable RTC module. */
+ rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
+}
+
+#if (RTC_INST_NUM > 1) && !defined(__DOXYGEN__)
+/**
+ * \internal Find the index of given RTC module instance.
+ *
+ * \param[in] RTC module instance pointer.
+ *
+ * \return Index of the given AC module instance.
+ */
+uint8_t _rtc_get_inst_index(
+ Rtc *const hw)
+{
+ /* List of available RTC modules. */
+ static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
+
+ /* Find index for RTC instance. */
+ for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
+ if (hw == rtc_modules[i]) {
+ return i;
+ }
+ }
+
+ /* Invalid data given. */
+ Assert(false);
+ return 0;
+}
+#endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
+
+enum status_code rtc_count_init(
+ struct rtc_module *const module,
+ Rtc *const hw,
+ const struct rtc_count_config *const config);
+
+enum status_code rtc_count_frequency_correction(
+ struct rtc_module *const module,
+ const int8_t value);
+
+/** @} */
+
+/** \name Count and compare value management
+ * @{
+ */
+enum status_code rtc_count_set_count(
+ struct rtc_module *const module,
+ const uint32_t count_value);
+
+uint32_t rtc_count_get_count(struct rtc_module *const module);
+
+enum status_code rtc_count_set_compare(
+ struct rtc_module *const module,
+ const uint32_t comp_value,
+ const enum rtc_count_compare comp_index);
+
+enum status_code rtc_count_get_compare(
+ struct rtc_module *const module,
+ uint32_t *const comp_value,
+ const enum rtc_count_compare comp_index);
+
+enum status_code rtc_count_set_period(
+ struct rtc_module *const module,
+ uint16_t period_value);
+
+enum status_code rtc_count_get_period(
+ struct rtc_module *const module,
+ uint16_t *const period_value);
+
+/** @} */
+
+
+/** \name Status management
+ * @{
+ */
+
+/**
+ * \brief Check if an RTC overflow has occurred.
+ *
+ * Checks the overflow flag in the RTC. The flag is set when there
+ * is an overflow in the clock.
+ *
+ * \param[in,out] module RTC hardware module
+ *
+ * \return Overflow state of the RTC module.
+ *
+ * \retval true If the RTC count value has overflowed
+ * \retval false If the RTC count value has not overflowed
+ */
+
+static inline bool rtc_count_is_overflow(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Return status of flag */
+ return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF);
+}
+
+/**
+ * \brief Clears the RTC overflow flag.
+ *
+ * Clears the RTC module counter overflow flag, so that new overflow conditions
+ * can be detected.
+ *
+ * \param[in,out] module RTC hardware module
+ */
+static inline void rtc_count_clear_overflow(struct rtc_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Clear OVF flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+bool rtc_count_is_compare_match(
+ struct rtc_module *const module,
+ const enum rtc_count_compare comp_index);
+
+enum status_code rtc_count_clear_compare_match(
+ struct rtc_module *const module,
+ const enum rtc_count_compare comp_index);
+
+/** @} */
+
+
+/**
+ * \name Event management
+ * @{
+ */
+
+/**
+ * \brief Enables a RTC event output.
+ *
+ * Enables one or more output events from the RTC module. See
+ * \ref rtc_count_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module RTC hardware module
+ * \param[in] events Struct containing flags of events to enable
+ */
+static inline void rtc_count_enable_events(
+ struct rtc_module *const module,
+ struct rtc_count_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ uint32_t event_mask = 0;
+
+ /* Check if the user has requested an overflow event. */
+ if (events->generate_event_on_overflow) {
+ event_mask |= RTC_MODE0_EVCTRL_OVFEO;
+ }
+
+ /* Check if the user has requested any compare events. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+ if (events->generate_event_on_compare[i]) {
+ event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
+ }
+ }
+
+ /* Check if the user has requested any periodic events. */
+ for (uint8_t i = 0; i < 8; i++) {
+ if (events->generate_event_on_periodic[i]) {
+ event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
+ }
+ }
+
+ /* Enable given event(s). */
+ rtc_module->MODE0.EVCTRL.reg |= event_mask;
+}
+
+/**
+ * \brief Disables a RTC event output.
+ *
+ * Disabled one or more output events from the RTC module. See
+ * \ref rtc_count_events for a list of events this module supports.
+ *
+ * \note Events cannot be altered while the module is enabled.
+ *
+ * \param[in,out] module RTC hardware module
+ * \param[in] events Struct containing flags of events to disable
+ */
+static inline void rtc_count_disable_events(
+ struct rtc_module *const module,
+ struct rtc_count_events *const events)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ uint32_t event_mask = 0;
+
+ /* Check if the user has requested an overflow event. */
+ if (events->generate_event_on_overflow) {
+ event_mask |= RTC_MODE0_EVCTRL_OVFEO;
+ }
+
+ /* Check if the user has requested any compare events. */
+ for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+ if (events->generate_event_on_compare[i]) {
+ event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
+ }
+ }
+
+ /* Check if the user has requested any periodic events. */
+ for (uint8_t i = 0; i < 8; i++) {
+ if (events->generate_event_on_periodic[i]) {
+ event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
+ }
+ }
+
+ /* Disable given event(s). */
+ rtc_module->MODE0.EVCTRL.reg &= ~event_mask;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_rtc_count_extra Extra Information for RTC COUNT Driver
+ *
+ * \section asfdoc_sam0_rtc_count_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</td>
+ * <th>Description</td>
+ * </tr>
+ * <tr>
+ * <td>RTC</td>
+ * <td>Real Time Counter</td>
+ * </tr>
+ * <tr>
+ * <td>PPM</td>
+ * <td>Part Per Million</td>
+ * </tr>
+ * <tr>
+ * <td>RC</td>
+ * <td>Resistor/Capacitor</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_rtc_count_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>
+ * Added support for SAMD21 and added driver instance parameter to all
+ * API function calls, except get_config_defaults.
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Updated initialization function to also enable the digital interface
+ * clock to the module if it is disabled.</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_rtc_count_exqsg Examples for RTC (COUNT) Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_rtc_count_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_rtc_count_basic_use_case
+ * \if RTC_COUNT_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_rtc_count_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_rtc_count_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>05/2014</td>
+ * <td>Added support for SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>03/2014</td>
+ * <td>Added support for SAMR21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Added additional documentation on the event system. Corrected
+ * documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif /* RTC_COUNT_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.c
new file mode 100755
index 0000000000000000000000000000000000000000..8aebe7f89eaf95417f5ede099915c4c26025be8c
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.c
@@ -0,0 +1,317 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "rtc_count_interrupt.h"
+
+extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ * To enable the callback, the \ref rtc_count_enable_callback function
+ * must be used.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] callback Pointer to the function desired for the specified
+ * callback
+ * \param[in] callback_type Callback type to register
+ *
+ * \return Status of registering callback
+ * \retval STATUS_OK Registering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
+ */
+enum status_code rtc_count_register_callback(
+ struct rtc_module *const module,
+ rtc_count_callback_t callback,
+ enum rtc_count_callback callback_type)
+{
+
+ enum status_code status = STATUS_OK;
+
+ /* Overflow callback */
+ if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+ status = STATUS_OK;
+ } else {
+ /* Make sure callback type can be registered */
+ switch (module->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Check sanity for 32-bit mode. */
+ if (callback_type > RTC_NUM_OF_COMP32) {
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ break;
+ case RTC_COUNT_MODE_16BIT:
+ /* Check sanity for 16-bit mode. */
+ if (callback_type > RTC_NUM_OF_COMP16) {
+ status = STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ default:
+ status = STATUS_ERR_INVALID_ARG;
+ }
+ }
+
+ if (status == STATUS_OK) {
+ /* Register callback */
+ module->callbacks[callback_type] = callback;
+ /* Set corresponding bit to set callback as registered */
+ module->registered_callback |= (1 << callback_type);
+ }
+
+ return status;
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] callback_type Specifies the callback type to unregister
+ *
+ * \return Status of unregistering callback
+ * \retval STATUS_OK Unregistering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
+ */
+enum status_code rtc_count_unregister_callback(
+ struct rtc_module *const module,
+ enum rtc_count_callback callback_type)
+{
+ enum status_code status = STATUS_OK;
+
+ /* Overflow callback */
+ if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+ status = STATUS_OK;
+ } else {
+ /* Make sure callback type can be unregistered */
+ switch (module->mode) {
+ case RTC_COUNT_MODE_32BIT:
+ /* Check sanity for 32-bit mode. */
+ if (callback_type > RTC_NUM_OF_COMP32) {
+ status = STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ case RTC_COUNT_MODE_16BIT:
+ /* Check sanity for 16-bit mode. */
+ if (callback_type > RTC_NUM_OF_COMP16) {
+ status = STATUS_ERR_INVALID_ARG;
+ }
+ break;
+ default:
+ status = STATUS_ERR_INVALID_ARG;
+ }
+ }
+ if (status == STATUS_OK) {
+ /* Unregister callback */
+ module->callbacks[callback_type] = NULL;
+
+ /* Clear corresponding bit to set callback as unregistered */
+ module->registered_callback &= ~(1 << callback_type);
+ }
+ return status;
+}
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] callback_type Callback type to enable
+ */
+void rtc_count_enable_callback(
+ struct rtc_module *const module,
+ enum rtc_count_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+ rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
+ } else {
+ rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
+ }
+ /* Mark callback as enabled. */
+ module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out] module Pointer to the software instance struct
+ * \param[in] callback_type Callback type to disable
+ */
+void rtc_count_disable_callback(
+ struct rtc_module *const module,
+ enum rtc_count_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Disable interrupt */
+ if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+ rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
+ } else {
+ rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
+ }
+
+ /* Mark callback as disabled. */
+ module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal Interrupt handler for RTC
+ *
+ * \param [in] instance_index Default value 0
+ */
+static void _rtc_interrupt_handler(const uint32_t instance_index)
+{
+ struct rtc_module *module = _rtc_instance[instance_index];
+
+ Rtc *const rtc_module = module->hw;
+
+ /* Combine callback registered and enabled masks */
+ uint8_t callback_mask = module->enabled_callback;
+ callback_mask &= module->registered_callback;
+
+ /* Read and mask interrupt flag register */
+ uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
+ interrupt_status &= rtc_module->MODE0.INTENSET.reg;
+
+ if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
+ /* Overflow interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
+ module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
+ }
+
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+
+ } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
+ /* Compare 0 interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
+ module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
+ }
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
+
+ } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
+ #if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+ /* Compare 1 interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
+ module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
+ }
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
+ #endif
+
+ } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
+ #if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+ /* Compare 2 interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
+ module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
+ }
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
+ #endif
+
+ } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
+ #if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+ /* Compare 3 interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
+ module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
+ }
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
+ #endif
+
+ } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
+ #if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+ /* Compare 4 interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
+ module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
+ }
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
+ #endif
+
+ } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
+ #if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+ /* Compare 5 interrupt */
+ if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
+ module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
+ }
+ /* Clear interrupt flag */
+ rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
+ #endif
+ }
+}
+
+/**
+ * \internal ISR handler for RTC
+ */
+#if (RTC_INST_NUM == 1)
+void RTC_Handler(void)
+{
+ _rtc_interrupt_handler(0);
+}
+#elif (RTC_INST_NUM > 1)
+# define _RTC_INTERRUPT_HANDLER(n, unused) \
+ void RTC##n##_Handler(void) \
+ { \
+ _rtc_interrupt_handler(n); \
+ }
+
+MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
+#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.h
new file mode 100755
index 0000000000000000000000000000000000000000..f75c109c16fe214e83a069330bbca7bffcba149f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef RTC_COUNT_INTERRUPT_H_INCLUDED
+#define RTC_COUNT_INTERRUPT_H_INCLUDED
+
+#include "rtc_count.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_rtc_count_group
+ * @{
+ */
+
+ /**
+ * \name Callbacks
+ * @{
+ */
+enum status_code rtc_count_register_callback(
+ struct rtc_module *const module,
+ rtc_count_callback_t callback,
+ enum rtc_count_callback callback_type);
+
+enum status_code rtc_count_unregister_callback(
+ struct rtc_module *const module,
+ enum rtc_count_callback callback_type);
+
+void rtc_count_enable_callback(
+ struct rtc_module *const module,
+ enum rtc_count_callback callback_type);
+
+void rtc_count_disable_callback(
+ struct rtc_module *const module,
+ enum rtc_count_callback callback_type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTC_COUNT_INTERRUPT_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom.c
new file mode 100755
index 0000000000000000000000000000000000000000..0d1b022f95172486bf9ebb56a380faed7eee16b7
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom.c
@@ -0,0 +1,267 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "sercom.h"
+
+#define SHIFT 32
+#define BAUD_INT_MAX 8192
+#define BAUD_FP_MAX 8
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Configuration structure to save current gclk status.
+ */
+struct _sercom_conf {
+ /* Status of gclk generator initialization. */
+ bool generator_is_set;
+ /* Sercom gclk generator used. */
+ enum gclk_generator generator_source;
+};
+
+static struct _sercom_conf _sercom_config;
+
+
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+ int32_t i;
+ uint64_t q = 0, r = 0, bit_shift;
+ for (i = 63; i >= 0; i--) {
+ bit_shift = (uint64_t)1 << i;
+
+ r = r << 1;
+
+ if (n & bit_shift) {
+ r |= 0x01;
+ }
+
+ if (r >= d) {
+ r = r - d;
+ q |= bit_shift;
+ }
+ }
+
+ return q;
+}
+
+/**
+ * \internal Calculate synchronous baudrate value (SPI/UART)
+ */
+enum status_code _sercom_get_sync_baud_val(
+ const uint32_t baudrate,
+ const uint32_t external_clock,
+ uint16_t *const baudvalue)
+{
+ /* Baud value variable */
+ uint16_t baud_calculated = 0;
+ uint32_t clock_value = external_clock;
+
+
+ /* Check if baudrate is outside of valid range. */
+ if (baudrate > (external_clock / 2)) {
+ /* Return with error code */
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+
+ /* Calculate BAUD value from clock frequency and baudrate */
+ clock_value = external_clock / 2;
+ while (clock_value >= baudrate) {
+ clock_value = clock_value - baudrate;
+ baud_calculated++;
+ }
+ baud_calculated = baud_calculated - 1;
+
+ /* Check if BAUD value is more than 255, which is maximum
+ * for synchronous mode */
+ if (baud_calculated > 0xFF) {
+ /* Return with an error code */
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ } else {
+ *baudvalue = baud_calculated;
+ return STATUS_OK;
+ }
+}
+
+/**
+ * \internal Calculate asynchronous baudrate value (UART)
+*/
+enum status_code _sercom_get_async_baud_val(
+ const uint32_t baudrate,
+ const uint32_t peripheral_clock,
+ uint16_t *const baudval,
+ enum sercom_asynchronous_operation_mode mode,
+ enum sercom_asynchronous_sample_num sample_num)
+{
+ /* Temporary variables */
+ uint64_t ratio = 0;
+ uint64_t scale = 0;
+ uint64_t baud_calculated = 0;
+ uint8_t baud_fp;
+ uint32_t baud_int = 0;
+ uint64_t temp1, temp2;
+
+ /* Check if the baudrate is outside of valid range */
+ if ((baudrate * sample_num) > peripheral_clock) {
+ /* Return with error code */
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+
+ if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+ /* Calculate the BAUD value */
+ temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+ ratio = long_division(temp1, peripheral_clock);
+ scale = ((uint64_t)1 << SHIFT) - ratio;
+ baud_calculated = (65536 * scale) >> SHIFT;
+ } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+ for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) {
+ temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock;
+ temp2 = ((uint64_t)baudrate * sample_num);
+ baud_int = long_division(temp1, temp2);
+ baud_int -= baud_fp;
+ baud_int = baud_int / BAUD_FP_MAX;
+ if(baud_int < BAUD_INT_MAX) {
+ break;
+ }
+ }
+ if(baud_fp == BAUD_FP_MAX) {
+ return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+ }
+ baud_calculated = baud_int | (baud_fp << 13);
+ }
+
+ *baudval = baud_calculated;
+ return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Set GCLK channel to generator.
+ *
+ * This will set the appropriate GCLK channel to the requested GCLK generator.
+ * This will set the generator for all SERCOM instances, and the user will thus
+ * only be able to set the same generator that has previously been set, if any.
+ *
+ * After the generator has been set the first time, the generator can be changed
+ * using the \c force_change flag.
+ *
+ * \param[in] generator_source The generator to use for SERCOM.
+ * \param[in] force_change Force change the generator.
+ *
+ * \return Status code indicating the GCLK generator change operation.
+ * \retval STATUS_OK If the generator update request was
+ * successful.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured
+ * and the new configuration was not
+ * forced.
+ */
+enum status_code sercom_set_gclk_generator(
+ const enum gclk_generator generator_source,
+ const bool force_change)
+{
+ /* Check if valid option. */
+ if (!_sercom_config.generator_is_set || force_change) {
+ /* Create and fill a GCLK configuration structure for the new config. */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = generator_source;
+ system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+ system_gclk_chan_enable(SERCOM_GCLK_ID);
+
+ /* Save config. */
+ _sercom_config.generator_source = generator_source;
+ _sercom_config.generator_is_set = true;
+
+ return STATUS_OK;
+ } else if (generator_source == _sercom_config.generator_source) {
+ /* Return status OK if same config. */
+ return STATUS_OK;
+ }
+
+ /* Return invalid config to already initialized GCLK. */
+ return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/** \internal
+ * Creates a switch statement case entry to convert a SERCOM instance and pad
+ * index to the default SERCOM pad MUX setting.
+ */
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
+ case (uintptr_t)SERCOM##n: \
+ switch (pad) { \
+ case 0: \
+ return SERCOM##n##_PAD0_DEFAULT; \
+ case 1: \
+ return SERCOM##n##_PAD1_DEFAULT; \
+ case 2: \
+ return SERCOM##n##_PAD2_DEFAULT; \
+ case 3: \
+ return SERCOM##n##_PAD3_DEFAULT; \
+ } \
+ break;
+
+/**
+ * \internal Gets the default PAD pinout for a given SERCOM.
+ *
+ * Returns the PINMUX settings for the given SERCOM and pad. This is used
+ * for default configuration of pins.
+ *
+ * \param[in] sercom_module Pointer to the SERCOM module
+ * \param[in] pad PAD to get default pinout for
+ *
+ * \returns The default PINMUX for the given SERCOM instance and PAD
+ *
+ */
+uint32_t _sercom_get_default_pad(
+ Sercom *const sercom_module,
+ const uint8_t pad)
+{
+ switch ((uintptr_t)sercom_module) {
+ /* Auto-generate a lookup table for the default SERCOM pad defaults */
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+ }
+
+ Assert(false);
+ return 0;
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom.h
new file mode 100755
index 0000000000000000000000000000000000000000..0d15665f6c68b3f2966dee98e3bedfe37b004f9d
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SERCOM_H_INCLUDED
+#define SERCOM_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <clock.h>
+#include "sercom_interrupt.h"
+#include "sercom_pinout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (SAMD10) || (SAMD11)
+
+#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \
+ SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW)
+# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+#else
+# error "SERCOM modules must share the same slow GCLK channel ID."
+#endif
+
+#else
+
+#if (SERCOM0_GCLK_ID_SLOW == SERCOM1_GCLK_ID_SLOW && \
+ SERCOM0_GCLK_ID_SLOW == SERCOM2_GCLK_ID_SLOW && \
+ SERCOM0_GCLK_ID_SLOW == SERCOM3_GCLK_ID_SLOW)
+# define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+#else
+# error "SERCOM modules must share the same slow GCLK channel ID."
+#endif
+
+#endif
+
+#if (0x1ff >= REV_SERCOM)
+# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
+#elif (0x2ff >= REV_SERCOM)
+# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
+#else
+# error "Unknown SYNCBUSY scheme for this SERCOM revision"
+#endif
+
+/**
+ * \brief sercom asynchronous operation mode
+ *
+ * Select sercom asynchronous operation mode
+ */
+enum sercom_asynchronous_operation_mode {
+ SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+ SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+};
+
+/**
+ * \brief sercom asynchronous samples per bit
+ *
+ * Select number of samples per bit
+ */
+enum sercom_asynchronous_sample_num {
+ SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+ SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+ SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+};
+
+enum status_code sercom_set_gclk_generator(
+ const enum gclk_generator generator_source,
+ const bool force_change);
+
+enum status_code _sercom_get_sync_baud_val(
+ const uint32_t baudrate,
+ const uint32_t external_clock,
+ uint16_t *const baudval);
+
+enum status_code _sercom_get_async_baud_val(
+ const uint32_t baudrate,
+ const uint32_t peripheral_clock,
+ uint16_t *const baudval,
+ enum sercom_asynchronous_operation_mode mode,
+ enum sercom_asynchronous_sample_num sample_num);
+
+uint32_t _sercom_get_default_pad(
+ Sercom *const sercom_module,
+ const uint8_t pad);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SERCOM_H_INCLUDED
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_interrupt.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_interrupt.c
new file mode 100755
index 0000000000000000000000000000000000000000..05da2582f7d142dcb9e54828570a1ae1e3e62565
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_interrupt.c
@@ -0,0 +1,164 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "sercom_interrupt.h"
+
+void *_sercom_instances[SERCOM_INST_NUM];
+
+/** Save status of initialized handlers. */
+static bool _handler_table_initialized = false;
+
+/** Void pointers for saving device instance structures. */
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
+
+/**
+ * \internal
+ * Default interrupt handler.
+ *
+ * \param[in] instance SERCOM instance used.
+ */
+static void _sercom_default_handler(
+ const uint8_t instance)
+{
+ Assert(false);
+}
+
+/**
+ * \internal
+ * Find index of given instance.
+ *
+ * \param[in] sercom_instance Instance pointer.
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+ Sercom *const sercom_instance)
+{
+ /* Save all available SERCOM instances for compare. */
+ Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+ /* Find index for sercom instance. */
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+ if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+ return i;
+ }
+ }
+
+ /* Invalid data given. */
+ Assert(false);
+ return 0;
+}
+
+/**
+ * \internal
+ * Saves the given callback handler.
+ *
+ * \param[in] instance Instance index.
+ * \param[in] interrupt_handler Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+ const uint8_t instance,
+ const sercom_handler_t interrupt_handler)
+{
+ /* Initialize handlers with default handler and device instances with 0. */
+ if (_handler_table_initialized == false) {
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+ _sercom_interrupt_handlers[i] = &_sercom_default_handler;
+ _sercom_instances[i] = NULL;
+ }
+
+ _handler_table_initialized = true;
+ }
+
+ /* Save interrupt handler. */
+ _sercom_interrupt_handlers[instance] = interrupt_handler;
+}
+
+
+/** \internal
+ * Converts a given SERCOM index to its interrupt vector index.
+ */
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
+ SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
+ void SERCOM##n##_Handler(void) \
+ { \
+ _sercom_interrupt_handlers[n](n); \
+ }
+
+/**
+ * \internal
+ * Returns the system interrupt vector.
+ *
+ * \param[in] sercom_instance Instance pointer
+ *
+ * \return Enum of system interrupt vector
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+ Sercom *const sercom_instance)
+{
+ const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+ {
+ MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+ };
+
+ /* Retrieve the index of the SERCOM being requested */
+ uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+
+ /* Get the vector number from the lookup table for the requested SERCOM */
+ return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+}
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_interrupt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_interrupt.h
new file mode 100755
index 0000000000000000000000000000000000000000..b9ae9982af17b2a912b7f1d59f9523f9f3417eb7
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_interrupt.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SERCOM_INTERRUPT_H_INCLUDED
+#define SERCOM_INTERRUPT_H_INCLUDED
+
+#include "sercom.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Look-up table for device instances. */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+typedef void (*sercom_handler_t)(uint8_t instance);
+
+uint8_t _sercom_get_sercom_inst_index(
+ Sercom *const sercom_instance);
+
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+ Sercom *const sercom_instance);
+
+void _sercom_set_handler(
+ const uint8_t instance,
+ const sercom_handler_t interrupt_handler);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_pinout.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_pinout.h
new file mode 100755
index 0000000000000000000000000000000000000000..61d265b64b7ea455929e68f04bd5a0ac874cca36
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/sercom_pinout.h
@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM Module Pinout Definitions
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SERCOM_PINOUT_H_INCLUDED
+#define SERCOM_PINOUT_H_INCLUDED
+
+#include "sercom.h"
+
+#if (SAMD10) || (SAMD11)
+/* SERCOM0 */
+#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
+#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
+#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
+#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
+
+/* SERCOM1 */
+#define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0
+#define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1
+#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
+#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
+
+/* SERCOM2 */
+#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0
+#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1
+#define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2
+#define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3
+#else
+/* SERCOM0 */
+#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0
+#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1
+#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2
+#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3
+
+/* SERCOM1 */
+#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0
+#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1
+#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2
+#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3
+
+/* SERCOM2 */
+#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0
+#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1
+#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2
+#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3
+
+/* SERCOM3 */
+#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0
+#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1
+#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2
+#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3
+
+/* SERCOM4 */
+#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0
+#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1
+#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2
+#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3
+
+/* SERCOM5 */
+#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0
+#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1
+#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2
+#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3
+#endif
+
+#endif /* SERCOM_PINOUT_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h
new file mode 100755
index 0000000000000000000000000000000000000000..9627a3e5cd742fd0e8b3e5298f80187f2d20d283
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
+ *
+ * This quick start will echo back characters typed into the terminal. In this
+ * use case the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and 1 Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_basic_use.c module_inst
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_basic_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_basic_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ * the USART driver state while it is in use.
+ * \snippet qs_usart_basic_use.c module_inst
+ * \note This should never go out of scope as long as the module is in use.
+ * In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ * -# Create a USART module configuration struct, which can be filled out to
+ * adjust the configuration of a physical USART peripheral.
+ * \snippet qs_usart_basic_use.c setup_config
+ * -# Initialize the USART configuration struct with the module's default values.
+ * \snippet qs_usart_basic_use.c setup_config_defaults
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Alter the USART settings to configure the physical pinout, baud rate and
+ * other relevant parameters.
+ * \snippet qs_usart_basic_use.c setup_change_config
+ * -# Configure the USART module with the desired settings, retrying while the
+ * driver is busy until the configuration is stressfully set.
+ * \snippet qs_usart_basic_use.c setup_set_config
+ * -# Enable the USART module.
+ * \snippet qs_usart_basic_use.c setup_enable
+ *
+ *
+ * \section asfdoc_sam0_usart_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_basic_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
+ * -# Send a string to the USART to show the demo is running, blocking until
+ * all characters have been sent.
+ * \snippet qs_usart_basic_use.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ * \snippet qs_usart_basic_use.c main_loop
+ * -# Perform a blocking read of the USART, storing the received character into
+ * the previously declared temporary variable.
+ * \snippet qs_usart_basic_use.c main_read
+ * -# Echo the received variable back to the USART via a blocking write.
+ * \snippet qs_usart_basic_use.c main_write
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h
new file mode 100755
index 0000000000000000000000000000000000000000..eeffcd4e6f61580dfb32a1cd793ba07db43839eb
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h
@@ -0,0 +1,210 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/D10/D11 Quick Start Guide for Using Usart driver with DMA
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
+ *
+ * The supported board list:
+ * - SAMD21 Xplained Pro
+ * - SAMR21 Xplained Pro
+ * - SAMR11 Xplained Pro
+ *
+ * This quick start will receiving 8 bytes of data from PC terminal and transmit back the string
+ * to the terminal through DMA. In this use case the USART will be configured with the following
+ * settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and 1 Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_dma_use.c module_inst
+ * \snippet qs_usart_dma_use.c dma_resource
+ * \snippet qs_usart_dma_use.c usart_buffer
+ * \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_dma_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_dma_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
+ * -# Create a module software instance structure for the USART module to store
+ * the USART driver state while it is in use.
+ * \snippet qs_usart_dma_use.c module_inst
+ * \note This should never go out of scope as long as the module is in use.
+ * In most cases, this should be global.
+ *
+ * -# Create module software instance structures for DMA resources to store
+ * the DMA resource state while it is in use.
+ * \snippet qs_usart_dma_use.c dma_resource
+ * \note This should never go out of scope as long as the module is in use.
+ * In most cases, this should be global.
+ *
+ * -# Create a buffer to store the data to be transferred /received
+ * \snippet qs_usart_dma_use.c usart_buffer
+ * -# Create DMA transfer descriptors for RX/TX
+ * \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
+ * -# Create a USART module configuration struct, which can be filled out to
+ * adjust the configuration of a physical USART peripheral.
+ * \snippet qs_usart_dma_use.c setup_config
+ * -# Initialize the USART configuration struct with the module's default values.
+ * \snippet qs_usart_dma_use.c setup_config_defaults
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Alter the USART settings to configure the physical pinout, baud rate and
+ * other relevant parameters.
+ * \snippet qs_usart_dma_use.c setup_change_config
+ * -# Configure the USART module with the desired settings, retrying while the
+ * driver is busy until the configuration is stressfully set.
+ * \snippet qs_usart_dma_use.c setup_set_config
+ * -# Enable the USART module.
+ * \snippet qs_usart_dma_use.c setup_enable
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
+ * -# Create a callback function of receiver done
+ * \snippet qs_usart_dma_use.c transfer_done_rx
+ *
+ * -# Create a callback function of transmission done
+ * \snippet qs_usart_dma_use.c transfer_done_tx
+ *
+ * -# Create a DMA resource configuration structure, which can be filled out to
+ * adjust the configuration of a single DMA transfer.
+ * \snippet qs_usart_dma_use.c setup_rx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ * default values.
+ * \snippet qs_usart_dma_use.c setup_rx_2
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ * trigger, SERCOM Tx empty trigger and trigger causes a beat transfer in
+ * this example.
+ * \snippet qs_usart_dma_use.c setup_rx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ * \snippet qs_usart_dma_use.c setup_rx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ * filled out to adjust the configuration of a single DMA transfer.
+ * \snippet qs_usart_dma_use.c setup_rx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ * default values.
+ * \snippet qs_usart_dma_use.c setup_rx_6
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ * address, destination address.
+ * \snippet qs_usart_dma_use.c setup_rx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ * \snippet qs_usart_dma_use.c setup_rx_8
+ *
+ * -# Create a DMA resource configuration structure for tx, which can be filled
+ * out to adjust the configuration of a single DMA transfer.
+ * \snippet qs_usart_dma_use.c setup_tx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ * default values.
+ * \snippet qs_usart_dma_use.c setup_tx_2
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ * trigger, SERCOM Rx Ready trigger and trigger causes a beat transfer in
+ * this example.
+ * \snippet qs_usart_dma_use.c setup_tx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ * \snippet qs_usart_dma_use.c setup_tx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ * filled out to adjust the configuration of a single DMA transfer.
+ * \snippet qs_usart_dma_use.c setup_tx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ * default values.
+ * \snippet qs_usart_dma_use.c setup_tx_6
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ * address, destination address.
+ * \snippet qs_usart_dma_use.c setup_tx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ * \snippet qs_usart_dma_use.c setup_tx_8
+ *
+ * \section asfdoc_sam0_usart_dma_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_dma_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
+ * -# Wait for receiving data.
+ * \snippet qs_usart_dma_use.c main_1
+ *
+ * -# enter endless loop
+ * \snippet qs_usart_dma_use.c endless_loop
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/usart.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/usart.c
new file mode 100755
index 0000000000000000000000000000000000000000..f93ae24511ff2545dc41dae9470243633562dafb
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/usart.c
@@ -0,0 +1,697 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "usart.h"
+#include <pinmux.h>
+#if USART_CALLBACK_MODE == true
+# include "usart_interrupt.h"
+#endif
+
+/**
+ * \internal
+ * Set Configuration of the USART module
+ */
+static enum status_code _usart_set_config(
+ struct usart_module *const module,
+ const struct usart_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Index for generic clock */
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ /* Cache new register values to minimize the number of register writes */
+ uint32_t ctrla = 0;
+ uint32_t ctrlb = 0;
+ uint16_t baud = 0;
+
+ enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+ switch (config->sample_rate) {
+ case USART_SAMPLE_RATE_16X_ARITHMETIC:
+ mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+ break;
+ case USART_SAMPLE_RATE_8X_ARITHMETIC:
+ mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+ break;
+ case USART_SAMPLE_RATE_3X_ARITHMETIC:
+ mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+ break;
+ case USART_SAMPLE_RATE_16X_FRACTIONAL:
+ mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+ break;
+ case USART_SAMPLE_RATE_8X_FRACTIONAL:
+ mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+ sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+ break;
+ }
+#endif
+
+ /* Set data order, internal muxing, and clock polarity */
+ ctrla = (uint32_t)config->data_order |
+ (uint32_t)config->mux_setting |
+ #ifdef FEATURE_USART_OVER_SAMPLE
+ config->sample_adjustment |
+ config->sample_rate |
+ #endif
+ #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+ (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+ #endif
+ (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+ enum status_code status_code = STATUS_OK;
+
+ /* Get baud value from mode and clock */
+ switch (config->transfer_mode)
+ {
+ case USART_TRANSFER_SYNCHRONOUSLY:
+ if (!config->use_external_clock) {
+ status_code = _sercom_get_sync_baud_val(config->baudrate,
+ system_gclk_chan_get_hz(gclk_index), &baud);
+ }
+
+ break;
+
+ case USART_TRANSFER_ASYNCHRONOUSLY:
+ if (config->use_external_clock) {
+ status_code =
+ _sercom_get_async_baud_val(config->baudrate,
+ config->ext_clock_freq, &baud, mode, sample_num);
+ } else {
+ status_code =
+ _sercom_get_async_baud_val(config->baudrate,
+ system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+ }
+
+ break;
+ }
+
+ /* Check if calculating the baud rate failed */
+ if (status_code != STATUS_OK) {
+ /* Abort */
+ return status_code;
+ }
+
+#ifdef FEATURE_USART_IRDA
+ if(config->encoding_format_enable) {
+ usart_hw->RXPL.reg = config->receive_pulse_length;
+ }
+#endif
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /*Set baud val */
+ usart_hw->BAUD.reg = baud;
+
+ /* Set sample mode */
+ ctrla |= config->transfer_mode;
+
+ if (config->use_external_clock == false) {
+ ctrla |= SERCOM_USART_CTRLA_MODE_USART_INT_CLK;
+ }
+ else {
+ ctrla |= SERCOM_USART_CTRLA_MODE_USART_EXT_CLK;
+ }
+
+ /* Set stopbits, character size and enable transceivers */
+ ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size |
+ #ifdef FEATURE_USART_IRDA
+ (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+ #endif
+ #ifdef FEATURE_USART_START_FRAME_DECTION
+ (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+ #endif
+ #ifdef FEATURE_USART_COLLISION_DECTION
+ (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+ #endif
+ (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+ (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+
+ /* Check parity mode bits */
+ if (config->parity != USART_PARITY_NONE) {
+#ifdef FEATURE_USART_LIN_SLAVE
+ if(config->lin_slave_enable) {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0x5);
+ }
+#else
+ ctrla |= SERCOM_USART_CTRLA_FORM(1);
+#endif
+ ctrlb |= config->parity;
+ } else {
+#ifdef FEATURE_USART_LIN_SLAVE
+ if(config->lin_slave_enable) {
+ ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+ }
+#else
+ ctrla |= SERCOM_USART_CTRLA_FORM(0);
+#endif
+ }
+
+ /* Set whether module should run in standby. */
+ if (config->run_in_standby || system_is_debugger_present()) {
+ ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+ }
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Write configuration to CTRLB */
+ usart_hw->CTRLB.reg = ctrlb;
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Write configuration to CTRLA */
+ usart_hw->CTRLA.reg = ctrla;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the USART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[out] module Pointer to USART device
+ * \param[in] hw Pointer to USART hardware instance
+ * \param[in] config Pointer to configuration struct
+ *
+ * \return Status of the initialization
+ *
+ * \retval STATUS_OK The initialization was successful
+ * \retval STATUS_BUSY The USART module is busy
+ * resetting
+ * \retval STATUS_ERR_DENIED The USART have not been disabled in
+ * advance of initialization
+ * \retval STATUS_ERR_INVALID_ARG The configuration struct contains
+ * invalid configuration
+ * \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been
+ * initialized with different clock
+ * configuration
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the
+ * configuration
+ * struct cannot be reached with
+ * the current clock configuration
+ */
+enum status_code usart_init(
+ struct usart_module *const module,
+ Sercom *const hw,
+ const struct usart_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(hw);
+ Assert(config);
+
+ enum status_code status_code = STATUS_OK;
+
+ /* Assign module pointer to software instance struct */
+ module->hw = hw;
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+ uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+ uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+ if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+ /* The module is busy resetting itself */
+ return STATUS_BUSY;
+ }
+
+ if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+ /* Check the module is enabled */
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Turn on module in PM */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+ /* Set up the GCLK for the module */
+ struct system_gclk_chan_config gclk_chan_conf;
+ system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+ gclk_chan_conf.source_generator = config->generator_source;
+ system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+ system_gclk_chan_enable(gclk_index);
+ sercom_set_gclk_generator(config->generator_source, false);
+
+ /* Set character size */
+ module->character_size = config->character_size;
+
+ /* Set transmitter and receiver status */
+ module->receiver_enabled = config->receiver_enable;
+ module->transmitter_enabled = config->transmitter_enable;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+ module->lin_slave_enabled = config->lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ module->start_frame_detection_enabled = config->start_frame_detection_enable;
+#endif
+ /* Set configuration according to the config struct */
+ status_code = _usart_set_config(module, config);
+ if(status_code != STATUS_OK) {
+ return status_code;
+ }
+
+ struct system_pinmux_config pin_conf;
+ system_pinmux_get_config_defaults(&pin_conf);
+ pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+ uint32_t pad_pinmuxes[] = {
+ config->pinmux_pad0, config->pinmux_pad1,
+ config->pinmux_pad2, config->pinmux_pad3
+ };
+
+ /* Configure the SERCOM pins according to the user configuration */
+ for (uint8_t pad = 0; pad < 4; pad++) {
+ uint32_t current_pinmux = pad_pinmuxes[pad];
+
+ if (current_pinmux == PINMUX_DEFAULT) {
+ current_pinmux = _sercom_get_default_pad(hw, pad);
+ }
+
+ if (current_pinmux != PINMUX_UNUSED) {
+ pin_conf.mux_position = current_pinmux & 0xFFFF;
+ system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+ }
+ }
+
+#if USART_CALLBACK_MODE == true
+ /* Initialize parameters */
+ for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
+ module->callback[i] = NULL;
+ }
+
+ module->tx_buffer_ptr = NULL;
+ module->rx_buffer_ptr = NULL;
+ module->remaining_tx_buffer_length = 0x0000;
+ module->remaining_rx_buffer_length = 0x0000;
+ module->callback_reg_mask = 0x00;
+ module->callback_enable_mask = 0x00;
+ module->rx_status = STATUS_OK;
+ module->tx_status = STATUS_OK;
+
+ /* Set interrupt handler and register USART software module struct in
+ * look-up table */
+ uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+ _sercom_set_handler(instance_index, _usart_interrupt_handler);
+ _sercom_instances[instance_index] = module;
+#endif
+
+ return status_code;
+}
+
+/**
+ * \brief Transmit a character via the USART
+ *
+ * This blocking function will transmit a single character via the
+ * USART.
+ *
+ * \param[in] module Pointer to the software instance struct
+ * \param[in] tx_data Data to transfer
+ *
+ * \return Status of the operation
+ * \retval STATUS_OK If the operation was completed
+ * \retval STATUS_BUSY If the operation was not completed, due to the USART
+ * module being busy.
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_wait(
+ struct usart_module *const module,
+ const uint16_t tx_data)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Check that the transmitter is enabled */
+ if (!(module->transmitter_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+#if USART_CALLBACK_MODE == true
+ /* Check if the USART is busy doing asynchronous operation. */
+ if (module->remaining_tx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+
+#else
+ /* Check if USART is ready for new data */
+ if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+ /* Return error code */
+ return STATUS_BUSY;
+ }
+#endif
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Write data to USART module */
+ usart_hw->DATA.reg = tx_data;
+
+ while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+ /* Wait until data is sent */
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Receive a character via the USART
+ *
+ * This blocking function will receive a character via the USART.
+ *
+ * \param[in] module Pointer to the software instance struct
+ * \param[out] rx_data Pointer to received data
+ *
+ * \return Status of the operation
+ * \retval STATUS_OK If the operation was completed
+ * \retval STATUS_BUSY If the operation was not completed,
+ * due to the USART module being busy
+ * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
+ * due to configuration mismatch between USART
+ * and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
+ * due to the baud rate being too low or the
+ * system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to
+ * data being corrupted
+ * \retval STATUS_ERR_DENIED If the receiver is not enabled
+ */
+enum status_code usart_read_wait(
+ struct usart_module *const module,
+ uint16_t *const rx_data)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Error variable */
+ uint8_t error_code;
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Check that the receiver is enabled */
+ if (!(module->receiver_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+#if USART_CALLBACK_MODE == true
+ /* Check if the USART is busy doing asynchronous operation. */
+ if (module->remaining_rx_buffer_length > 0) {
+ return STATUS_BUSY;
+ }
+#endif
+
+ /* Check if USART has new data */
+ if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+ /* Return error code */
+ return STATUS_BUSY;
+ }
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Read out the status code and mask away all but the 3 LSBs*/
+ error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+ /* Check if an error has occurred during the receiving */
+ if (error_code) {
+ /* Check which error occurred */
+ if (error_code & SERCOM_USART_STATUS_FERR) {
+ /* Clear flag by writing a 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+ return STATUS_ERR_BAD_FORMAT;
+ } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+ /* Clear flag by writing a 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+ return STATUS_ERR_OVERFLOW;
+ } else if (error_code & SERCOM_USART_STATUS_PERR) {
+ /* Clear flag by writing a 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+ return STATUS_ERR_BAD_DATA;
+ }
+#ifdef FEATURE_USART_LIN_SLAVE
+ else if (error_code & SERCOM_USART_STATUS_ISF) {
+ /* Clear flag by writing 1 to it and
+ * return with an error code */
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF;
+
+ return STATUS_ERR_PROTOCOL;
+ }
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ else if (error_code & SERCOM_USART_STATUS_COLL) {
+ /* Clear flag by writing 1 to it
+ * return with an error code */
+ usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL;
+
+ return STATUS_ERR_PACKET_COLLISION;
+ }
+#endif
+ }
+
+ /* Read data from USART module */
+ *rx_data = usart_hw->DATA.reg;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Transmit a buffer of characters via the USART
+ *
+ * This blocking function will transmit a block of \c length characters
+ * via the USART
+ *
+ * \note Using this function in combination with the interrupt (\c _job) functions is
+ * not recommended as it has no functionality to check if there is an
+ * ongoing interrupt driven operation running or not.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] tx_data Pointer to data to transmit
+ * \param[in] length Number of characters to transmit
+ *
+ * \return Status of the operation
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ * arguments
+ * \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART
+ * module timing out
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_wait(
+ struct usart_module *const module,
+ const uint8_t *tx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Check if the buffer length is valid */
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check that the transmitter is enabled */
+ if (!(module->transmitter_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ uint16_t tx_pos = 0;
+
+ /* Blocks while buffer is being transferred */
+ while (length--) {
+ /* Wait for the USART to be ready for new data and abort
+ * operation if it doesn't get ready within the timeout*/
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
+ break;
+ } else if (i == USART_TIMEOUT) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+
+ /* Data to send is at least 8 bits long */
+ uint16_t data_to_send = tx_data[tx_pos++];
+
+ /* Check if the character size exceeds 8 bit */
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+ data_to_send |= (tx_data[tx_pos++] << 8);
+ }
+
+ /* Send the data through the USART module */
+ usart_write_wait(module, data_to_send);
+ }
+
+ /* Wait until Transmit is complete or timeout */
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
+ break;
+ } else if (i == USART_TIMEOUT) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the USART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ * functions is not recommended as it has no functionality to check if
+ * there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[out] rx_data Pointer to receive buffer
+ * \param[in] length Number of characters to receive
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an
+ * invalid argument being supplied
+ * \retval STATUS_ERR_TIMEOUT If operation was not completed, due
+ * to USART module timing out
+ * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed,
+ * due to a configuration mismatch
+ * between USART and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed,
+ * due to the baud rate being too low or the
+ * system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due
+ * to data being corrupted
+ * \retval STATUS_ERR_DENIED If the receiver is not enabled
+ */
+enum status_code usart_read_buffer_wait(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Check if the buffer length is valid */
+ if (length == 0) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ /* Check that the receiver is enabled */
+ if (!(module->receiver_enabled)) {
+ return STATUS_ERR_DENIED;
+ }
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ uint16_t rx_pos = 0;
+
+ /* Blocks while buffer is being received */
+ while (length--) {
+ /* Wait for the USART to have new data and abort operation if it
+ * doesn't get ready within the timeout*/
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
+ break;
+ } else if (i == USART_TIMEOUT) {
+ return STATUS_ERR_TIMEOUT;
+ }
+ }
+
+ enum status_code retval;
+ uint16_t received_data = 0;
+
+ retval = usart_read_wait(module, &received_data);
+
+ if (retval != STATUS_OK) {
+ /* Overflow, abort */
+ return retval;
+ }
+
+ /* Read value will be at least 8-bits long */
+ rx_data[rx_pos++] = received_data;
+
+ /* If 9-bit data, write next received byte to the buffer */
+ if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+ rx_data[rx_pos++] = (received_data >> 8);
+ }
+ }
+
+ return STATUS_OK;
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/usart.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/usart.h
new file mode 100755
index 0000000000000000000000000000000000000000..e61af7a3382cd8c4982eae5a36f836c1357fc85b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/sercom/usart/usart.h
@@ -0,0 +1,1257 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef USART_H_INCLUDED
+#define USART_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART Driver (SERCOM USART)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of the SERCOM module in its USART mode to transfer or receive
+ * USART data frames. The following driver API modes are covered by this
+ * manual:
+ *
+ * - Polled APIs
+ * \if USART_CALLBACK_MODE
+ * - Callback APIs
+ * \endif
+ *
+ * The following peripherals are used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_usart_prerequisites
+ * - \ref asfdoc_sam0_sercom_usart_overview
+ * - \ref asfdoc_sam0_sercom_usart_special_considerations
+ * - \ref asfdoc_sam0_sercom_usart_extra_info
+ * - \ref asfdoc_sam0_sercom_usart_examples
+ * - \ref asfdoc_sam0_sercom_usart_api_overview
+ *
+ * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites
+ *
+ * To use the USART you need to have a GCLK generator enabled and running
+ * that can be used as the SERCOM clock source. This can either be configured
+ * in conf_clocks.h or by using the system clock driver.
+ *
+ * \section asfdoc_sam0_sercom_usart_overview Module Overview
+ *
+ * This driver will use one (or more) SERCOM interfaces on the system
+ * and configure it to run as a USART interface in either synchronous
+ * or asynchronous mode.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_SYNC_SCHEME_V2</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_OVER_SAMPLE</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_HARDWARE_FLOW_CONTROL</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_IRDA</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_LIN_SLAVE</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_COLLISION_DECTION</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_START_FRAME_DECTION</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION</td>
+ * <td>SAM D21/R21/D10/D11</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format
+ *
+ * Communication is based on frames, where the frame format can be customized
+ * to accommodate a wide range of standards. A frame consists of a start bit,
+ * a number of data bits, an optional parity bit for error detection as well
+ * as a configurable length stop bit(s) - see
+ * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below".
+ * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the
+ * available parameters you can change in a frame.
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_params
+ * <table>
+ * <caption>USART Frame Parameters</caption>
+ * <tr>
+ * <th>Parameter</th>
+ * <th>Options</th>
+ * </tr>
+ * <tr>
+ * <td>Start bit</td>
+ * <td>1</td>
+ * </tr>
+ * <tr>
+ * <td>Data bits</td>
+ * <td>5, 6, 7, 8, 9</td>
+ * </tr>
+ * <tr>
+ * <td>Parity bit</td>
+ * <td>None, Even, Odd</td>
+ * </tr>
+ * <tr>
+ * <td>Stop bits</td>
+ * <td>1, 2</td>
+ * </tr>
+ * </table>
+ *
+ * \anchor asfdoc_sam0_sercom_usart_frame_diagram
+ * \image html usart_frame.svg "USART Frame overview" width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous mode
+ *
+ * In synchronous mode a dedicated clock line is provided; either by the USART
+ * itself if in master mode, or by an external master if in slave mode.
+ * Maximum transmission speed is the same as the GCLK clocking the USART
+ * peripheral when in slave mode, and the GCLK divided by two if in
+ * master mode. In synchronous mode the interface needs three lines to
+ * communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ * - XCK (Clock pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data sampling
+ * In synchronous mode the data is sampled on either the rising or falling edge
+ * of the clock signal. This is configured by setting the clock polarity in the
+ * configuration struct.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous mode
+ *
+ * In asynchronous mode no dedicated clock line is used, and the communication
+ * is based on matching the clock speed on the transmitter and receiver. The
+ * clock is generated from the internal SERCOM baudrate generator, and the
+ * frames are synchronized by using the frame start bits. Maximum transmission
+ * speed is limited to the SERCOM GCLK divided by 16.
+ * In asynchronous mode the interface only needs two lines to communicate:
+ * - TX (Transmit pin)
+ * - RX (Receive pin)
+ *
+ * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver clock matching
+ *
+ * For successful transmit and receive using the asynchronous mode the receiver
+ * and transmitter clocks needs to be closely matched. When receiving a frame
+ * that does not match the selected baud rate closely enough the receiver will
+ * be unable to synchronize the frame(s), and garbage transmissions will
+ * result.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_parity Parity
+ * Parity can be enabled to detect if a transmission was in error. This is done
+ * by counting the number of "1" bits in the frame. When using Even parity the
+ * parity bit will be set if the total number of "1"s in the frame are an even
+ * number. If using Odd parity the parity bit will be set if the total number
+ * of "1"s are Odd.
+ *
+ * When receiving a character the receiver will count the number of "1"s in the
+ * frame and give an error if the received frame and parity bit disagree.
+ *
+ * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO configuration
+ *
+ * The SERCOM module has four internal pads; the RX pin can be placed freely on
+ * any one of the four pads, and the TX and XCK pins have two predefined
+ * positions that can be selected as a pair. The pads can then be routed to an
+ * external GPIO pin using the normal pin multiplexing scheme on the SAM.
+ *
+ * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations
+ *
+ * \if USART_CALLBACK_MODE
+ * Never execute large portions of code in the callbacks. These
+ * are run from the interrupt routine, and thus having long callbacks will
+ * keep the processor in the interrupt handler for an equally long time.
+ * A common way to handle this is to use global flags signaling the
+ * main application that an interrupt event has happened, and only do the
+ * minimal needed processing in the callback.
+ * \else
+ * No special considerations.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_usart_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_sercom_usart_extra. This includes:
+ * - \ref asfdoc_sam0_sercom_usart_extra_acronyms
+ * - \ref asfdoc_sam0_sercom_usart_extra_dependencies
+ * - \ref asfdoc_sam0_sercom_usart_extra_errata
+ * - \ref asfdoc_sam0_sercom_usart_extra_history
+ *
+ * \section asfdoc_sam0_sercom_usart_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_usart_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_usart_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <sercom.h>
+#include <pinmux.h>
+
+#if USART_CALLBACK_MODE == true
+# include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver feature definition
+ * Define SERCOM USART features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || defined(__DOXYGEN__)
+/** Usart sync scheme version 2. */
+# define FEATURE_USART_SYNC_SCHEME_V2
+/** Usart over sampling. */
+# define FEATURE_USART_OVER_SAMPLE
+/** Usart hardware control flow. */
+# define FEATURE_USART_HARDWARE_FLOW_CONTROL
+/** IrDA mode. */
+# define FEATURE_USART_IRDA
+/** LIN slave mode. */
+# define FEATURE_USART_LIN_SLAVE
+/** Usart collision detection. */
+# define FEATURE_USART_COLLISION_DECTION
+/** Usart start frame detection. */
+# define FEATURE_USART_START_FRAME_DECTION
+/** Usart start buffer overflow notification. */
+# define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+#endif
+/*@}*/
+
+#ifndef PINMUX_DEFAULT
+/** Default pin mux. */
+# define PINMUX_DEFAULT 0
+#endif
+
+#ifndef PINMUX_UNUSED
+/** Unused PIN mux. */
+# define PINMUX_UNUSED 0xFFFFFFFF
+#endif
+
+#ifndef USART_TIMEOUT
+/** USART timeout value. */
+# define USART_TIMEOUT 0xFFFF
+#endif
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART Callback enum
+ *
+ * Callbacks for the Asynchronous USART driver
+ */
+enum usart_callback {
+ /** Callback for buffer transmitted */
+ USART_CALLBACK_BUFFER_TRANSMITTED,
+ /** Callback for buffer received */
+ USART_CALLBACK_BUFFER_RECEIVED,
+ /** Callback for error */
+ USART_CALLBACK_ERROR,
+#ifdef FEATURE_USART_LIN_SLAVE
+ /** Callback for break character is received. */
+ USART_CALLBACK_BREAK_RECEIVED,
+#endif
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+ /** Callback for a change is detected on the CTS pin. */
+ USART_CALLBACK_CTS_INPUT_CHANGE,
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /** Callback for a start condition is detected on the RxD line. */
+ USART_CALLBACK_START_RECEIVED,
+#endif
+# if !defined(__DOXYGEN__)
+ /** Number of available callbacks. */
+ USART_CALLBACK_N,
+# endif
+};
+#endif
+
+/**
+ * \brief USART Data Order enum
+ *
+ * The data order decides which of MSB or LSB is shifted out first when data is
+ * transferred
+ */
+enum usart_dataorder {
+ /** The MSB will be shifted out first during transmission,
+ * and shifted in first during reception */
+ USART_DATAORDER_MSB = 0,
+ /** The LSB will be shifted out first during transmission,
+ * and shifted in first during reception */
+ USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
+};
+
+/**
+ * \brief USART Transfer mode enum
+ *
+ * Select USART transfer mode
+ */
+enum usart_transfer_mode {
+ /** Transfer of data is done synchronously */
+ USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
+ /** Transfer of data is done asynchronously */
+ USART_TRANSFER_ASYNCHRONOUSLY = 0
+};
+
+/**
+ * \brief USART Parity enum
+ *
+ * Select parity USART parity mode
+ */
+enum usart_parity {
+ /** For odd parity checking, the parity bit will be set if number of
+ * ones being transferred is even */
+ USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE,
+
+ /** For even parity checking, the parity bit will be set if number of
+ * ones being received is odd */
+ USART_PARITY_EVEN = 0,
+
+ /** No parity checking will be executed, and there will be no parity bit
+ * in the received frame */
+ USART_PARITY_NONE = 0xFF,
+};
+
+/**
+ * \brief USART signal mux settings
+ *
+ * Set the functionality of the SERCOM pins.
+ *
+ * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the
+ * various MUX setting options.
+ */
+enum usart_signal_mux_settings {
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+ /** MUX setting RX_0_TX_0_XCK_1 */
+ USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_0_TX_2_XCK_3 */
+ USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */
+ USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
+ /** MUX setting RX_1_TX_0_XCK_1 */
+ USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_1_TX_2_XCK_3 */
+ USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */
+ USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
+ /** MUX setting RX_2_TX_0_XCK_1 */
+ USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_2_TX_2_XCK_3 */
+ USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */
+ USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
+ /** MUX setting RX_3_TX_0_XCK_1 */
+ USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
+ /** MUX setting RX_3_TX_2_XCK_3 */
+ USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
+ /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */
+ USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
+#else
+ /** MUX setting RX_0_TX_0_XCK_1 */
+ USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
+ /** MUX setting RX_0_TX_2_XCK_3 */
+ USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
+ /** MUX setting RX_1_TX_0_XCK_1 */
+ USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
+ /** MUX setting RX_1_TX_2_XCK_3 */
+ USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
+ /** MUX setting RX_2_TX_0_XCK_1 */
+ USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
+ /** MUX setting RX_2_TX_2_XCK_3 */
+ USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
+ /** MUX setting RX_3_TX_0_XCK_1 */
+ USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
+ /** MUX setting RX_3_TX_2_XCK_3 */
+ USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
+#endif
+};
+
+/**
+ * \brief USART Stop Bits enum
+ *
+ * Number of stop bits for a frame.
+ */
+enum usart_stopbits {
+ /** Each transferred frame contains 1 stop bit */
+ USART_STOPBITS_1 = 0,
+ /** Each transferred frame contains 2 stop bits */
+ USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
+};
+
+/**
+ * \brief USART Character Size
+ *
+ * Number of bits for the character sent in a frame.
+ */
+enum usart_character_size {
+ /** The char being sent in a frame is 5 bits long */
+ USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
+ /** The char being sent in a frame is 6 bits long */
+ USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
+ /** The char being sent in a frame is 7 bits long */
+ USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
+ /** The char being sent in a frame is 8 bits long */
+ USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
+ /** The char being sent in a frame is 9 bits long */
+ USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
+};
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+/**
+ * \brief USART Sample Rate
+ *
+ * The value of sample rate and baud rate generation mode.
+ */
+enum usart_sample_rate {
+ /** 16x over-sampling using arithmetic baud rate generation */
+ USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
+ /** 16x over-sampling using fractional baud rate generation */
+ USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
+ /** 8x over-sampling using arithmetic baud rate generation */
+ USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
+ /** 8x over-sampling using fractional baud rate generation */
+ USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
+ /** 3x over-sampling using arithmetic baud rate generation */
+ USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
+};
+
+/**
+ * \brief USART Sample Adjustment
+ *
+ * The value of sample number used for majority voting
+ */
+enum usart_sample_adjustment {
+ /** The first, middle and last sample number used for majority voting is 7-8-9 */
+ USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
+ /** The first, middle and last sample number used for majority voting is 9-10-11 */
+ USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
+ /** The first, middle and last sample number used for majority voting is 11-12-13 */
+ USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
+ /** The first, middle and last sample number used for majority voting is 13-14-15 */
+ USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
+};
+#endif
+
+/**
+ * \brief USART Transceiver
+ *
+ * Select Receiver or Transmitter
+ */
+enum usart_transceiver_type {
+ /** The parameter is for the Receiver */
+ USART_TRANSCEIVER_RX,
+ /** The parameter is for the Transmitter */
+ USART_TRANSCEIVER_TX,
+};
+
+/**
+ * \brief USART configuration struct
+ *
+ * Configuration options for USART
+ */
+struct usart_config {
+ /** USART bit order (MSB or LSB first) */
+ enum usart_dataorder data_order;
+ /** USART in asynchronous or synchronous mode */
+ enum usart_transfer_mode transfer_mode;
+ /** USART parity */
+ enum usart_parity parity;
+ /** Number of stop bits */
+ enum usart_stopbits stopbits;
+ /** USART character size */
+ enum usart_character_size character_size;
+ /** USART pin out */
+ enum usart_signal_mux_settings mux_setting;
+#ifdef FEATURE_USART_OVER_SAMPLE
+ /** USART sample rate */
+ enum usart_sample_rate sample_rate;
+ /** USART sample adjustment */
+ enum usart_sample_adjustment sample_adjustment;
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+ /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs.*/
+ bool immediate_buffer_overflow_notification;
+#endif
+#ifdef FEATURE_USART_IRDA
+ /** Enable IrDA encoding format */
+ bool encoding_format_enable;
+ /** The minimum pulse length that is required for a pulse to be accepted by the IrDA receiver */
+ uint8_t receive_pulse_length;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+ /** Enable LIN Slave Support */
+ bool lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /** Enable start of frame dection */
+ bool start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ /** Enable collision dection */
+ bool collision_detection_enable;
+#endif
+ /** USART baud rate */
+ uint32_t baudrate;
+ /** Enable receiver */
+ bool receiver_enable;
+ /** Enable transmitter */
+ bool transmitter_enable;
+
+ /** USART Clock Polarity.
+ * If true, data changes on falling XCK edge and
+ * is sampled at rising edge.
+ * If false, data changes on rising XCK edge and
+ * is sampled at falling edge.
+ * */
+ bool clock_polarity_inverted;
+
+ /** States whether to use the external clock applied to the XCK pin.
+ * In synchronous mode the shift register will act directly on the XCK clock.
+ * In asynchronous mode the XCK will be the input to the USART hardware module.
+ */
+ bool use_external_clock;
+ /** External clock frequency in synchronous mode.
+ * This must be set if \c use_external_clock is true. */
+ uint32_t ext_clock_freq;
+ /** If true the USART will be kept running in Standby sleep mode */
+ bool run_in_standby;
+ /** GCLK generator source */
+ enum gclk_generator generator_source;
+ /** PAD0 pinmux */
+ uint32_t pinmux_pad0;
+ /** PAD1 pinmux */
+ uint32_t pinmux_pad1;
+ /** PAD2 pinmux */
+ uint32_t pinmux_pad2;
+ /** PAD3 pinmux */
+ uint32_t pinmux_pad3;
+};
+
+#if USART_CALLBACK_MODE == true
+/**
+ * \brief USART module instance
+ *
+ * Forward Declaration for the device instance
+ */
+struct usart_module;
+
+/**
+ * \brief USART callback type
+ *
+ * Type of the callback functions
+ */
+typedef void (*usart_callback_t)(const struct usart_module *const module);
+#endif
+
+/**
+ * \brief SERCOM USART driver software device instance structure.
+ *
+ * SERCOM USART driver software instance structure, used to retain software
+ * state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ * application; they are reserved for module-internal use only.
+ */
+struct usart_module {
+#if !defined(__DOXYGEN__)
+ /** Pointer to the hardware instance */
+ Sercom *hw;
+ /** Module lock */
+ volatile bool locked;
+ /** Character size of the data being transferred */
+ enum usart_character_size character_size;
+ /** Receiver enabled */
+ bool receiver_enabled;
+ /** Transmitter enabled */
+ bool transmitter_enabled;
+#ifdef FEATURE_USART_LIN_SLAVE
+ /** LIN Slave Support enabled */
+ bool lin_slave_enabled;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ /** Start of frame dection enabled */
+ bool start_frame_detection_enabled;
+#endif
+# if USART_CALLBACK_MODE == true
+ /** Array to store callback function pointers in */
+ usart_callback_t callback[USART_CALLBACK_N];
+ /** Buffer pointer to where the next received character will be put */
+ volatile uint8_t *rx_buffer_ptr;
+
+ /** Buffer pointer to where the next character will be transmitted from
+ **/
+ volatile uint8_t *tx_buffer_ptr;
+ /** Remaining characters to receive */
+ volatile uint16_t remaining_rx_buffer_length;
+ /** Remaining characters to transmit */
+ volatile uint16_t remaining_tx_buffer_length;
+ /** Bit mask for callbacks registered */
+ uint8_t callback_reg_mask;
+ /** Bit mask for callbacks enabled */
+ uint8_t callback_enable_mask;
+ /** Holds the status of the ongoing or last read operation */
+ volatile enum status_code rx_status;
+ /** Holds the status of the ongoing or last write operation */
+ volatile enum status_code tx_status;
+# endif
+#endif
+};
+
+ /**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock.
+ *
+ * \retval STATUS_OK if the module was locked.
+ * \retval STATUS_BUSY if the module was already locked.
+ */
+static inline enum status_code usart_lock(
+ struct usart_module *const module)
+{
+ enum status_code status;
+
+ system_interrupt_enter_critical_section();
+
+ if (module->locked) {
+ status = STATUS_BUSY;
+ } else {
+ module->locked = true;
+ status = STATUS_OK;
+ }
+
+ system_interrupt_leave_critical_section();
+
+ return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock.
+ *
+ */
+static inline void usart_unlock(struct usart_module *const module)
+{
+ module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \brief Check if peripheral is busy syncing registers across clock domains
+ *
+ * Return peripheral synchronization status. If doing a non-blocking
+ * implementation this function can be used to check the sync state and hold of
+ * any new actions until sync is complete. If this functions is not run; the
+ * functions will block until the sync has completed.
+ *
+ * \param[in] module Pointer to peripheral module
+ *
+ * \return Peripheral sync status
+ *
+ * \retval true Peripheral is busy syncing
+ * \retval false Peripheral is not busy syncing and can be read/written without
+ * stalling the bus.
+ */
+static inline bool usart_is_syncing(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+#ifdef FEATURE_USART_SYNC_SCHEME_V2
+ return (usart_hw->SYNCBUSY.reg);
+#else
+ return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
+#endif
+}
+
+#if !defined (__DOXYGEN__)
+/**
+ * \internal
+ * Waits until synchronization is complete
+ */
+static inline void _usart_wait_for_sync(
+ const struct usart_module *const module)
+{
+ /* Sanity check. */
+ Assert(module);
+
+ while (usart_is_syncing(module)) {
+ /* Wait until the synchronization is complete */
+ }
+}
+#endif
+
+/**
+ * \brief Initializes the device to predefined defaults
+ *
+ * Initialize the USART device to predefined defaults:
+ * - 8-bit asynchronous USART
+ * - No parity
+ * - 1 stop bit
+ * - 9600 baud
+ * - Transmitter enabled
+ * - Receiver enabled
+ * - GCLK generator 0 as clock source
+ * - Default pin configuration
+ *
+ * The configuration struct will be updated with the default
+ * configuration.
+ *
+ * \param[in,out] config Pointer to configuration struct
+ */
+static inline void usart_get_config_defaults(
+ struct usart_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Set default config in the config struct */
+ config->data_order = USART_DATAORDER_LSB;
+ config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY;
+ config->parity = USART_PARITY_NONE;
+ config->stopbits = USART_STOPBITS_1;
+ config->character_size = USART_CHARACTER_SIZE_8BIT;
+ config->baudrate = 9600;
+ config->receiver_enable = true;
+ config->transmitter_enable = true;
+ config->clock_polarity_inverted = false;
+ config->use_external_clock = false;
+ config->ext_clock_freq = 0;
+ config->mux_setting = USART_RX_1_TX_2_XCK_3;
+ config->run_in_standby = false;
+ config->generator_source = GCLK_GENERATOR_0;
+ config->pinmux_pad0 = PINMUX_DEFAULT;
+ config->pinmux_pad1 = PINMUX_DEFAULT;
+ config->pinmux_pad2 = PINMUX_DEFAULT;
+ config->pinmux_pad3 = PINMUX_DEFAULT;
+#ifdef FEATURE_USART_OVER_SAMPLE
+ config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9;
+ config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC;
+#endif
+#ifdef FEATURE_USART_LIN_SLAVE
+ config->lin_slave_enable = false;
+#endif
+#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+ config->immediate_buffer_overflow_notification = false;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+ config->start_frame_detection_enable = false;
+#endif
+#ifdef FEATURE_USART_IRDA
+ config->encoding_format_enable = false;
+ config->receive_pulse_length = 19;
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+ config->collision_detection_enable = false;
+#endif
+}
+
+enum status_code usart_init(
+ struct usart_module *const module,
+ Sercom *const hw,
+ const struct usart_config *const config);
+
+/**
+ * \brief Enable the module
+ *
+ * Enables the USART module
+ *
+ * \param[in] module Pointer to USART software instance struct
+ */
+static inline void usart_enable(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+#if USART_CALLBACK_MODE == true
+ /* Enable Global interrupt for module */
+ system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Enable USART module */
+ usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Disable module
+ *
+ * Disables the USART module
+ *
+ * \param[in] module Pointer to USART software instance struct
+ */
+static inline void usart_disable(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Disable Global interrupt for module */
+ system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Disable USART module */
+ usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+}
+
+/**
+ * \brief Resets the USART module
+ *
+ * Disables and resets the USART module.
+ *
+ * \param[in] module Pointer to the USART software instance struct
+ */
+static inline void usart_reset(
+ const struct usart_module *const module)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ usart_disable(module);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ /* Reset module */
+ usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
+}
+
+/**
+ * \name Writing and reading
+ * @{
+ */
+enum status_code usart_write_wait(
+ struct usart_module *const module,
+ const uint16_t tx_data);
+
+enum status_code usart_read_wait(
+ struct usart_module *const module,
+ uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_wait(
+ struct usart_module *const module,
+ const uint8_t *tx_data,
+ uint16_t length);
+
+enum status_code usart_read_buffer_wait(
+ struct usart_module *const module,
+ uint8_t *rx_data,
+ uint16_t length);
+/** @} */
+
+/**
+ * \name Enabling/Disabling receiver and transmitter
+ * @{
+ */
+
+/**
+ * \brief Enable Transceiver
+ *
+ * Enable the given transceiver. Either RX or TX.
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] transceiver_type Transceiver type.
+ */
+static inline void usart_enable_transceiver(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ switch (transceiver_type) {
+ case USART_TRANSCEIVER_RX:
+ /* Enable RX */
+ usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+ module->receiver_enabled = true;
+ break;
+
+ case USART_TRANSCEIVER_TX:
+ /* Enable TX */
+ usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+ module->transmitter_enabled = true;
+ break;
+ }
+}
+
+/**
+ * \brief Disable Transceiver
+ *
+ * Disable the given transceiver (RX or TX).
+ *
+ * \param[in] module Pointer to USART software instance struct
+ * \param[in] transceiver_type Transceiver type.
+ */
+static inline void usart_disable_transceiver(
+ struct usart_module *const module,
+ enum usart_transceiver_type transceiver_type)
+{
+ /* Sanity check arguments */
+ Assert(module);
+ Assert(module->hw);
+
+ /* Get a pointer to the hardware module instance */
+ SercomUsart *const usart_hw = &(module->hw->USART);
+
+ /* Wait until synchronization is complete */
+ _usart_wait_for_sync(module);
+
+ switch (transceiver_type) {
+ case USART_TRANSCEIVER_RX:
+ /* Disable RX */
+ usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+ module->receiver_enabled = false;
+ break;
+
+ case USART_TRANSCEIVER_TX:
+ /* Disable TX */
+ usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+ module->transmitter_enabled = false;
+ break;
+ }
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver
+*
+* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms
+*
+* Below is a table listing the acronyms used in this module, along with their
+* intended meanings.
+*
+* <table>
+* <tr>
+* <th>Acronym</th>
+* <th>Description</th>
+* </tr>
+* <tr>
+* <td>SERCOM</td>
+* <td>Serial Communication Interface</td>
+* </tr>
+* <tr>
+* <td>USART</td>
+* <td>Universal Synchronous and Asynchronous Serial Receiver and Transmitter</td>
+* </tr>
+* <tr>
+* <td>LSB</td>
+* <td>Least Significant Bit</td>
+* </tr>
+* <tr>
+* <td>MSB</td>
+* <td>Most Significant Bit</td>
+* </tr>
+* <tr>
+* <td>DMA</td>
+* <td>Direct Memory Access</td>
+* </tr>
+* </table>
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies
+* This driver has the following dependencies:
+*
+* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+* - \ref asfdoc_sam0_system_clock_group "System clock configuration"
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_errata Errata
+* There are no errata related to this driver.
+*
+*
+* \section asfdoc_sam0_sercom_usart_extra_history Module History
+* An overview of the module history is presented in the table below, with
+* details on the enhancements and fixes made to the module since its first
+* release. The current version of this corresponds to the newest version in
+* the table.
+*
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAMD10/D11 (same features as SAMD21).</td>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAMR21 (same features as SAMD21).</td>
+ * </tr>
+ * <tr>
+ * <td>Add support for SAMD21 and added new feature as below:
+ \li Oversample
+ \li Buffer overflow notification
+ \li Irda
+ \li Lin slave
+ \li Start frame detection
+ \li Hardware flow control
+ \li Collision detection
+ \li DMA support </td>
+ * </tr>
+ * <tr>
+ * <td>\li Added new \c transmitter_enable and \c receiver_enable boolean
+ * values to \c struct usart_config.
+ * \li Altered \c usart_write_* and usart_read_* functions to abort with
+ * an error code if the relevant transceiver is not enabled.
+ * \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()
+ * not aborting correctly when a timeout condition occurs.</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+*/
+
+/**
+ * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_sercom_usart_basic_use_case
+ * \if USART_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_usart_callback_use_case
+ * \endif
+ * - \subpage asfdoc_sam0_sercom_usart_dma_use_case
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings
+ *
+ * The following lists the possible internal SERCOM module pad function
+ * assignments, for the four SERCOM pads when in USART mode. Note that this is
+ * in addition to the physical GPIO pin MUX of the device, and can be used in
+ * conjunction to optimize the serial data pin-out.
+ *
+ * When TX and RX are connected to the same pin, the USART will operate in
+ * half-duplex mode if both the transmitter and receivers are enabled.
+ *
+ * \note When RX and XCK are connected to the same pin, the receiver must not
+ * be enabled if the USART is configured to use an external clock.
+ *
+ *
+ * <table>
+ * <tr>
+ * <th>Mux/Pad</th>
+ * <th>PAD 0</th>
+ * <th>PAD 1</th>
+ * <th>PAD 2</th>
+ * <th>PAD 3</th>
+ * </tr>
+ * <tr>
+ * <td>RX_0_TX_0_XCK_1</td>
+ * <td>TX / RX</td>
+ * <td>XCK</td>
+ * <td>-</td>
+ * <td>-</td>
+ * </tr>
+ * <tr>
+ * <td>RX_0_TX_2_XCK_3</td>
+ * <td>RX</td>
+ * <td>-</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * </tr>
+ * <tr>
+ * <td>RX_1_TX_0_XCK_1</td>
+ * <td>TX</td>
+ * <td>RX / XCK</td>
+ * <td>-</td>
+ * <td>-</td>
+ * </tr>
+ * <tr>
+ * <td>RX_1_TX_2_XCK_3</td>
+ * <td>-</td>
+ * <td>RX</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * </tr>
+ * <tr>
+ * <td>RX_2_TX_0_XCK_1</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * <td>RX</td>
+ * <td>-</td>
+ * </tr>
+ * <tr>
+ * <td>RX_2_TX_2_XCK_3</td>
+ * <td>-</td>
+ * <td>-</td>
+ * <td>TX / RX</td>
+ * <td>XCK</td>
+ * </tr>
+ * <tr>
+ * <td>RX_3_TX_0_XCK_1</td>
+ * <td>TX</td>
+ * <td>XCK</td>
+ * <td>-</td>
+ * <td>RX</td>
+ * </tr>
+ * <tr>
+ * <td>RX_3_TX_2_XCK_3</td>
+ * <td>-</td>
+ * <td>-</td>
+ * <td>TX</td>
+ * <td>RX / XCK</td>
+ * </tr>
+ * </table>
+ *
+ * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>F</td>
+ * <td>05/2014</td>
+ * <td>Add support for SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>03/2014</td>
+ * <td>Add support for SAMR21.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>01/2014</td>
+ * <td>Add support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>10/2013</td>
+ * <td>Replaced the pad multiplexing documentation with a condensed table.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+#endif /* USART_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock.h
new file mode 100755
index 0000000000000000000000000000000000000000..a1f35db680f3007d6ad815d87c238c6ec35f4d49
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock.h
@@ -0,0 +1,1526 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SYSTEM_CLOCK_H_INCLUDED
+#define SYSTEM_CLOCK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of the device's clocking related functions. This includes
+ * the various clock sources, bus clocks and generic clocks within the device,
+ * with functions to manage the enabling, disabling, source selection and
+ * prescaling of clocks to various internal peripherals.
+ *
+ * The following peripherals are used by this module:
+ *
+ * - GCLK (Generic Clock Management)
+ * - PM (Power Management)
+ * - SYSCTRL (Clock Source Control)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_clock_prerequisites
+ * - \ref asfdoc_sam0_system_clock_module_overview
+ * - \ref asfdoc_sam0_system_clock_special_considerations
+ * - \ref asfdoc_sam0_system_clock_extra_info
+ * - \ref asfdoc_sam0_system_clock_examples
+ * - \ref asfdoc_sam0_system_clock_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_clock_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_module_overview Module Overview
+ * The SAM devices contain a sophisticated clocking system, which is designed
+ * to give the maximum flexibility to the user application. This system allows
+ * a system designer to tune the performance and power consumption of the device
+ * in a dynamic manner, to achieve the best trade-off between the two for a
+ * particular application.
+ *
+ * This driver provides a set of functions for the configuration and management
+ * of the various clock related functionality within the device.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
+ * <table>
+ * <tr>
+ * <th>Driver Feature Macro</th>
+ * <th>Supported devices</th>
+ * </tr>
+ * <tr>
+ * <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ * <td>SAMD21, SAMR21, SAMD10, SAMD11</td>
+ * </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
+ * The SAM devices have a number of master clock source modules, each of
+ * which being capable of producing a stabilized output frequency which can then
+ * be fed into the various peripherals and modules within the device.
+ *
+ * Possible clock source modules include internal R/C oscillators, internal
+ * DFLL modules, as well as external crystal oscillators and/or clock inputs.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
+ * The CPU and AHB/APBx buses are clocked by the same physical clock source
+ * (referred in this module as the Main Clock), however the APBx buses may
+ * have additional prescaler division ratios set to give each peripheral bus a
+ * different clock speed.
+ *
+ * The general main clock tree for the CPU and associated buses is shown in
+ * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_clock_tree
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * clk_src [label="Clock Sources", shape=none, height=0];
+ * node [label="CPU Bus" shape=ellipse] cpu_bus;
+ * node [label="AHB Bus" shape=ellipse] ahb_bus;
+ * node [label="APBA Bus" shape=ellipse] apb_a_bus;
+ * node [label="APBB Bus" shape=ellipse] apb_b_bus;
+ * node [label="APBC Bus" shape=ellipse] apb_c_bus;
+ * node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
+ * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
+ * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
+ * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
+ * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
+ *
+ * clk_src -> main_clock_mux;
+ * main_clock_mux -> main_prescaler;
+ * main_prescaler -> cpu_bus;
+ * main_prescaler -> ahb_bus;
+ * main_prescaler -> apb_a_prescaler;
+ * main_prescaler -> apb_b_prescaler;
+ * main_prescaler -> apb_c_prescaler;
+ * apb_a_prescaler -> apb_a_bus;
+ * apb_b_prescaler -> apb_b_bus;
+ * apb_c_prescaler -> apb_c_bus;
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
+ * To save power, the input clock to one or more peripherals on the AHB and APBx
+ * buses can be masked away - when masked, no clock is passed into the module.
+ * Disabling of clocks of unused modules will prevent all access to the masked
+ * module, but will reduce the overall device power consumption.
+ *
+ * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
+ * Within the SAM devices are a number of Generic Clocks; these are used to
+ * provide clocks to the various peripheral clock domains in the device in a
+ * standardized manner. One or more master source clocks can be selected as the
+ * input clock to a Generic Clock Generator, which can prescale down the input
+ * frequency to a slower rate for use in a peripheral.
+ *
+ * Additionally, a number of individually selectable Generic Clock Channels are
+ * provided, which multiplex and gate the various generator outputs for one or
+ * more peripherals within the device. This setup allows for a single common
+ * generator to feed one or more channels, which can then be enabled or disabled
+ * individually as required.
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_overview
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * node [label="Clock\nSource a" shape=square] system_clock_source;
+ * node [label="Generator 1" shape=square] clock_gen;
+ * node [label="Channel x" shape=square] clock_chan0;
+ * node [label="Channel y" shape=square] clock_chan1;
+ * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ *
+ * system_clock_source -> clock_gen;
+ * clock_gen -> clock_chan0;
+ * clock_chan0 -> peripheral0;
+ * clock_gen -> clock_chan1;
+ * clock_chan1 -> peripheral1;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
+ * An example setup of a complete clock chain within the device is shown in
+ * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
+ *
+ * \anchor asfdoc_sam0_system_clock_module_chain_example_fig
+ * \dot
+ * digraph overview {
+ * rankdir=LR;
+ * node [label="External\nOscillator" shape=square] system_clock_source0;
+ * node [label="Generator 0" shape=square] clock_gen0;
+ * node [label="Channel x" shape=square] clock_chan0;
+ * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
+ *
+ * system_clock_source0 -> clock_gen0;
+ * clock_gen0 -> clock_chan0;
+ * clock_chan0 -> peripheral0;
+ * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
+ * node [label="Generator 1" shape=square] clock_gen1;
+ * node [label="Channel y" shape=square] clock_chan1;
+ * node [label="Channel z" shape=square] clock_chan2;
+ * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
+ * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;
+ *
+ * system_clock_source1 -> clock_gen1;
+ * clock_gen1 -> clock_chan1;
+ * clock_gen1 -> clock_chan2;
+ * clock_chan1 -> peripheral1;
+ * clock_chan2 -> peripheral2;
+ * }
+ * \enddot
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
+ * Each Generic Clock generator within the device can source its input clock
+ * from one of the provided Source Clocks, and prescale the output for one or
+ * more Generic Clock Channels in a one-to-many relationship. The generators
+ * thus allow for several clocks to be generated of different frequencies,
+ * power usages and accuracies, which can be turned on and off individually to
+ * disable the clocks to multiple peripherals as a group.
+ *
+ * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
+ * To connect a Generic Clock Generator to a peripheral within the
+ * device, a Generic Clock Channel is used. Each peripheral or
+ * peripheral group has an associated Generic Clock Channel, which serves as the
+ * clock input for the peripheral(s). To supply a clock to the peripheral
+ * module(s), the associated channel must be connected to a running Generic
+ * Clock Generator and the channel enabled.
+ *
+ * \section asfdoc_sam0_system_clock_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_system_clock_extra. This includes:
+ * - \ref asfdoc_sam0_system_clock_extra_acronyms
+ * - \ref asfdoc_sam0_system_clock_extra_dependencies
+ * - \ref asfdoc_sam0_system_clock_extra_errata
+ * - \ref asfdoc_sam0_system_clock_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_clock_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_clock_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <gclk.h>
+
+/**
+ * \name Driver feature definition
+ * Define system clock features set according to different device family.
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || defined(__DOXYGEN__)
+/** Digital Phase Locked Loop (DPLL) feature support */
+# define FEATURE_SYSTEM_CLOCK_DPLL
+#endif
+/*@}*/
+
+/**
+ * \brief Available start-up times for the XOSC32K
+ *
+ * Available external 32KHz oscillator start-up times, as a number of external
+ * clock cycles.
+ */
+enum system_xosc32k_startup {
+ /** Wait 0 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_0,
+ /** Wait 32 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_32,
+ /** Wait 2048 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_2048,
+ /** Wait 4096 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_4096,
+ /** Wait 16384 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_16384,
+ /** Wait 32768 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_32768,
+ /** Wait 65536 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_65536,
+ /** Wait 131072 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC32K_STARTUP_131072,
+};
+
+/**
+ * \brief Available start-up times for the XOSC
+ *
+ * Available external oscillator start-up times, as a number of external clock
+ * cycles.
+ */
+enum system_xosc_startup {
+ /** Wait 1 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_1,
+ /** Wait 2 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_2,
+ /** Wait 4 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_4,
+ /** Wait 8 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_8,
+ /** Wait 16 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_16,
+ /** Wait 32 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_32,
+ /** Wait 64 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_64,
+ /** Wait 128 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_128,
+ /** Wait 256 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_256,
+ /** Wait 512 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_512,
+ /** Wait 1024 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_1024,
+ /** Wait 2048 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_2048,
+ /** Wait 4096 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_4096,
+ /** Wait 8192 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_8192,
+ /** Wait 16384 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_16384,
+ /** Wait 32768 clock cycles until the clock source is considered stable */
+ SYSTEM_XOSC_STARTUP_32768,
+};
+
+/**
+ * \brief Available start-up times for the OSC32K
+ *
+ * Available internal 32KHz oscillator start-up times, as a number of internal
+ * OSC32K clock cycles.
+ */
+enum system_osc32k_startup {
+ /** Wait 3 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_3,
+ /** Wait 4 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_4,
+ /** Wait 6 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_6,
+ /** Wait 10 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_10,
+ /** Wait 18 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_18,
+ /** Wait 34 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_34,
+ /** Wait 66 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_66,
+ /** Wait 130 clock cycles until the clock source is considered stable */
+ SYSTEM_OSC32K_STARTUP_130,
+};
+
+/**
+ * \brief Division prescalers for the internal 8MHz system clock
+ *
+ * Available prescalers for the internal 8MHz (nominal) system clock.
+ */
+enum system_osc8m_div {
+ /** Do not divide the 8MHz RC oscillator output */
+ SYSTEM_OSC8M_DIV_1,
+ /** Divide the 8MHz RC oscillator output by 2 */
+ SYSTEM_OSC8M_DIV_2,
+ /** Divide the 8MHz RC oscillator output by 4 */
+ SYSTEM_OSC8M_DIV_4,
+ /** Divide the 8MHz RC oscillator output by 8 */
+ SYSTEM_OSC8M_DIV_8,
+};
+
+/**
+ * \brief Frequency range for the internal 8Mhz RC oscillator
+ *
+ * Internal 8Mhz RC oscillator frequency range setting
+ */
+enum system_osc8m_frequency_range {
+ /** Frequency range 4 Mhz to 6 Mhz */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+ /** Frequency range 6 Mhz to 8 Mhz */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+ /** Frequency range 8 Mhz to 11 Mhz */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+ /** Frequency range 11 Mhz to 15 Mhz */
+ SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+};
+
+/**
+ * \brief Main CPU and APB/AHB bus clock source prescaler values
+ *
+ * Available division ratios for the CPU and APB/AHB bus clocks.
+ */
+enum system_main_clock_div {
+ /** Divide Main clock by 1 */
+ SYSTEM_MAIN_CLOCK_DIV_1,
+ /** Divide Main clock by 2 */
+ SYSTEM_MAIN_CLOCK_DIV_2,
+ /** Divide Main clock by 4 */
+ SYSTEM_MAIN_CLOCK_DIV_4,
+ /** Divide Main clock by 8 */
+ SYSTEM_MAIN_CLOCK_DIV_8,
+ /** Divide Main clock by 16 */
+ SYSTEM_MAIN_CLOCK_DIV_16,
+ /** Divide Main clock by 32 */
+ SYSTEM_MAIN_CLOCK_DIV_32,
+ /** Divide Main clock by 64 */
+ SYSTEM_MAIN_CLOCK_DIV_64,
+ /** Divide Main clock by 128 */
+ SYSTEM_MAIN_CLOCK_DIV_128,
+};
+
+/**
+ * \brief External clock source types.
+ *
+ * Available external clock source types.
+ */
+enum system_clock_external {
+ /** The external clock source is a crystal oscillator */
+ SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+ /** The connected clock source is an external logic level clock signal */
+ SYSTEM_CLOCK_EXTERNAL_CLOCK,
+};
+
+/**
+ * \brief Operating modes of the DFLL clock source.
+ *
+ * Available operating modes of the DFLL clock source module,
+ */
+enum system_clock_dfll_loop_mode {
+ /** The DFLL is operating in open loop mode with no feedback */
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+ /** The DFLL is operating in closed loop mode with frequency feedback from
+ * a low frequency reference clock
+ */
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+
+#ifdef SYSCTRL_DFLLCTRL_USBCRM
+ /** The DFLL is operating in USB recovery mode with frequency feedback
+ * from USB SOF
+ */
+ SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+#endif
+};
+
+/**
+ * \brief Locking behavior for the DFLL during device wake-up
+ *
+ * DFLL lock behavior modes on device wake-up from sleep.
+ */
+enum system_clock_dfll_wakeup_lock {
+ /** Keep DFLL lock when the device wakes from sleep */
+ SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+ /** Lose DFLL lock when the devices wakes from sleep */
+ SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+};
+
+/**
+ * \brief Fine tracking behavior for the DFLL once a lock has been acquired
+ *
+ * DFLL fine tracking behavior modes after a lock has been acquired.
+ */
+enum system_clock_dfll_stable_tracking {
+ /** Keep tracking after the DFLL has gotten a fine lock */
+ SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+ /** Stop tracking after the DFLL has gotten a fine lock */
+ SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+};
+
+/**
+ * \brief Chill-cycle behavior of the DFLL module
+ *
+ * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
+ * of time when the DFLL output frequency is not measured by the unit, to allow
+ * the output to stabilize after a change in the input clock source.
+ */
+enum system_clock_dfll_chill_cycle {
+ /** Enable a chill cycle, where the DFLL output frequency is not measured */
+ SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+ /** Disable a chill cycle, where the DFLL output frequency is not measured */
+ SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+};
+
+/**
+ * \brief QuickLock settings for the DFLL module
+ *
+ * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
+ * the DFLL output frequency at the expense of accuracy.
+ */
+enum system_clock_dfll_quick_lock {
+ /** Enable the QuickLock feature for looser lock requirements on the DFLL */
+ SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+ /** Disable the QuickLock feature for strict lock requirements on the DFLL */
+ SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+};
+
+/**
+ * \brief Available clock sources in the system
+ *
+ * Clock sources available to the GCLK generators
+ */
+enum system_clock_source {
+ /** Internal 8MHz RC oscillator */
+ SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,
+ /** Internal 32kHz RC oscillator */
+ SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
+ /** External oscillator */
+ SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
+ /** External 32kHz oscillator */
+ SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
+ /** Digital Frequency Locked Loop (DFLL) */
+ SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
+ /** Internal Ultra Low Power 32kHz oscillator */
+ SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
+ /** Generator input pad */
+ SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
+ /** Generic clock generator 1 output */
+ SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ /** Digital Phase Locked Loop (DPLL).
+ * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+ */
+ SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
+#endif
+};
+
+/**
+ * \brief List of APB peripheral buses
+ *
+ * Available bus clock domains on the APB bus.
+ */
+enum system_clock_apb_bus {
+ /** Peripheral bus A on the APB bus. */
+ SYSTEM_CLOCK_APB_APBA,
+ /** Peripheral bus B on the APB bus. */
+ SYSTEM_CLOCK_APB_APBB,
+ /** Peripheral bus C on the APB bus. */
+ SYSTEM_CLOCK_APB_APBC,
+};
+
+/**
+ * \brief Configuration structure for XOSC
+ *
+ * External oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc_config {
+ /** External clock type */
+ enum system_clock_external external_clock;
+ /** Crystal oscillator start-up time */
+ enum system_xosc_startup startup_time;
+ /** Enable automatic amplitude gain control */
+ bool auto_gain_control;
+ /** External clock/crystal frequency */
+ uint32_t frequency;
+ /** Keep the XOSC enabled in standby sleep mode */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the XOSC won't run
+ * until requested by a peripheral */
+ bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for XOSC32K
+ *
+ * External 32KHz oscillator clock configuration structure.
+ */
+struct system_clock_source_xosc32k_config {
+ /** External clock type */
+ enum system_clock_external external_clock;
+ /** Crystal oscillator start-up time */
+ enum system_xosc32k_startup startup_time;
+ /** Enable automatic amplitude control */
+ bool auto_gain_control;
+ /** Enable 1kHz output */
+ bool enable_1khz_output;
+ /** Enable 32kHz output */
+ bool enable_32khz_output;
+ /** External clock/crystal frequency */
+ uint32_t frequency;
+ /** Keep the XOSC32K enabled in standby sleep mode */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the XOSC32K won't run
+ * until requested by a peripheral */
+ bool on_demand;
+ /** Lock configuration after it has been written,
+ * a device reset will release the lock */
+ bool write_once;
+};
+
+/**
+ * \brief Configuration structure for OSC8M
+ *
+ * Internal 8MHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc8m_config {
+ /* Internal 8MHz RC oscillator prescaler */
+ enum system_osc8m_div prescaler;
+ /** Keep the OSC8M enabled in standby sleep mode */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the OSC8M won't run
+ * until requested by a peripheral */
+ bool on_demand;
+};
+
+/**
+ * \brief Configuration structure for OSC32K
+ *
+ * Internal 32KHz (nominal) oscillator configuration structure.
+ */
+struct system_clock_source_osc32k_config {
+ /** Startup time */
+ enum system_osc32k_startup startup_time;
+ /** Enable 1kHz output */
+ bool enable_1khz_output;
+ /** Enable 32kHz output */
+ bool enable_32khz_output;
+ /** Keep the OSC32K enabled in standby sleep mode */
+ bool run_in_standby;
+ /** Run On Demand. If this is set the OSC32K won't run
+ * until requested by a peripheral */
+ bool on_demand;
+ /** Lock configuration after it has been written,
+ * a device reset will release the lock */
+ bool write_once;
+};
+
+/**
+ * \brief Configuration structure for DFLL
+ *
+ * DFLL oscillator configuration structure.
+ */
+struct system_clock_source_dfll_config {
+ /** Loop mode */
+ enum system_clock_dfll_loop_mode loop_mode;
+ /** Run On Demand. If this is set the DFLL won't run
+ * until requested by a peripheral */
+ bool on_demand;
+ /** Enable Quick Lock */
+ enum system_clock_dfll_quick_lock quick_lock;
+ /** Enable Chill Cycle */
+ enum system_clock_dfll_chill_cycle chill_cycle;
+ /** DFLL lock state on wakeup */
+ enum system_clock_dfll_wakeup_lock wakeup_lock;
+ /** DFLL tracking after fine lock */
+ enum system_clock_dfll_stable_tracking stable_tracking;
+ /** Coarse calibration value (Open loop mode) */
+ uint8_t coarse_value;
+ /** Fine calibration value (Open loop mode) */
+ uint16_t fine_value;
+ /** Coarse adjustment max step size (Closed loop mode) */
+ uint8_t coarse_max_step;
+ /** Fine adjustment max step size (Closed loop mode) */
+ uint16_t fine_max_step;
+ /** DFLL multiply factor (Closed loop mode */
+ uint16_t multiply_factor;
+};
+
+/**
+ * \name External Oscillator management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external oscillator module:
+ * - External Crystal
+ * - Start-up time of 16384 external clock cycles
+ * - Automatic crystal gain control mode enabled
+ * - Frequency of 12MHz
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc_get_config_defaults(
+ struct system_clock_source_xosc_config *const config)
+{
+ Assert(config);
+
+ config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+ config->startup_time = SYSTEM_XOSC_STARTUP_16384;
+ config->auto_gain_control = true;
+ config->frequency = 12000000UL;
+ config->run_in_standby = false;
+ config->on_demand = true;
+}
+
+void system_clock_source_xosc_set_config(
+ struct system_clock_source_xosc_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name External 32KHz Oscillator management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for XOSC32K
+ *
+ * Fills a configuration structure with the default configuration for an
+ * external 32KHz oscillator module:
+ * - External Crystal
+ * - Start-up time of 16384 external clock cycles
+ * - Automatic crystal gain control mode disabled
+ * - Frequency of 32.768KHz
+ * - 1KHz clock output disabled
+ * - 32KHz clock output enabled
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ * - Don't lock registers after configuration has been written
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_xosc32k_get_config_defaults(
+ struct system_clock_source_xosc32k_config *const config)
+{
+ Assert(config);
+
+ config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+ config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;
+ config->auto_gain_control = false;
+ config->frequency = 32768UL;
+ config->enable_1khz_output = false;
+ config->enable_32khz_output = true;
+ config->run_in_standby = false;
+ config->on_demand = true;
+ config->write_once = false;
+}
+
+void system_clock_source_xosc32k_set_config(
+ struct system_clock_source_xosc32k_config *const config);
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 32KHz Oscillator management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC32K
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 32KHz oscillator module:
+ * - 1KHz clock output enabled
+ * - 32KHz clock output enabled
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ * - Set startup time to 130 cycles
+ * - Don't lock registers after configuration has been written
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc32k_get_config_defaults(
+ struct system_clock_source_osc32k_config *const config)
+{
+ Assert(config);
+
+ config->enable_1khz_output = true;
+ config->enable_32khz_output = true;
+ config->run_in_standby = false;
+ config->on_demand = true;
+ config->startup_time = SYSTEM_OSC32K_STARTUP_130;
+ config->write_once = false;
+}
+
+void system_clock_source_osc32k_set_config(
+ struct system_clock_source_osc32k_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal 8MHz Oscillator management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for OSC8M
+ *
+ * Fills a configuration structure with the default configuration for an
+ * internal 8MHz (nominal) oscillator module:
+ * - Clock output frequency divided by a factor of 8
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_osc8m_get_config_defaults(
+ struct system_clock_source_osc8m_config *const config)
+{
+ Assert(config);
+
+ config->prescaler = SYSTEM_OSC8M_DIV_8;
+ config->run_in_standby = false;
+ config->on_demand = true;
+}
+
+void system_clock_source_osc8m_set_config(
+ struct system_clock_source_osc8m_config *const config);
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Internal DFLL management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DFLL
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DFLL oscillator module:
+ * - Open loop mode
+ * - QuickLock mode enabled
+ * - Chill cycle enabled
+ * - Output frequency lock maintained during device wake-up
+ * - Continuous tracking of the output frequency
+ * - Default tracking values at the mid-points for both coarse and fine
+ * tracking parameters
+ * - Don't run in STANDBY sleep mode
+ * - Run only when requested by peripheral (on demand)
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dfll_get_config_defaults(
+ struct system_clock_source_dfll_config *const config)
+{
+ Assert(config);
+
+ config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+ config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+ config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+ config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+ config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+ config->on_demand = true;
+
+ /* Open loop mode calibration value */
+ config->coarse_value = 0x1f / 4; /* Midpoint */
+ config->fine_value = 0xff / 4; /* Midpoint */
+
+ /* Closed loop mode */
+ config->coarse_max_step = 1;
+ config->fine_max_step = 1;
+ config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+}
+
+void system_clock_source_dfll_set_config(
+ struct system_clock_source_dfll_config *const config);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Clock source management
+ * @{
+ */
+enum status_code system_clock_source_write_calibration(
+ const enum system_clock_source system_clock_source,
+ const uint16_t calibration_value,
+ const uint8_t freq_range);
+
+enum status_code system_clock_source_enable(
+ const enum system_clock_source system_clock_source);
+
+enum status_code system_clock_source_disable(
+ const enum system_clock_source clk_source);
+
+bool system_clock_source_is_ready(
+ const enum system_clock_source clk_source);
+
+uint32_t system_clock_source_get_hz(
+ const enum system_clock_source clk_source);
+
+/**
+ * @}
+ */
+
+/**
+ * \name Main clock management
+ * @{
+ */
+
+#ifdef FEATURE_SYSTEM_CLOCK_FAILURE_DETECT
+/**
+ * \brief Enable or disable the main clock failure detection.
+ *
+ * This mechanism allows switching automatically the main clock to the safe
+ * RCSYS clock, when the main clock source is considered off.
+ *
+ * This may happen for instance when an external crystal is selected as the
+ * clock source of the main clock and the crystal dies. The mechanism is to
+ * detect, during a RCSYS period, at least one rising edge of the main clock.
+ * If no rising edge is seen the clock is considered failed.
+ * As soon as the detector is enabled, the clock failure detector
+ * CFD) will monitor the divided main clock. When a clock failure is detected,
+ * the main clock automatically switches to the RCSYS clock and the CFD
+ * interrupt is generated if enabled.
+ *
+ * \note The failure detect must be disabled if the system clock is the same or
+ * slower than 32kHz as it will believe the system clock has failed with
+ * a too-slow clock.
+ *
+ * \param[in] enable Boolean \c true to enable, \c false to disable detection
+ */
+static inline void system_main_clock_set_failure_detect(
+ const bool enable)
+{
+ if (enable) {
+ PM->CTRL.reg |= PM_CTRL_CFDEN;
+ } else {
+ PM->CTRL.reg &= ~PM_CTRL_CFDEN;
+ }
+}
+#endif
+
+/**
+ * \brief Set main CPU clock divider.
+ *
+ * Sets the clock divider used on the main clock to provide the CPU clock.
+ *
+ * \param[in] divider CPU clock divider to set
+ */
+static inline void system_cpu_clock_set_divider(
+ const enum system_main_clock_div divider)
+{
+ Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+ PM->CPUSEL.reg = (uint32_t)divider;
+}
+
+/**
+ * \brief Retrieves the current frequency of the CPU core.
+ *
+ * Retrieves the operating frequency of the CPU core, obtained from the main
+ * generic clock and the set CPU bus divider.
+ *
+ * \return Current CPU frequency in Hz.
+ */
+static inline uint32_t system_cpu_clock_get_hz(void)
+{
+ return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+}
+
+/**
+ * \brief Set APBx clock divider.
+ *
+ * Set the clock divider used on the main clock to provide the clock for the
+ * given APBx bus.
+ *
+ * \param[in] divider APBx bus divider to set
+ * \param[in] bus APBx bus to set divider for
+ *
+ * \returns Status of the clock division change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
+ * \retval STATUS_OK The APBx clock was set successfully
+ */
+static inline enum status_code system_apb_clock_set_divider(
+ const enum system_clock_apb_bus bus,
+ const enum system_main_clock_div divider)
+{
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ PM->APBASEL.reg = (uint32_t)divider;
+ break;
+ case SYSTEM_CLOCK_APB_APBB:
+ PM->APBBSEL.reg = (uint32_t)divider;
+ break;
+ case SYSTEM_CLOCK_APB_APBC:
+ PM->APBCSEL.reg = (uint32_t)divider;
+ break;
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the current frequency of a ABPx.
+ *
+ * Retrieves the operating frequency of an APBx bus, obtained from the main
+ * generic clock and the set APBx bus divider.
+ *
+ * \return Current APBx bus frequency in Hz.
+ */
+static inline uint32_t system_apb_clock_get_hz(
+ const enum system_clock_apb_bus bus)
+{
+ uint16_t bus_divider = 0;
+
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ bus_divider = PM->APBASEL.reg;
+ break;
+ case SYSTEM_CLOCK_APB_APBB:
+ bus_divider = PM->APBBSEL.reg;
+ break;
+ case SYSTEM_CLOCK_APB_APBC:
+ bus_divider = PM->APBCSEL.reg;
+ break;
+ default:
+ Assert(false);
+ return 0;
+ }
+
+ return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * \name Bus clock masking
+ * @{
+ */
+
+/**
+ * \brief Set bits in the clock mask for the AHB bus.
+ *
+ * This function will set bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will enable that clock, 0 bits in the mask
+ * will be ignored
+ *
+ * \param[in] ahb_mask AHB clock mask to enable
+ */
+static inline void system_ahb_clock_set_mask(
+ const uint32_t ahb_mask)
+{
+ PM->AHBMASK.reg |= ahb_mask;
+}
+
+/**
+ * \brief Clear bits in the clock mask for the AHB bus.
+ *
+ * This function will clear bits in the clock mask for the AHB bus.
+ * Any bits set to 1 will disable that clock, 0 bits in the mask
+ * will be ignored.
+ *
+ * \param[in] ahb_mask AHB clock mask to disable
+ */
+static inline void system_ahb_clock_clear_mask(
+ const uint32_t ahb_mask)
+{
+ PM->AHBMASK.reg &= ~ahb_mask;
+}
+
+/**
+ * \brief Set bits in the clock mask for an APBx bus.
+ *
+ * This function will set bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will enable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ * the device header files
+ * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
+ * constants from the device header files
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus given
+ * \retval STATUS_OK The clock mask was set successfully
+ */
+static inline enum status_code system_apb_clock_set_mask(
+ const enum system_clock_apb_bus bus,
+ const uint32_t mask)
+{
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ PM->APBAMASK.reg |= mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBB:
+ PM->APBBMASK.reg |= mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBC:
+ PM->APBCMASK.reg |= mask;
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Clear bits in the clock mask for an APBx bus.
+ *
+ * This function will clear bits in the clock mask for an APBx bus.
+ * Any bits set to 1 will disable the corresponding module clock, zero bits in
+ * the mask will be ignored.
+ *
+ * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
+ * the device header files
+ * \param[in] bus Bus to clear clock mask bits for
+ *
+ * \returns Status indicating the result of the clock mask change operation.
+ *
+ * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given.
+ * \retval STATUS_OK The clock mask was changed successfully.
+ */
+static inline enum status_code system_apb_clock_clear_mask(
+ const enum system_clock_apb_bus bus,
+ const uint32_t mask)
+{
+ switch (bus) {
+ case SYSTEM_CLOCK_APB_APBA:
+ PM->APBAMASK.reg &= ~mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBB:
+ PM->APBBMASK.reg &= ~mask;
+ break;
+
+ case SYSTEM_CLOCK_APB_APBC:
+ PM->APBCMASK.reg &= ~mask;
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * @}
+ */
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Reference clock source of the DPLL module
+ */
+enum system_clock_source_dpll_reference_clock {
+ /** Select CLK_DPLL_REF0 as clock reference */
+ SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0,
+ /** Select CLK_DPLL_REF1 as clock reference */
+ SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1,
+ /** Select GCLK_DPLL as clock reference */
+ SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+};
+
+/**
+ * \brief Lock time-out value of the DPLL module
+ */
+enum system_clock_source_dpll_lock_time {
+ /** Set no time-out as default */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+ /** Set time-out if no lock within 8 ms */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+ /** Set time-out if no lock within 9 ms */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+ /** Set time-out if no lock within 10 ms */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+ /** Set time-out if no lock within 11 ms */
+ SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+};
+
+/**
+ * \brief Filter type of the DPLL module
+ */
+enum system_clock_source_dpll_filter {
+ /** Default filter mode */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+ /** Low bandwidth filter */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+ /** High bandwidth filter */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+ /** High damping filter */
+ SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+};
+
+/**
+ * \brief Configuration structure for DPLL
+ *
+ * DPLL oscillator configuration structure.
+ */
+struct system_clock_source_dpll_config {
+ /** Run On Demand. If this is set the DPLL won't run
+ * until requested by a peripheral */
+ bool on_demand;
+ /** Keep the DPLL enabled in standby sleep mode */
+ bool run_in_standby;
+ /** Bypass lock signal */
+ bool lock_bypass;
+ /** Wake up fast. If this is set DPLL output clock is enabled after
+ * the startup time */
+ bool wake_up_fast;
+ /** Enable low power mode */
+ bool low_power_enable;
+
+ /** Output frequency of the clock */
+ uint32_t output_frequency;
+ /** Reference frequency of the clock */
+ uint32_t reference_frequency;
+ /** Devider of reference clock */
+ uint16_t reference_divider;
+
+ /** Filter type of the DPLL module */
+ enum system_clock_source_dpll_filter filter;
+ /** Lock time-out value of the DPLL module */
+ enum system_clock_source_dpll_lock_time lock_time;
+ /** Reference clock source of the DPLL module */
+ enum system_clock_source_dpll_reference_clock reference_clock;
+};
+
+/**
+ * \name Internal DPLL management
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for DPLL
+ *
+ * Fills a configuration structure with the default configuration for a
+ * DPLL oscillator module:
+ * - Run only when requested by peripheral (on demand)
+ * - Don't run in STANDBY sleep mode
+ * - Lock bypass disabled
+ * - Fast wake up disabled
+ * - Low power mode disabled
+ * - Output frequency is 48MHz
+ * - Reference clock frequency is 32768Hz
+ * - Not divide reference clock
+ * - Select REF0 as reference clock
+ * - Set lock time to default mode
+ * - Use default filter
+ *
+ * \param[out] config Configuration structure to fill with default values
+ */
+static inline void system_clock_source_dpll_get_config_defaults(
+ struct system_clock_source_dpll_config *const config)
+{
+ config->on_demand = true;
+ config->run_in_standby = false;
+ config->lock_bypass = false;
+ config->wake_up_fast = false;
+ config->low_power_enable = false;
+
+ config->output_frequency = 48000000;
+ config->reference_frequency = 32768;
+ config->reference_divider = 1;
+ config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0;
+
+ config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+ config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+};
+
+void system_clock_source_dpll_set_config(
+ struct system_clock_source_dpll_config *const config);
+
+/* @} */
+#endif
+
+/**
+ * \name System Clock Initialization
+ * @{
+ */
+
+void system_clock_init(void);
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Flash Wait States
+ * @{
+ */
+
+/**
+ * \brief Set flash controller wait states
+ *
+ * Will set the number of wait states that are used by the onboard
+ * flash memory. The number of wait states depend on both device
+ * supply voltage and CPU speed. The required number of wait states
+ * can be found in the electrical characteristics of the device.
+ *
+ * \param[in] wait_states Number of wait states to use for internal flash
+ */
+static inline void system_flash_set_waitstates(uint8_t wait_states)
+{
+ Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+ ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+
+ NVMCTRL->CTRLB.bit.RWS = wait_states;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
+ *
+ * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>DFLL</td>
+ * <td>Digital Frequency Locked Loop</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * <tr>
+ * <td>OSC32K</td>
+ * <td>Internal 32KHz Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>OSC8M</td>
+ * <td>Internal 8MHz Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>PLL</td>
+ * <td>Phase Locked Loop</td>
+ * </tr>
+ * <tr>
+ * <td>OSC</td>
+ * <td>Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>XOSC</td>
+ * <td>External Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>XOSC32K</td>
+ * <td>External 32KHz Oscillator</td>
+ * </tr>
+ * <tr>
+ * <td>AHB</td>
+ * <td>Advanced High-performance Bus</td>
+ * </tr>
+ * <tr>
+ * <td>APB</td>
+ * <td>Advanced Peripheral Bus</td>
+ * </tr>
+ * <tr>
+ * <td>DPLL</td>
+ * <td>Digital Phase Locked Loop</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_errata Errata
+ *
+ * - This driver implements workaround for errata 10558
+ *
+ * "Several reset values of SYSCTRL.INTFLAG are wrong (BOD and DFLL)"
+ * When system_init is called it will reset these interrupts flags before they are used.
+
+ * - This driver implements experimental workaround for errata 9905
+ *
+ * "The DFLL clock must be requested before being configured otherwise a
+ * write access to a DFLL register can freeze the device."
+ * This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *
+ *
+ * \section asfdoc_sam0_system_clock_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Corrected OSC32K startup time definitions.
+ * \li Support locking of OSC32K and XOSC32K config register (default: false).
+ * \li Added DPLL support, functions added:
+ * \c system_clock_source_dpll_get_config_defaults() and
+ * \c system_clock_source_dpll_set_config().
+ * \li Moved gclk channel locking feature out of the config struct,
+ * functions added:
+ * \c system_gclk_chan_lock(),
+ * \c system_gclk_chan_is_locked(),
+ * \c system_gclk_chan_is_enabled() and
+ * \c system_gclk_gen_is_enabled().
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ * and configured to a failed/not running clock generator.</td>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false.
+ * \li Fixed system_flash_set_waitstates() failing with an assertion
+ * if an odd number of wait states provided.
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>
+ * \li Updated dfll configuration function to implement workaround for
+ * errata 9905 in the DFLL module.
+ * \li Updated \c system_clock_init() to reset interrupt flags before
+ * they are used, errata 10558.
+ * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ * frequency number.
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ * state for \c SYSTEM_CLOCK_SOURCE_OSC8M.
+ * \li Renamed the various \c system_clock_source_*_get_default_config()
+ * functions to \c system_clock_source_*_get_config_defaults() to
+ * match the remainder of ASF.
+ * \li Added OSC8M calibration constant loading from the device signature
+ * row when the oscillator is initialized.
+ * \li Updated default configuration of the XOSC32 to disable Automatic
+ * Gain Control due to silicon errata.
+ * </td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in
+ * a selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_system_clock_basic_use_case
+ * - \subpage asfdoc_sam0_system_gclk_basic_use_case
+ *
+ * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>04/2014</td>
+ * <td>Added support for SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>02/2014</td>
+ * <td>Added support for SAMR21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos. Fixed missing steps in the Basic
+ * Use Case Quick Start Guide.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CLOCK_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock.c
new file mode 100755
index 0000000000000000000000000000000000000000..281914f4706c8ab79d7e424d96ebc4c9fdd9e1a7
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock.c
@@ -0,0 +1,963 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21 Clock Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <clock.h>
+#include <conf_clocks.h>
+#include <system.h>
+
+#ifndef SYSCTRL_FUSES_OSC32K_ADDR
+# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
+# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos
+#endif
+
+/**
+ * \internal
+ * \brief DFLL-specific data container
+ */
+struct _system_clock_dfll_config {
+ uint32_t control;
+ uint32_t val;
+ uint32_t mul;
+};
+
+/**
+ * \internal
+ * \brief DPLL-specific data container
+ */
+struct _system_clock_dpll_config {
+ uint32_t frequency;
+};
+
+
+/**
+ * \internal
+ * \brief XOSC-specific data container
+ */
+struct _system_clock_xosc_config {
+ uint32_t frequency;
+};
+
+/**
+ * \internal
+ * \brief System clock module data container
+ */
+struct _system_clock_module {
+ volatile struct _system_clock_dfll_config dfll;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ volatile struct _system_clock_dpll_config dpll;
+#endif
+
+ volatile struct _system_clock_xosc_config xosc;
+ volatile struct _system_clock_xosc_config xosc32k;
+};
+
+/**
+ * \internal
+ * \brief Internal module instance to cache configuration values
+ */
+static struct _system_clock_module _system_clock_inst = {
+ .dfll = {
+ .control = 0,
+ .val = 0,
+ .mul = 0,
+ },
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ .dpll = {
+ .frequency = 0,
+ },
+#endif
+ .xosc = {
+ .frequency = 0,
+ },
+ .xosc32k = {
+ .frequency = 0,
+ },
+ };
+
+/**
+ * \internal
+ * \brief Wait for sync to the DFLL control registers
+ */
+static inline void _system_dfll_wait_for_sync(void)
+{
+ while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
+ /* Wait for DFLL sync */
+ }
+}
+
+/**
+ * \internal
+ * \brief Wait for sync to the OSC32K control registers
+ */
+static inline void _system_osc32k_wait_for_sync(void)
+{
+ while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
+ /* Wait for OSC32K sync */
+ }
+}
+
+static inline void _system_clock_source_dfll_set_config_errata_9905(void)
+{
+
+ /* Disable ONDEMAND mode while writing configurations */
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;
+ _system_dfll_wait_for_sync();
+
+ SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+ SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+
+ /* Write full configuration to DFLL control register */
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+}
+
+/**
+ * \brief Retrieve the frequency of a clock source
+ *
+ * Determines the current operating frequency of a given clock source.
+ *
+ * \param[in] clock_source Clock source to get the frequency of
+ *
+ * \returns Frequency of the given clock source, in Hz
+ */
+uint32_t system_clock_source_get_hz(
+ const enum system_clock_source clock_source)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ return _system_clock_inst.xosc.frequency;
+
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ return 32768UL;
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ return 32768UL;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ return _system_clock_inst.xosc32k.frequency;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+
+ /* Check if the DFLL has been configured */
+ if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+ return 0;
+
+ /* Make sure that the DFLL module is ready */
+ _system_dfll_wait_for_sync();
+
+ /* Check if operating in closed loop mode */
+ if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
+ return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+ (_system_clock_inst.dfll.mul & 0xffff);
+ }
+
+ return 48000000UL;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
+ return 0;
+ }
+
+ return _system_clock_inst.dpll.frequency;
+#endif
+
+ default:
+ return 0;
+ }
+}
+
+/**
+ * \brief Configure the internal OSC8M oscillator clock source
+ *
+ * Configures the 8MHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config OSC8M configuration structure containing the new config
+ */
+void system_clock_source_osc8m_set_config(
+ struct system_clock_source_osc8m_config *const config)
+{
+ SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+
+ /* Use temporary struct to reduce register access */
+ temp.bit.PRESC = config->prescaler;
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+
+ SYSCTRL->OSC8M = temp;
+}
+
+/**
+ * \brief Configure the internal OSC32K oscillator clock source
+ *
+ * Configures the 32KHz (nominal) internal RC oscillator with the given
+ * configuration settings.
+ *
+ * \param[in] config OSC32K configuration structure containing the new config
+ */
+void system_clock_source_osc32k_set_config(
+ struct system_clock_source_osc32k_config *const config)
+{
+ SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+
+ /* Update settings via a temporary struct to reduce register access */
+ temp.bit.EN1K = config->enable_1khz_output;
+ temp.bit.EN32K = config->enable_32khz_output;
+ temp.bit.STARTUP = config->startup_time;
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+ temp.bit.WRTLOCK = config->write_once;
+
+ SYSCTRL->OSC32K = temp;
+}
+
+/**
+ * \brief Configure the external oscillator clock source
+ *
+ * Configures the external oscillator clock source with the given configuration
+ * settings.
+ *
+ * \param[in] config External oscillator configuration structure containing
+ * the new config
+ */
+void system_clock_source_xosc_set_config(
+ struct system_clock_source_xosc_config *const config)
+{
+ SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+ temp.bit.STARTUP = config->startup_time;
+
+ if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+ temp.bit.XTALEN = 1;
+ } else {
+ temp.bit.XTALEN = 0;
+ }
+
+ temp.bit.AMPGC = config->auto_gain_control;
+
+ /* Set gain if automatic gain control is not selected */
+ if (!config->auto_gain_control) {
+ if (config->frequency <= 2000000) {
+ temp.bit.GAIN = 0;
+ } else if (config->frequency <= 4000000) {
+ temp.bit.GAIN = 1;
+ } else if (config->frequency <= 8000000) {
+ temp.bit.GAIN = 2;
+ } else if (config->frequency <= 16000000) {
+ temp.bit.GAIN = 3;
+ } else if (config->frequency <= 30000000) {
+ temp.bit.GAIN = 4;
+ }
+
+ }
+
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+
+ /* Store XOSC frequency for internal use */
+ _system_clock_inst.xosc.frequency = config->frequency;
+
+ SYSCTRL->XOSC = temp;
+}
+
+/**
+ * \brief Configure the XOSC32K external 32KHz oscillator clock source
+ *
+ * Configures the external 32KHz oscillator clock source with the given
+ * configuration settings.
+ *
+ * \param[in] config XOSC32K configuration structure containing the new config
+ */
+void system_clock_source_xosc32k_set_config(
+ struct system_clock_source_xosc32k_config *const config)
+{
+ SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+
+ temp.bit.STARTUP = config->startup_time;
+
+ if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
+ temp.bit.XTALEN = 1;
+ } else {
+ temp.bit.XTALEN = 0;
+ }
+
+ temp.bit.AAMPEN = config->auto_gain_control;
+ temp.bit.EN1K = config->enable_1khz_output;
+ temp.bit.EN32K = config->enable_32khz_output;
+
+ temp.bit.ONDEMAND = config->on_demand;
+ temp.bit.RUNSTDBY = config->run_in_standby;
+ temp.bit.WRTLOCK = config->write_once;
+
+ /* Cache the new frequency in case the user needs to check the current
+ * operating frequency later */
+ _system_clock_inst.xosc32k.frequency = config->frequency;
+
+ SYSCTRL->XOSC32K = temp;
+}
+
+/**
+ * \brief Configure the DFLL clock source
+ *
+ * Configures the Digital Frequency Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DFLL will be running when this function returns, as the DFLL module
+ * needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config DFLL configuration structure containing the new config
+ */
+void system_clock_source_dfll_set_config(
+ struct system_clock_source_dfll_config *const config)
+{
+ _system_clock_inst.dfll.val =
+ SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
+ SYSCTRL_DFLLVAL_FINE(config->fine_value);
+
+ _system_clock_inst.dfll.control =
+ (uint32_t)config->wakeup_lock |
+ (uint32_t)config->stable_tracking |
+ (uint32_t)config->quick_lock |
+ (uint32_t)config->chill_cycle |
+ ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+ if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+
+ _system_clock_inst.dfll.mul =
+ SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+ SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) |
+ SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+ /* Enable the closed loop mode */
+ _system_clock_inst.dfll.control |= config->loop_mode;
+ }
+ if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+
+ _system_clock_inst.dfll.mul =
+ SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+ /* Enable the USB recovery mode */
+ _system_clock_inst.dfll.control |= config->loop_mode |
+ SYSCTRL_DFLLCTRL_BPLCKC;
+ }
+}
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+/**
+ * \brief Configure the DPLL clock source
+ *
+ * Configures the Digital Phase-Locked Loop clock source with the given
+ * configuration settings.
+ *
+ * \note The DPLL will be running when this function returns, as the DPLL module
+ * needs to be enabled in order to perform the module configuration.
+ *
+ * \param[in] config DPLL configuration structure containing the new config
+ */
+void system_clock_source_dpll_set_config(
+ struct system_clock_source_dpll_config *const config)
+{
+
+ uint32_t tmpldr;
+ uint8_t tmpldrfrac;
+ uint32_t refclk;
+
+ refclk = config->reference_frequency;
+
+ /* Only reference clock REF1 can be divided */
+ if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) {
+ refclk = refclk / config->reference_divider;
+ }
+
+ /* Calculate LDRFRAC and LDR */
+ tmpldr = (config->output_frequency << 4) / refclk;
+ tmpldrfrac = tmpldr & 0x0f;
+ tmpldr = (tmpldr >> 4) - 1;
+
+ SYSCTRL->DPLLCTRLA.reg =
+ ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
+ ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
+
+ SYSCTRL->DPLLRATIO.reg =
+ SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
+ SYSCTRL_DPLLRATIO_LDR(tmpldr);
+
+ SYSCTRL->DPLLCTRLB.reg =
+ SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
+ ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
+ SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
+ SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
+ ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
+ ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
+ SYSCTRL_DPLLCTRLB_FILTER(config->filter);
+
+ /*
+ * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
+ */
+ _system_clock_inst.dpll.frequency =
+ (config->reference_frequency *
+ (((tmpldr + 1) << 4) + tmpldrfrac)
+ ) >> 4;
+}
+#endif
+
+/**
+ * \brief Writes the calibration values for a given oscillator clock source
+ *
+ * Writes an oscillator calibration value to the given oscillator control
+ * registers. The acceptable ranges are:
+ *
+ * For OSC32K:
+ * - 7 bits (max value 128)
+ * For OSC8MHZ:
+ * - 8 bits (Max value 255)
+ * For OSCULP:
+ * - 5 bits (Max value 32)
+ *
+ * \note The frequency range parameter applies only when configuring the 8MHz
+ * oscillator and will be ignored for the other oscillators.
+ *
+ * \param[in] clock_source Clock source to calibrate
+ * \param[in] calibration_value Calibration value to write
+ * \param[in] freq_range Frequency range (8MHz oscillator only)
+ *
+ * \retval STATUS_OK The calibration value was written
+ * successfully.
+ * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock
+ * source.
+ */
+enum status_code system_clock_source_write_calibration(
+ const enum system_clock_source clock_source,
+ const uint16_t calibration_value,
+ const uint8_t freq_range)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+
+ if (calibration_value > 0xfff || freq_range > 4) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ SYSCTRL->OSC8M.bit.CALIB = calibration_value;
+ SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+
+ if (calibration_value > 128) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ _system_osc32k_wait_for_sync();
+ SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+
+ if (calibration_value > 32) {
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+ break;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ break;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables a clock source
+ *
+ * Enables a clock source which has been previously configured.
+ *
+ * \param[in] clock_source Clock source to enable
+ *
+ * \retval STATUS_OK Clock source was enabled successfully and
+ * is ready
+ * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this
+ * device
+ */
+enum status_code system_clock_source_enable(
+ const enum system_clock_source clock_source)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+ return STATUS_OK;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+ _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+ _system_clock_source_dfll_set_config_errata_9905();
+ break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+ break;
+#endif
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ /* Always enabled */
+ return STATUS_OK;
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables a clock source
+ *
+ * Disables a clock source that was previously enabled.
+ *
+ * \param[in] clock_source Clock source to disable
+ *
+ * \retval STATUS_OK Clock source was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was
+ * given
+ */
+enum status_code system_clock_source_disable(
+ const enum system_clock_source clock_source)
+{
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+ _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+ SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+ break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+ break;
+#endif
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ /* Not possible to disable */
+
+ default:
+ Assert(false);
+ return STATUS_ERR_INVALID_ARG;
+
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Checks if a clock source is ready
+ *
+ * Checks if a given clock source is ready to be used.
+ *
+ * \param[in] clock_source Clock source to check if ready
+ *
+ * \returns Ready state of the given clock source.
+ *
+ * \retval true Clock source is enabled and ready
+ * \retval false Clock source is disabled or not yet ready
+ */
+bool system_clock_source_is_ready(
+ const enum system_clock_source clock_source)
+{
+ uint32_t mask = 0;
+
+ switch (clock_source) {
+ case SYSTEM_CLOCK_SOURCE_OSC8M:
+ mask = SYSCTRL_PCLKSR_OSC8MRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_OSC32K:
+ mask = SYSCTRL_PCLKSR_OSC32KRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC:
+ mask = SYSCTRL_PCLKSR_XOSCRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_XOSC32K:
+ mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+ break;
+
+ case SYSTEM_CLOCK_SOURCE_DFLL:
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+ mask = (SYSCTRL_PCLKSR_DFLLRDY |
+ SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+ } else {
+ mask = SYSCTRL_PCLKSR_DFLLRDY;
+ }
+ break;
+
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+ case SYSTEM_CLOCK_SOURCE_DPLL:
+ return ((SYSCTRL->DPLLSTATUS.reg &
+ (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
+ (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
+#endif
+
+ case SYSTEM_CLOCK_SOURCE_ULP32K:
+ /* Not possible to disable */
+ return true;
+
+ default:
+ return false;
+ }
+
+ return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+}
+
+/* Include some checks for conf_clocks.h validation */
+#include "clock_config_check.h"
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
+ */
+# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
+ if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
+ struct system_gclk_gen_config gclk_conf; \
+ system_gclk_gen_get_config_defaults(&gclk_conf); \
+ gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \
+ gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \
+ gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+ gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \
+ system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \
+ system_gclk_gen_enable(GCLK_GENERATOR_##n); \
+ }
+
+/** \internal
+ *
+ * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
+ * provided that it is not the main Generic Clock Generator channel.
+ */
+# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
+ if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+#endif
+
+/**
+ * \brief Initialize clock system based on the configuration in conf_clocks.h
+ *
+ * This function will apply the settings in conf_clocks.h when run from the user
+ * application. All clock sources and GCLK generators are running when this function
+ * returns.
+ */
+void system_clock_init(void)
+{
+ /* Various bits in the INTFLAG register can be set to one at startup.
+ This will ensure that these bits are cleared */
+ SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+ SYSCTRL_INTFLAG_DFLLRDY;
+
+ system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+
+ /* XOSC */
+#if CONF_CLOCK_XOSC_ENABLE == true
+ struct system_clock_source_xosc_config xosc_conf;
+ system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+ xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+ xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME;
+ xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
+ xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+ xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND;
+ xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+ system_clock_source_xosc_set_config(&xosc_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+#endif
+
+
+ /* XOSC32K */
+#if CONF_CLOCK_XOSC32K_ENABLE == true
+ struct system_clock_source_xosc32k_config xosc32k_conf;
+ system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+ xosc32k_conf.frequency = 32768UL;
+ xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+ xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+ xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+ xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+ xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+ xosc32k_conf.on_demand = false;
+ xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+ system_clock_source_xosc32k_set_config(&xosc32k_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+ while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+ if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
+ SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+ }
+#endif
+
+
+ /* OSCK32K */
+#if CONF_CLOCK_OSC32K_ENABLE == true
+ SYSCTRL->OSC32K.bit.CALIB =
+ (*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos);
+
+ struct system_clock_source_osc32k_config osc32k_conf;
+ system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+
+ osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME;
+ osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+ osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+ osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND;
+ osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+
+ system_clock_source_osc32k_set_config(&osc32k_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+#endif
+
+
+ /* DFLL Config (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+ struct system_clock_source_dfll_config dfll_conf;
+ system_clock_source_dfll_get_config_defaults(&dfll_conf);
+
+ dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE;
+ dfll_conf.on_demand = false;
+
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
+ dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE;
+ dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE;
+ }
+
+# if CONF_CLOCK_DFLL_QUICK_LOCK == true
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+# else
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+# endif
+
+# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+# else
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+# endif
+
+# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+# else
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+# endif
+
+# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+# else
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+# endif
+
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+ dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+ }
+
+ dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+ dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
+#define NVM_DFLL_COARSE_POS 58
+#define NVM_DFLL_COARSE_SIZE 6
+#define NVM_DFLL_FINE_POS 64
+#define NVM_DFLL_FINE_SIZE 10
+ uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_DFLL_COARSE_POS / 32))
+ >> (NVM_DFLL_COARSE_POS % 32))
+ & ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+ if (coarse == 0x3f) {
+ coarse = 0x1f;
+ }
+ uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_DFLL_FINE_POS / 32))
+ >> (NVM_DFLL_FINE_POS % 32))
+ & ((1 << NVM_DFLL_FINE_SIZE) - 1);
+ if (fine == 0x3ff) {
+ fine = 0x1ff;
+ }
+ dfll_conf.coarse_value = coarse;
+ dfll_conf.fine_value = fine;
+
+ dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+ dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+ dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+ dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+
+ dfll_conf.multiply_factor = 48000;
+ }
+
+ system_clock_source_dfll_set_config(&dfll_conf);
+#endif
+
+
+ /* OSC8M */
+ struct system_clock_source_osc8m_config osc8m_conf;
+ system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+
+ osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER;
+ osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND;
+ osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+
+ system_clock_source_osc8m_set_config(&osc8m_conf);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+
+
+ /* GCLK */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+ system_gclk_init();
+
+ /* Configure all GCLK generators except for the main generator, which
+ * is configured later after all other clock systems are set up */
+ MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+
+# if CONF_CLOCK_DFLL_ENABLE == true
+ /* Enable DFLL reference clock if in closed loop mode */
+ if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
+ struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+ system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+ dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+ system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+ system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+ }
+# endif
+#endif
+
+
+ /* DFLL Enable (Open and Closed Loop) */
+#if CONF_CLOCK_DFLL_ENABLE == true
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+ while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+ if (CONF_CLOCK_DFLL_ON_DEMAND) {
+ SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+ }
+#endif
+
+ /* DPLL */
+#ifdef FEATURE_SYSTEM_CLOCK_DPLL
+# if (CONF_CLOCK_DPLL_ENABLE == true)
+
+ /* Enable DPLL reference clock */
+ if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) {
+ /* XOSC32K should have been enabled for DPLL_REF0 */
+ Assert(CONF_CLOCK_XOSC32K_ENABLE);
+ }
+
+ struct system_clock_source_dpll_config dpll_config;
+ system_clock_source_dpll_get_config_defaults(&dpll_config);
+
+ dpll_config.on_demand = false;
+ dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
+ dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS;
+ dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST;
+ dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
+
+ dpll_config.filter = CONF_CLOCK_DPLL_FILTER;
+
+ dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
+ dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
+ dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER;
+ dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
+
+ system_clock_source_dpll_set_config(&dpll_config);
+ system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
+ while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
+ if (CONF_CLOCK_DPLL_ON_DEMAND) {
+ SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
+ }
+
+# endif
+#endif
+
+ /* CPU and BUS clocks */
+ system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+
+#ifdef FEATURE_SYSTEM_CLOCK_FAILURE_DETECT
+ system_main_clock_set_failure_detect(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT);
+#endif
+
+ system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+ system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+
+ /* GCLK 0 */
+#if CONF_CLOCK_CONFIGURE_GCLK == true
+ /* Configure the main GCLK last as it might depend on other generators */
+ _CONF_CLOCK_GCLK_CONFIG(0, ~);
+#endif
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock_config_check.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock_config_check.h
new file mode 100755
index 0000000000000000000000000000000000000000..045ef6437c25c6eb26cf79ec89ae87c1f5524bdf
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock_config_check.h
@@ -0,0 +1,423 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21 Clock Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef CLOCK_CONFIG_CHECK_H
+# define CLOCK_CONFIG_CHECK_H
+
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
+# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_CPU_DIVIDER)
+# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_APBA_DIVIDER)
+# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_APBB_DIVIDER)
+# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
+# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
+# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
+# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ENABLE)
+# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
+# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
+# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
+# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
+# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
+# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
+# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
+# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
+# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
+# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
+# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
+# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
+# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
+# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
+# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)
+# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
+# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
+# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
+# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
+# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
+# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE)
+# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
+# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
+# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_COARSE_VALUE)
+# error CONF_CLOCK_DFLL_COARSE_VALUE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
+# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
+# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
+# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
+# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
+# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
+# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
+# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
+# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
+# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ENABLE)
+# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
+# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
+# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
+# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
+# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
+# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
+# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
+# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_FILTER)
+# error CONF_CLOCK_DPLL_FILTER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
+# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFEREMCE_DIVIDER)
+# error CONF_CLOCK_DPLL_REFEREMCE_DIVIDER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
+# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
+# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
+# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
+# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
+# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
+# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
+# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
+# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
+# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
+# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
+# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
+# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
+# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
+# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
+# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
+# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
+# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
+# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
+# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
+# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clock.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
+# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clock.h
+#endif
+
+#endif /* CLOCK_CONFIG_CHECK_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/gclk.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/gclk.c
new file mode 100755
index 0000000000000000000000000000000000000000..3816ff7b8b8ef1997425b231f24d78b120e46a19
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/gclk.c
@@ -0,0 +1,496 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21 Generic Clock Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+ /* Software reset the module to ensure it is re-initialized correctly */
+ GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+ while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+ /* Wait for reset to complete */
+ }
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ * generator) can take additional time if the clock source is configured
+ * to only run on-demand (ONDEMAND bit is set) and it is not currently
+ * running (no peripheral is requesting the clock source). In this case
+ * the GCLK will request the new clock while still keeping a request to
+ * the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ * to start the generator, call \ref system_gclk_gen_enable()
+ * after configuring a generator.
+ *
+ * \param[in] generator Generic Clock Generator index to configure
+ * \param[in] config Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+ const uint8_t generator,
+ struct system_gclk_gen_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Cache new register configurations to minimize sync requirements. */
+ uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+ uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);
+
+ /* Select the requested source clock for the generator */
+ new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+ /* Configure the clock to be either high or low when disabled */
+ if (config->high_when_disabled) {
+ new_genctrl_config |= GCLK_GENCTRL_OOV;
+ }
+
+ /* Configure if the clock output to I/O pin should be enabled. */
+ if (config->output_enable) {
+ new_genctrl_config |= GCLK_GENCTRL_OE;
+ }
+
+ /* Set division factor */
+ if (config->division_factor > 1) {
+ /* Check if division is a power of two */
+ if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+ /* Determine the index of the highest bit set to get the
+ * division factor that must be loaded into the division
+ * register */
+
+ uint32_t div2_count = 0;
+
+ uint32_t mask;
+ for (mask = (1UL << 1); mask < config->division_factor;
+ mask <<= 1) {
+ div2_count++;
+ }
+
+ /* Set binary divider power of 2 division factor */
+ new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;
+ new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+ } else {
+ /* Set integer division factor */
+
+ new_gendiv_config |=
+ (config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+ /* Enable non-binary division with increased duty cycle accuracy */
+ new_genctrl_config |= GCLK_GENCTRL_IDC;
+ }
+
+ }
+
+ /* Enable or disable the clock in standby mode */
+ if (config->run_in_standby) {
+ new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+ }
+
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the correct generator */
+ *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+ /* Write the new generator configuration */
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+ GCLK->GENDIV.reg = new_gendiv_config;
+
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+ GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+ const uint8_t generator)
+{
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ /* Enable generator */
+ GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+ const uint8_t generator)
+{
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ /* Disable generator */
+ GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+ while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
+ /* Wait for clock to become disabled */
+ }
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled
+ *
+ * \param[in] generator Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled;
+ * \retval false The Generic Clock Generator is disabled.
+ */
+bool system_gclk_gen_is_enabled(
+ const uint8_t generator)
+{
+ bool enabled;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ /* Obtain the enabled status */
+ enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+ system_interrupt_leave_critical_section();
+
+ return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+ const uint8_t generator)
+{
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the appropriate generator */
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ /* Get the frequency of the source connected to the GCLK generator */
+ uint32_t gen_input_hz = system_clock_source_get_hz(
+ (enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+
+ *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+
+ uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+
+ /* Select the appropriate generator division register */
+ *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+ while (system_gclk_is_syncing()) {
+ /* Wait for synchronization */
+ };
+
+ uint32_t divider = GCLK->GENDIV.bit.DIV;
+
+ system_interrupt_leave_critical_section();
+
+ /* Check if the generator is using fractional or binary division */
+ if (!divsel && divider > 1) {
+ gen_input_hz /= divider;
+ } else if (divsel) {
+ gen_input_hz >>= (divider+1);
+ }
+
+ return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ * call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel Generic Clock channel to configure
+ * \param[in] config Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+ const uint8_t channel,
+ struct system_gclk_chan_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Cache the new config to reduce sync requirements */
+ uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+
+ /* Select the desired generic clock generator */
+ new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+
+ /* Disable generic clock channel */
+ system_gclk_chan_disable(channel);
+
+ /* Write the new configuration */
+ GCLK->CLKCTRL.reg = new_clkctrl_config;
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+ const uint8_t channel)
+{
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+ /* Enable the generic clock */
+ GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+ const uint8_t channel)
+{
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+ /* Sanity check WRTLOCK */
+ Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+ /* Switch to known-working source so that the channel can be disabled */
+ uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+ GCLK->CLKCTRL.bit.GEN = 0;
+
+ /* Disable the generic clock */
+ GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+ while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+ /* Wait for clock to become disabled */
+ }
+
+ /* Restore previous configured clock generator */
+ GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled
+ *
+ * \param[in] channel Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled;
+ * \retval false The Generic Clock channel is disabled.
+ */
+bool system_gclk_chan_is_enabled(
+ const uint8_t channel)
+{
+ bool enabled;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generic clock channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+ enabled = GCLK->CLKCTRL.bit.CLKEN;
+
+ system_interrupt_leave_critical_section();
+
+ return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+ const uint8_t channel)
+{
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generator channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+ /* Enable the generic clock */
+ GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+ system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked
+ *
+ * \param[in] channel Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked;
+ * \retval false The Generic Clock channel is not locked.
+ */
+bool system_gclk_chan_is_locked(
+ const uint8_t channel)
+{
+ bool locked;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generic clock channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+ locked = GCLK->CLKCTRL.bit.WRTLOCK;
+
+ system_interrupt_leave_critical_section();
+
+ return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+ const uint8_t channel)
+{
+ uint8_t gen_id;
+
+ system_interrupt_enter_critical_section();
+
+ /* Select the requested generic clock channel */
+ *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+ gen_id = GCLK->CLKCTRL.bit.GEN;
+
+ system_interrupt_leave_critical_section();
+
+ /* Return the clock speed of the associated GCLK generator */
+ return system_gclk_gen_get_hz(gen_id);
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/gclk.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/gclk.h
new file mode 100755
index 0000000000000000000000000000000000000000..f427132eea5c4cdc2389c6820779b041b0671d91
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/gclk.h
@@ -0,0 +1,322 @@
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_system_clock_group
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief List of available GCLK generators.
+ *
+ * List of Available GCLK generators. This enum is used in the peripheral
+ * device drivers to select the GCLK generator to be used for its operation.
+ *
+ * The number of GCLK generators available is device dependent.
+ */
+enum gclk_generator {
+ /** GCLK generator channel 0. */
+ GCLK_GENERATOR_0,
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
+ /** GCLK generator channel 1. */
+ GCLK_GENERATOR_1,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
+ /** GCLK generator channel 2. */
+ GCLK_GENERATOR_2,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
+ /** GCLK generator channel 3. */
+ GCLK_GENERATOR_3,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
+ /** GCLK generator channel 4. */
+ GCLK_GENERATOR_4,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
+ /** GCLK generator channel 5. */
+ GCLK_GENERATOR_5,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
+ /** GCLK generator channel 6. */
+ GCLK_GENERATOR_6,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
+ /** GCLK generator channel 7. */
+ GCLK_GENERATOR_7,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
+ /** GCLK generator channel 8. */
+ GCLK_GENERATOR_8,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
+ /** GCLK generator channel 9. */
+ GCLK_GENERATOR_9,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
+ /** GCLK generator channel 10. */
+ GCLK_GENERATOR_10,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
+ /** GCLK generator channel 11. */
+ GCLK_GENERATOR_11,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
+ /** GCLK generator channel 12. */
+ GCLK_GENERATOR_12,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
+ /** GCLK generator channel 13. */
+ GCLK_GENERATOR_13,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
+ /** GCLK generator channel 14. */
+ GCLK_GENERATOR_14,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
+ /** GCLK generator channel 15. */
+ GCLK_GENERATOR_15,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
+ /** GCLK generator channel 16. */
+ GCLK_GENERATOR_16,
+#endif
+};
+
+/**
+ * \brief Generic Clock Generator configuration structure.
+ *
+ * Configuration structure for a Generic Clock Generator channel. This
+ * structure should be initialized by the
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_gclk_gen_config {
+ /** Source clock input channel index, please see the \ref system_clock_source. */
+ uint8_t source_clock;
+ /** If \c true, the generator output level is high when disabled. */
+ bool high_when_disabled;
+ /** Integer division factor of the clock output compared to the input. */
+ uint32_t division_factor;
+ /** If \c true, the clock is kept enabled during device standby mode. */
+ bool run_in_standby;
+ /** If \c true, enables GCLK generator clock output to a GPIO pin. */
+ bool output_enable;
+};
+
+/**
+ * \brief Generic Clock configuration structure.
+ *
+ * Configuration structure for a Generic Clock channel. This structure
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct system_gclk_chan_config {
+ /** Generic Clock Generator source channel. */
+ enum gclk_generator source_generator;
+};
+
+/** \name Generic Clock management
+ * @{
+ */
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module has completed synchronization
+ * \retval false if the module synchronization is ongoing
+ */
+static inline bool system_gclk_is_syncing(void)
+{
+ if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {
+ return true;
+ }
+
+ return false;
+}
+
+void system_gclk_init(void);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock management (Generators)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock Generator configuration structure to
+ * a set of known default values. This function should be called on all
+ * new instances of these configuration structures before being modified
+ * by the user application.
+ *
+ * The default configuration is as follows:
+ * \li Clock is generated undivided from the source frequency
+ * \li Clock generator output is low when the generator is disabled
+ * \li The input clock is sourced from input clock channel 0
+ * \li Clock will be disabled during sleep
+ * \li The clock output will not be routed to a physical GPIO pin
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void system_gclk_gen_get_config_defaults(
+ struct system_gclk_gen_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->division_factor = 1;
+ config->high_when_disabled = false;
+ config->source_clock = GCLK_SOURCE_OSC8M;
+ config->run_in_standby = false;
+ config->output_enable = false;
+}
+
+void system_gclk_gen_set_config(
+ const uint8_t generator,
+ struct system_gclk_gen_config *const config);
+
+void system_gclk_gen_enable(
+ const uint8_t generator);
+
+void system_gclk_gen_disable(
+ const uint8_t generator);
+
+bool system_gclk_gen_is_enabled(
+ const uint8_t generator);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock management (Channels)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Clock is sourced from the Generic Clock Generator channel 0
+ * \li Clock configuration will not be write-locked when set
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void system_gclk_chan_get_config_defaults(
+ struct system_gclk_chan_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->source_generator = GCLK_GENERATOR_0;
+}
+
+void system_gclk_chan_set_config(
+ const uint8_t channel,
+ struct system_gclk_chan_config *const config);
+
+void system_gclk_chan_enable(
+ const uint8_t channel);
+
+void system_gclk_chan_disable(
+ const uint8_t channel);
+
+bool system_gclk_chan_is_enabled(
+ const uint8_t channel);
+
+void system_gclk_chan_lock(
+ const uint8_t channel);
+
+bool system_gclk_chan_is_locked(
+ const uint8_t channel);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock frequency retrieval
+ * @{
+ */
+
+uint32_t system_gclk_gen_get_hz(
+ const uint8_t generator);
+
+uint32_t system_gclk_chan_get_hz(
+ const uint8_t channel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h
new file mode 100755
index 0000000000000000000000000000000000000000..46d7600d460fbbba3472c26ea397416d16c3fe84
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h
@@ -0,0 +1,129 @@
+/**
+ * \file
+ *
+ * \brief SAM System Clock Driver Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ */
+
+/**
+ * \page asfdoc_sam0_system_clock_basic_use_case Quick Start Guide for SYSTEM CLOCK - Basic
+ *
+ * In this case we apply the following configuration:
+ * - RC8MHz (internal 8MHz RC oscillator)
+ * - Divide by 4, giving a frequency of 2MHz
+ * - DFLL (Digital frequency locked loop)
+ * - Open loop mode
+ * - 48MHz frequency
+ * - CPU clock
+ * - Use two wait states when reading from flash memory
+ * - Use the DFLL, configured to 48MHz
+ *
+ * \section asfdoc_sam0_system_clock_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_clock_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_system_clock_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your application:
+ * \snippet qs_clock_source.c setup
+ *
+ * \subsection asfdoc_sam0_system_clock_basic_use_case_setup_flow Workflow
+ * -# Create a EXTOSC32K module configuration struct, which can be filled
+ * out to adjust the configuration of the external 32KHz oscillator channel.
+ * \snippet qs_clock_source.c config_extosc32k_config
+ *
+ * -# Initialize the oscillator configuration struct with the module's default
+ * values.
+ * \snippet qs_clock_source.c config_extosc32k_get_defaults
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Alter the EXTOSC32K module configuration struct to require a start-up time
+ * of 4096 clock cycles.
+ * \snippet qs_clock_source.c config_extosc32k_change_defaults
+ *
+ * -# Write the new configuration to the EXTOSC32K module.
+ * \snippet qs_clock_source.c config_extosc32k_set_config
+ *
+ * -# Create a DFLL module configuration struct, which can be filled
+ * out to adjust the configuration of the external 32KHz oscillator channel.
+ * \snippet qs_clock_source.c config_dfll_config
+ *
+ * -# Initialize the DFLL oscillator configuration struct with the module's
+ * default values.
+ * \snippet qs_clock_source.c config_dfll_get_defaults
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Write the new configuration to the DFLL module.
+ * \snippet qs_clock_source.c config_dfll_set_config
+ *
+ *
+ * \section asfdoc_sam0_system_clock_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_clock_basic_use_case_code Code
+ *
+ * Copy-paste the following code to your user application:
+ * \snippet qs_clock_source.c main
+ *
+ * \subsection asfdoc_sam0_system_clock_basic_use_case_flow Workflow
+ * -# Configure the external 32KHz oscillator source using the previously
+ * defined setup function.
+ * \snippet qs_clock_source.c config_extosc32k_main
+ *
+ * -# Enable the configured external 32KHz oscillator source.
+ * \snippet qs_clock_source.c enable_extosc32k_main
+ *
+ * -# Configure the DFLL oscillator source using the previously defined setup
+ * function.
+ * \snippet qs_clock_source.c config_dfll_main
+ *
+ * -# Enable the configured DFLL oscillator source.
+ * \snippet qs_clock_source.c enable_dfll_main
+ *
+ * -# Configure the flash wait states to have two wait states per read, as the
+ * high speed DFLL will be used as the system clock. If insufficient wait
+ * states are used, the device may crash randomly due to misread instructions.
+ * \snippet qs_clock_source.c set_sys_wait_states
+ *
+ * -# Switch the system clock source to the DFLL, by reconfiguring the main
+ * clock generator.
+ * \snippet qs_clock_source.c set_sys_clk_src
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h
new file mode 100755
index 0000000000000000000000000000000000000000..274a51973ff343e366bbaffe7b326657c66171ca
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h
@@ -0,0 +1,126 @@
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_system_gclk_basic_use_case Quick Start Guide for SYSTEM CLOCK - GCLK Configuration
+ *
+ * In this use case, the GCLK module is configured for:
+ * \li One generator attached to the internal 8MHz RC oscillator clock source
+ * \li Generator output equal to input frequency divided by a factor of 128
+ * \li One channel (connected to the TC0 module) enabled with the enabled generator selected
+ *
+ * This use case configures a clock channel to output a clock for a peripheral
+ * within the device, by first setting up a clock generator from a master clock
+ * source, and then linking the generator to the desired channel. This clock
+ * can then be used to clock a module within the device.
+ *
+ * \section asfdoc_sam0_system_gclk_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_gclk_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_system_gclk_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_gclk_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_gclk_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_system_gclk_basic_use_case_setup_flow Workflow
+ * -# Create a GCLK generator configuration struct, which can be filled out to
+ * adjust the configuration of a single clock generator.
+ * \snippet qs_gclk_basic.c setup_1
+ * -# Initialize the generator configuration struct with the module's default
+ * values.
+ * \snippet qs_gclk_basic.c setup_2
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Adjust the configuration struct to request that the master clock source
+ * channel 0 be used as the source of the generator, and set the generator
+ * output prescaler to divide the input clock by a factor of 128.
+ * \snippet qs_gclk_basic.c setup_3
+ * -# Configure the generator using the configuration structure.
+ * \snippet qs_gclk_basic.c setup_4
+ * \note The existing configuration struct may be re-used, as long as any
+ * values that have been altered from the default settings are taken
+ * into account by the user application.
+ *
+ * -# Enable the generator once it has been properly configured, to begin clock
+ * generation.
+ * \snippet qs_gclk_basic.c setup_5
+ *
+ * -# Create a GCLK channel configuration struct, which can be filled out to
+ * adjust the configuration of a single generic clock channel.
+ * \snippet qs_gclk_basic.c setup_6
+ * -# Initialize the channel configuration struct with the module's default
+ * values.
+ * \snippet qs_gclk_basic.c setup_7
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Adjust the configuration struct to request that the previously configured
+ * and enabled clock generator be used as the clock source for the channel.
+ * \snippet qs_gclk_basic.c setup_8
+ * -# Configure the channel using the configuration structure.
+ * \snippet qs_gclk_basic.c setup_9
+ * \note The existing configuration struct may be re-used, as long as any
+ * values that have been altered from the default settings are taken
+ * into account by the user application.
+ *
+ * -# Enable the channel once it has been properly configured, to output the
+ * clock to the channel's peripheral module consumers.
+ * \snippet qs_gclk_basic.c setup_10
+ *
+ * \section asfdoc_sam0_system_gclk_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_gclk_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_gclk_basic.c main
+ *
+ * \subsection asfdoc_sam0_system_gclk_basic_use_case_flow Workflow
+ * -# As the clock is generated asynchronously to the system core, no special
+ * extra application code is required.
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h
new file mode 100755
index 0000000000000000000000000000000000000000..a01033f754321e92920161fae5c2aa9edcf6b230
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h
@@ -0,0 +1,102 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_critsec_use_case Quick Start Guide for SYSTEM INTERRUPT - Critical Section Use Case
+ *
+ * In this case we perform a critical piece of code, disabling all interrupts
+ * while a global shared flag is read. During the critical section, no interrupts
+ * may occur.
+ *
+ * \section asfdoc_sam0_system_interrupt_critsec_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_interrupt_critsec_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \section asfdoc_sam0_system_interrupt_critsec_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_interrupt_critsec_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_system_interrupt.c main_1
+ *
+ * \subsection asfdoc_sam0_system_interrupt_critsec_use_case_flow Workflow
+ * -# Enter a critical section to disable global interrupts.
+ * \snippet qs_system_interrupt.c critical_section_start
+ * \note Critical sections <i>may</i> be nested if desired; if nested, global
+ * interrupts will only be re-enabled once the outer-most critical
+ * section has completed.
+ *
+ * -# Check a global shared flag and perform a response. This code may be any
+ * critical code that requires exclusive access to all resources without the
+ * possibility of interruption.
+ * \snippet qs_system_interrupt.c do_critical_code
+ *
+ * -# Exit the critical section to re-enable global interrupts.
+ * \snippet qs_system_interrupt.c critical_section_end
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_enablemodint_use_case Quick Start Guide for SYSTEM INTERRUPT - Enable Module Interrupt Use Case
+ *
+ * In this case we enable interrupt handling for a specific module, as well as
+ * enable interrupts globally for the device.
+ *
+ * \section asfdoc_sam0_system_interrupt_enablemodint_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_interrupt_enablemodint_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \section asfdoc_sam0_system_interrupt_enablemodint_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_interrupt_enablemodint_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_system_interrupt.c main_2
+ *
+ * \subsection asfdoc_sam0_system_interrupt_enablemodint_use_case_flow Workflow
+ * -# Enable interrupt handling for the device's RTC peripheral.
+ * \snippet qs_system_interrupt.c module_int_enable
+ *
+ * -# Enable global interrupts, so that any enabled and active interrupt sources
+ * can trigger their respective handler functions.
+ * \snippet qs_system_interrupt.c global_int_enable
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
new file mode 100755
index 0000000000000000000000000000000000000000..606a05ecb7f955698652c4c8f65e6b5e9c84c244
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c
@@ -0,0 +1,214 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "system_interrupt.h"
+
+/**
+ * \brief Check if a interrupt line is pending
+ *
+ * Checks if the requested interrupt vector is pending.
+ *
+ * \param[in] vector Interrupt vector number to check
+ *
+ * \returns A boolean identifying if the requested interrupt vector is pending.
+ *
+ * \retval true Specified interrupt vector is pending
+ * \retval false Specified interrupt vector is not pending
+ *
+ */
+bool system_interrupt_is_pending(
+ const enum system_interrupt_vector vector)
+{
+ bool result;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+ } else {
+ Assert(false);
+ result = false;
+ }
+
+ return result;
+}
+
+/**
+ * \brief Set a interrupt vector as pending
+ *
+ * Set the requested interrupt vector as pending (i.e issues a software
+ * interrupt request for the specified vector). The software handler will be
+ * handled (if enabled) in a priority order based on vector number and
+ * configured priority settings.
+ *
+ * \param[in] vector Interrupt vector number which is set as pending
+ *
+ * \returns Status code identifying if the vector was successfully set as
+ * pending.
+ *
+ * \retval STATUS_OK If no error was detected
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_pending(
+ const enum system_interrupt_vector vector)
+{
+ enum status_code status = STATUS_OK;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ NVIC->ISPR[0] = (1 << vector);
+ } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+ /* Note: Because NMI has highest priority it will be executed
+ * immediately after it has been set pending */
+ SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+ } else {
+ /* The user want to set something unsupported as pending */
+ Assert(false);
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Clear pending interrupt vector
+ *
+ * Clear a pending interrupt vector, so the software handler is not executed.
+ *
+ * \param[in] vector Interrupt vector number to clear
+ *
+ * \returns A status code identifying if the interrupt pending state was
+ * successfully cleared.
+ *
+ * \retval STATUS_OK If no error was detected
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_clear_pending(
+ const enum system_interrupt_vector vector)
+{
+ enum status_code status = STATUS_OK;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ NVIC->ICPR[0] = (1 << vector);
+ } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+ /* Note: Clearing of NMI pending interrupts does not make sense and is
+ * not supported by the device, as it has the highest priority and will
+ * always be executed at the moment it is set */
+ return STATUS_ERR_INVALID_ARG;
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+ } else {
+ Assert(false);
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Set interrupt vector priority level
+ *
+ * Set the priority level of an external interrupt or exception.
+ *
+ * \param[in] vector Interrupt vector to change
+ * \param[in] priority_level New vector priority level to set
+ *
+ * \returns Status code indicating if the priority level of the interrupt was
+ * successfully set.
+ *
+ * \retval STATUS_OK If no error was detected
+ * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_priority(
+ const enum system_interrupt_vector vector,
+ const enum system_interrupt_priority_level priority_level)
+{
+ enum status_code status = STATUS_OK;
+
+ if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+ uint8_t register_num = vector / 4;
+ uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+ NVIC->IP[register_num] =
+ (NVIC->IP[register_num] & ~(0x3 << priority_pos)) |
+ (priority_level << priority_pos);
+
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+ } else {
+ Assert(false);
+ status = STATUS_ERR_INVALID_ARG;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Get interrupt vector priority level
+ *
+ * Retrieves the priority level of the requested external interrupt or exception.
+ *
+ * \param[in] vector Interrupt vector of which the priority level will be read
+ *
+ * \return Currently configured interrupt priority level of the given interrupt
+ * vector.
+ */
+enum system_interrupt_priority_level system_interrupt_get_priority(
+ const enum system_interrupt_vector vector)
+{
+ uint8_t register_num = vector / 4;
+ uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+ enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+ if (vector >= 0) {
+ priority = (enum system_interrupt_priority_level)
+ ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+ } else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+ priority = (enum system_interrupt_priority_level)
+ ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+ }
+
+ return priority;
+}
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h
new file mode 100755
index 0000000000000000000000000000000000000000..03dd4fdc6e1a989b8fab376065cb08ba86f26f70
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h
@@ -0,0 +1,431 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#define SYSTEM_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt Driver (SYSTEM INTERRUPT)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of internal software and hardware interrupts/exceptions.
+ *
+ * The following peripherals are used by this module:
+ * - NVIC (Nested Vector Interrupt Controller)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_interrupt_prerequisites
+ * - \ref asfdoc_sam0_system_interrupt_module_overview
+ * - \ref asfdoc_sam0_system_interrupt_special_considerations
+ * - \ref asfdoc_sam0_system_interrupt_extra_info
+ * - \ref asfdoc_sam0_system_interrupt_examples
+ * - \ref asfdoc_sam0_system_interrupt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
+ *
+ * The ARM® Cortex® M0+ core contains an interrupt an exception vector table, which
+ * can be used to configure the device's interrupt handlers; individual
+ * interrupts and exceptions can be enabled and disabled, as well as configured
+ * with a variable priority.
+ *
+ * This driver provides a set of wrappers around the core interrupt functions,
+ * to expose a simple API for the management of global and individual interrupts
+ * within the device.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
+ * In some applications it is important to ensure that no interrupts may be
+ * executed by the system whilst a critical portion of code is being run; for
+ * example, a buffer may be copied from one context to another - during which
+ * interrupts must be disabled to avoid corruption of the source buffer contents
+ * until the copy has completed. This driver provides a basic API to enter and
+ * exit nested critical sections, so that global interrupts can be kept disabled
+ * for as long as necessary to complete a critical application code section.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
+ * For some applications, it may be desirable to raise a module or core
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or
+ * exception as pending are provided to the user application.
+ *
+ * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
+ *
+ * Interrupts from peripherals in the SAM devices are on a per-module basis;
+ * an interrupt raised from any source within a module will cause a single,
+ * module-common handler to execute. It is the user application or driver's
+ * responsibility to de-multiplex the module-common interrupt to determine the
+ * exact interrupt cause.
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_system_interrupt_extra. This includes:
+ * - \ref asfdoc_sam0_system_interrupt_extra_acronyms
+ * - \ref asfdoc_sam0_system_interrupt_extra_dependencies
+ * - \ref asfdoc_sam0_system_interrupt_extra_errata
+ * - \ref asfdoc_sam0_system_interrupt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_interrupt_exqsg.
+ *
+ * \section asfdoc_sam0_system_interrupt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <core_cm0plus.h>
+#include "system_interrupt_features.h"
+
+/**
+ * \brief Table of possible system interrupt/exception vector priorities.
+ *
+ * Table of all possible interrupt and exception vector priorities within the
+ * device.
+ */
+enum system_interrupt_priority_level {
+ /** Priority level 0, the highest possible interrupt priority. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0,
+ /** Priority level 1. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1,
+ /** Priority level 2. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2,
+ /** Priority level 3, the lowest possible interrupt priority. */
+ SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3,
+};
+
+/**
+ * \name Critical Section Management
+ * @{
+ */
+
+/**
+ * \brief Enters a critical section
+ *
+ * Disables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+ cpu_irq_enter_critical();
+}
+
+/**
+ * \brief Leaves a critical section
+ *
+ * Enables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+ cpu_irq_leave_critical();
+}
+
+/** @} */
+
+/**
+ * \name Interrupt Enabling/Disabling
+ * @{
+ */
+
+/**
+ * \brief Check if global interrupts are enabled
+ *
+ * Checks if global interrupts are currently enabled.
+ *
+ * \returns A boolean that identifies if the global interrupts are enabled or not.
+ *
+ * \retval true Global interrupts are currently enabled
+ * \retval false Global interrupts are currently disabled
+ *
+ */
+static inline bool system_interrupt_is_global_enabled(void)
+{
+ return cpu_irq_is_enabled();
+}
+
+/**
+ * \brief Enables global interrupts
+ *
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.
+ */
+static inline void system_interrupt_enable_global(void)
+{
+ cpu_irq_enable();
+}
+
+/**
+ * \brief Disables global interrupts
+ *
+ * Disabled global interrupts in the device, preventing any enabled interrupt
+ * handlers from executing.
+ */
+static inline void system_interrupt_disable_global(void)
+{
+ cpu_irq_disable();
+}
+
+/**
+ * \brief Checks if an interrupt vector is enabled or not
+ *
+ * Checks if a specific interrupt vector is currently enabled.
+ *
+ * \param[in] vector Interrupt vector number to check
+ *
+ * \returns A variable identifying if the requested interrupt vector is enabled
+ *
+ * \retval true Specified interrupt vector is currently enabled
+ * \retval false Specified interrupt vector is currently disabled
+ *
+ */
+static inline bool system_interrupt_is_enabled(
+ const enum system_interrupt_vector vector)
+{
+ return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+}
+
+/**
+ * \brief Enable interrupt vector
+ *
+ * Enables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+ const enum system_interrupt_vector vector)
+{
+ NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/**
+ * \brief Disable interrupt vector
+ *
+ * Disables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to disable
+ */
+static inline void system_interrupt_disable(
+ const enum system_interrupt_vector vector)
+{
+ NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/** @} */
+
+/**
+ * \name Interrupt State Management
+ * @{
+ */
+
+/**
+ * \brief Get active interrupt (if any)
+ *
+ * Return the vector number for the current executing software handler, if any.
+ *
+ * \return Interrupt number that is currently executing.
+ */
+static inline enum system_interrupt_vector system_interrupt_get_active(void)
+{
+ uint32_t IPSR = __get_IPSR();
+
+ return (enum system_interrupt_vector)(IPSR & _SYSTEM_INTERRUPT_IPSR_MASK);
+}
+
+bool system_interrupt_is_pending(
+ const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_set_pending(
+ const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_clear_pending(
+ const enum system_interrupt_vector vector);
+
+/** @} */
+
+/**
+ * \name Interrupt Priority Management
+ * @{
+ */
+
+enum status_code system_interrupt_set_priority(
+ const enum system_interrupt_vector vector,
+ const enum system_interrupt_priority_level priority_level);
+
+enum system_interrupt_priority_level system_interrupt_get_priority(
+ const enum system_interrupt_vector vector);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>ISR</td>
+ * <td>Interrupt Service Routine</td>
+ * </tr>
+ * <tr>
+ * <td>NMI</td>
+ * <td>Non-maskable interrupt</td>
+ * </tr>
+ * <tr>
+ * <td>SERCOM</td>
+ * <td>Serial Communication Interface</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMR21</td>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that QSGs can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
+ * - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
+ *
+ * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>04/2014</td>
+ * <td>Add support for SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>02/2014</td>
+ * <td>Add support for SAMR21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Add support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
new file mode 100755
index 0000000000000000000000000000000000000000..9e7c31a110edfa4db4fd7fed2417cc82eaeeaa8a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
@@ -0,0 +1,170 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 System Interrupt Driver
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+ and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+# define _MODULE_IRQn(n, module) \
+ SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+ given module type on the selected device. */
+# define _SYSTEM_INTERRUPT_MODULES(name) \
+ MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f
+# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000007
+
+# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0
+
+# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 29
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAMD21 device.
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samd21 {
+#else
+enum system_interrupt_vector {
+#endif
+ /** Interrupt vector index for a NMI interrupt. */
+ SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn,
+ /** Interrupt vector index for a Hard Fault memory access exception. */
+ SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn,
+ /** Interrupt vector index for a Supervisor Call exception. */
+ SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn,
+ /** Interrupt vector index for a Pending Supervisor interrupt. */
+ SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn,
+ /** Interrupt vector index for a System Tick interrupt. */
+ SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn,
+
+ /** Interrupt vector index for a Power Manager peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn,
+ /** Interrupt vector index for a System Control peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn,
+ /** Interrupt vector index for a Watch Dog peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn,
+ /** Interrupt vector index for a Real Time Clock peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn,
+ /** Interrupt vector index for an External Interrupt peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn,
+ /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */
+ SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn,
+ /** Interrupt vector index for a Direct Memory Access interrupt. */
+ SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn,
+ /** Interrupt vector index for a Universal Serial Bus interrupt. */
+ SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn,
+ /** Interrupt vector index for an Event System interrupt. */
+ SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+ /** Interrupt vector index for a SERCOM peripheral interrupt.
+ *
+ * Each specific device may contain several SERCOM peripherals; each module
+ * instance will have its own entry in the table, with the instance number
+ * substituted for "n" in the entry name (e.g.
+ * \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+ */
+ SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn,
+
+ /** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+ *
+ * Each specific device may contain several TCC peripherals; each module
+ * instance will have its own entry in the table, with the instance number
+ * substituted for "n" in the entry name (e.g.
+ * \c SYSTEM_INTERRUPT_MODULE_TCC0).
+ */
+ SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn,
+
+ /** Interrupt vector index for a Timer/Counter peripheral interrupt.
+ *
+ * Each specific device may contain several TC peripherals; each module
+ * instance will have its own entry in the table, with the instance number
+ * substituted for "n" in the entry name (e.g.
+ * \c SYSTEM_INTERRUPT_MODULE_TC3).
+ */
+ SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn,
+#else
+ _SYSTEM_INTERRUPT_MODULES(SERCOM)
+
+ _SYSTEM_INTERRUPT_MODULES(TCC)
+
+ SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn,
+ SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn,
+# if (SAMD21J)
+ //SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn,
+ //SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn,
+# endif
+#endif
+
+ /** Interrupt vector index for an Analog Comparator peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn,
+ /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn,
+ /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */
+ SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn,
+ /** Interrupt vector index for a Peripheral Touch Controller peripheral
+ * interrupt. */
+ SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn,
+ /** Interrupt vector index for a Inter-IC Sound Interface peripheral
+ * interrupt. */
+ SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn,
+};
+
+/** @} */
+
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/pinmux.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/pinmux.c
new file mode 100755
index 0000000000000000000000000000000000000000..6ae65acc06f1fa6f64aced25e1ce9c355e339b07
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/pinmux.c
@@ -0,0 +1,215 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <pinmux.h>
+
+/**
+ * \internal
+ * Writes out a given configuration of a Port pin configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] port Base of the PORT module to configure.
+ * \param[in] pin_mask Mask of the port pin to configure.
+ * \param[in] config Configuration settings for the pin.
+ */
+static void _system_pinmux_config(
+ PortGroup *const port,
+ const uint32_t pin_mask,
+ const struct system_pinmux_config *const config)
+{
+ Assert(port);
+ Assert(config);
+
+ /* Track the configuration bits into a temporary variable before writing */
+ uint32_t pin_cfg = 0;
+
+ /* Enabled powersave mode, don't create configuration */
+ if (!config->powersave) {
+ /* Enable the pin peripheral mux flag if non-GPIO selected (pin mux will
+ * be written later) and store the new mux mask */
+ if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+ pin_cfg |= PORT_WRCONFIG_PMUXEN;
+ pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+ }
+
+ /* Check if the user has requested that the input buffer be enabled */
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+ /* Enable input buffer flag */
+ pin_cfg |= PORT_WRCONFIG_INEN;
+
+ /* Enable pull-up/pull-down control flag if requested */
+ if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+ pin_cfg |= PORT_WRCONFIG_PULLEN;
+ }
+
+ /* Clear the port DIR bits to disable the output buffer */
+ port->DIRCLR.reg = pin_mask;
+ }
+
+ /* Check if the user has requested that the output buffer be enabled */
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+ /* Cannot use a pullup if the output driver is enabled,
+ * if requested the input buffer can only sample the current
+ * output state */
+ pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+ }
+ }
+
+ /* The Write Configuration register (WRCONFIG) requires the
+ * pins to to grouped into two 16-bit half-words - split them out here */
+ uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+ uint32_t upper_pin_mask = (pin_mask >> 16);
+
+ /* Configure the lower 16-bits of the port to the desired configuration,
+ * including the pin peripheral multiplexer just in case it is enabled */
+ port->WRCONFIG.reg
+ = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+ pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+ /* Configure the upper 16-bits of the port to the desired configuration,
+ * including the pin peripheral multiplexer just in case it is enabled */
+ port->WRCONFIG.reg
+ = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+ pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+ PORT_WRCONFIG_HWSEL;
+
+ if(!config->powersave) {
+ /* Set the pull-up state once the port pins are configured if one was
+ * requested and it does not violate the valid set of port
+ * configurations */
+ if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+ /* Set the OUT register bits to enable the pullup if requested,
+ * clear to enable pull-down */
+ if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+ port->OUTSET.reg = pin_mask;
+ } else {
+ port->OUTCLR.reg = pin_mask;
+ }
+ }
+
+ /* Check if the user has requested that the output buffer be enabled */
+ if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+ (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+ /* Set the port DIR bits to enable the output buffer */
+ port->DIRSET.reg = pin_mask;
+ }
+ }
+}
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure.
+ * \param[in] config Configuration settings for the pin.
+ */
+void system_pinmux_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct system_pinmux_config *const config)
+{
+ PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+ _system_pinmux_config(port, pin_mask, config);
+}
+
+/**
+ * \brief Writes a Port pin group configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ * configuration setting is ignored.
+ *
+ * \param[in] port Base of the PORT module to configure.
+ * \param[in] mask Mask of the port pin(s) to configure.
+ * \param[in] config Configuration settings for the pin.
+ */
+void system_pinmux_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct system_pinmux_config *const config)
+{
+ Assert(port);
+
+ for (int i = 0; i < 32; i++) {
+ if (mask & (1UL << i)) {
+ _system_pinmux_config(port, (1UL << i), config);
+ }
+ }
+}
+
+/**
+ * \brief Configures the input sampling mode for a group of pins.
+ *
+ * Configures the input sampling mode for a group of pins, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] port Base of the PORT module to configure.
+ * \param[in] mask Mask of the port pin(s) to configure.
+ * \param[in] mode New pin sampling mode to configure.
+ */
+void system_pinmux_group_set_input_sample_mode(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_sample mode)
+{
+ Assert(port);
+
+ if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+ port->CTRL.reg |= mask;
+ } else {
+ port->CTRL.reg &= ~mask;
+ }
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/pinmux.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/pinmux.h
new file mode 100755
index 0000000000000000000000000000000000000000..370c3db811a598f7f393f56e653a0fe2d76ad923
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/pinmux.h
@@ -0,0 +1,517 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef PINMUX_H_INCLUDED
+#define PINMUX_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer Driver (SYSTEM PINMUX)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of the device's physical I/O Pins, to alter the direction and
+ * input/drive characteristics as well as to configure the pin peripheral
+ * multiplexer selection.
+ *
+ * The following peripherals are used by this module:
+ * - PORT (Port I/O Management)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * Physically, the modules are interconnected within the device as shown in the
+ * following diagram:
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_pinmux_prerequisites
+ * - \ref asfdoc_sam0_system_pinmux_module_overview
+ * - \ref asfdoc_sam0_system_pinmux_special_considerations
+ * - \ref asfdoc_sam0_system_pinmux_extra_info
+ * - \ref asfdoc_sam0_system_pinmux_examples
+ * - \ref asfdoc_sam0_system_pinmux_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
+ *
+ * The SAM devices contain a number of General Purpose I/O pins, used to
+ * interface the user application logic and internal hardware peripherals to
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method
+ * of configuring the individual pin peripheral multiplexers to select
+ * alternate pin functions.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical, and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
+ * SAM devices contain a peripheral MUX, which is individually controllable
+ * for each I/O pin of the device. The peripheral MUX allows you to select the
+ * function of a physical package pin - whether it will be controlled as a user
+ * controllable GPIO pin, or whether it will be connected internally to one of
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
+ * configured in GPIO mode, other peripherals connected to the same pin will be
+ * disabled.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
+ * There are several special modes that can be selected on one or more I/O pins
+ * of the device, which alter the input and output characteristics of the pad:
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
+ * The Drive Strength configures the strength of the output driver on the
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely
+ * drive, however some I/O pads offer a higher drive mode which increases this
+ * limit for that I/O pin at the expense of an increased power consumption.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
+ * The Slew Rate configures the slew rate of the output driver, limiting the
+ * rate at which the pad output voltage can change with time.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
+ * The Input Sample Mode configures the input sampler buffer of the pad. By
+ * default, the input buffer is only sampled "on-demand", i.e. when the user
+ * application attempts to read from the input buffer. This mode is the most
+ * power efficient, but increases the latency of the input sample by two clock
+ * cycles of the port clock. To reduce latency, the input sampler can instead
+ * be configured to always sample the input buffer on each port clock cycle, at
+ * the expense of an increased power consumption.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
+ * how this module is interconnected within the device:
+ *
+ * \anchor asfdoc_sam0_system_pinmux_intconnections
+ * \dot
+ * digraph overview {
+ * node [label="Port Pad" shape=square] pad;
+ *
+ * subgraph driver {
+ * node [label="Peripheral Mux" shape=trapezium] pinmux;
+ * node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
+ * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ * }
+ *
+ * pinmux -> gpio;
+ * pad -> pinmux;
+ * pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampling mode is set in groups of four physical
+ * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
+ * will configure the sampling mode of the entire sub-group.
+ *
+ * High Drive Strength output driver mode is not available on all device pins -
+ * refer to your device specific datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_system_pinmux_extra. This includes:
+ * - \ref asfdoc_sam0_system_pinmux_extra_acronyms
+ * - \ref asfdoc_sam0_system_pinmux_extra_dependencies
+ * - \ref asfdoc_sam0_system_pinmux_extra_errata
+ * - \ref asfdoc_sam0_system_pinmux_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_pinmux_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Peripheral multiplexer index to select GPIO mode for a pin. */
+#define SYSTEM_PINMUX_GPIO (1 << 7)
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum system_pinmux_pin_dir {
+ /** The pin's input buffer should be enabled, so that the pin state can
+ * be read. */
+ SYSTEM_PINMUX_PIN_DIR_INPUT,
+ /** The pin's output buffer should be enabled, so that the pin state can
+ * be set (but not read back). */
+ SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+ /** The pin's output and input buffers should both be enabled, so that the
+ * pin state can be set and read back. */
+ SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum system_pinmux_pin_pull {
+ /** No logical pull should be applied to the pin. */
+ SYSTEM_PINMUX_PIN_PULL_NONE,
+ /** Pin should be pulled up when idle. */
+ SYSTEM_PINMUX_PIN_PULL_UP,
+ /** Pin should be pulled down when idle. */
+ SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin digital input sampling mode enum.
+ *
+ * Enum for the possible input sampling modes for the port pin configuration
+ * structure, to indicate the type of sampling a port pin should use.
+ */
+enum system_pinmux_pin_sample {
+ /** Pin input buffer should continuously sample the pin state. */
+ SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+ /** Pin input buffer should be enabled when the IN register is read. */
+ SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should be
+ * structure should be initialized by the
+ * \ref system_pinmux_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_pinmux_config {
+ /** MUX index of the peripheral that should control the pin, if peripheral
+ * control is desired. For GPIO use, this should be set to
+ * \ref SYSTEM_PINMUX_GPIO. */
+ uint8_t mux_position;
+
+ /** Port buffer input/output direction. */
+ enum system_pinmux_pin_dir direction;
+
+ /** Logic level pull of the input buffer. */
+ enum system_pinmux_pin_pull input_pull;
+
+ /** Enable lowest possible powerstate on the pin
+ *
+ * \note All other configurations will be ignored, the pin will be disabled
+ */
+ bool powersave;
+};
+
+/** \name Configuration and initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin configuration structure to defaults.
+ *
+ * Initializes a given Port pin configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Non peripheral (i.e. GPIO) controlled
+ * \li Input mode with internal pull-up enabled
+ *
+ * \param[out] config Configuration structure to initialize to default values
+ */
+static inline void system_pinmux_get_config_defaults(
+ struct system_pinmux_config *const config)
+{
+ /* Sanity check arguments */
+ Assert(config);
+
+ /* Default configuration values */
+ config->mux_position = SYSTEM_PINMUX_GPIO;
+ config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+ config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
+ config->powersave = false;
+}
+
+void system_pinmux_pin_set_config(
+ const uint8_t gpio_pin,
+ const struct system_pinmux_config *const config);
+
+void system_pinmux_group_set_config(
+ PortGroup *const port,
+ const uint32_t mask,
+ const struct system_pinmux_config *const config);
+
+/** @} */
+
+/** \name Special mode configuration (physical group orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to convert.
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
+ const uint8_t gpio_pin)
+{
+ uint8_t port_index = (gpio_pin / 128);
+ uint8_t group_index = (gpio_pin / 32);
+
+ /* Array of available ports. */
+ Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+ if (port_index < PORT_INST_NUM) {
+ return &(ports[port_index]->Group[group_index]);
+ } else {
+ Assert(false);
+ return NULL;
+ }
+}
+
+void system_pinmux_group_set_input_sample_mode(
+ PortGroup *const port,
+ const uint32_t mask,
+ const enum system_pinmux_pin_sample mode);
+
+/** @} */
+
+/** \name Special mode configuration (logical pin orientated)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the currently selected MUX position of a logical pin.
+ *
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure.
+ *
+ * \return Currently selected peripheral index on the specified pin.
+ */
+static inline uint8_t system_pinmux_pin_get_mux_position(
+ const uint8_t gpio_pin)
+{
+ PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
+ return SYSTEM_PINMUX_GPIO;
+ }
+
+ uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+ if (pin_index & 1) {
+ return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+ }
+ else {
+ return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+ }
+}
+
+/**
+ * \brief Configures the input sampling mode for a GPIO pin.
+ *
+ * Configures the input sampling mode for a GPIO input, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure.
+ * \param[in] mode New pin sampling mode to configure.
+ */
+static inline void system_pinmux_pin_set_input_sample_mode(
+ const uint8_t gpio_pin,
+ const enum system_pinmux_pin_sample mode)
+{
+ PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+ uint32_t pin_index = (gpio_pin % 32);
+
+ if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+ port->CTRL.reg |= (1 << pin_index);
+ } else {
+ port->CTRL.reg &= ~(1 << pin_index);
+ }
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr>
+ * <td>GPIO</td>
+ * <td>General Purpose Input/Output</td>
+ * </tr>
+ * <tr>
+ * <td>MUX</td>
+ * <td>Multiplexer</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Removed code of open drain, slew limit and drive strength
+ * features.</td>
+ * </tr>
+ * <tr>
+ * <td>Fixed broken sampling mode function implementations, which wrote
+ * corrupt configuration values to the device registers.</td>
+ * </tr>
+ * <tr>
+ * <td>Added missing NULL pointer asserts to the PORT driver functions.</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that QSGs can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ * - \subpage asfdoc_sam0_system_pinmux_basic_use_case
+ *
+ * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>F</td>
+ * <td>04/2014</td>
+ * <td>Add support for SAMD10/D11</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>02/2014</td>
+ * <td>Add support for SAMR21</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>01/2014</td>
+ * <td>Add support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>09/2013</td>
+ * <td>Fixed incorrect documentation for the device pin sampling mode.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h
new file mode 100755
index 0000000000000000000000000000000000000000..8dc9a665e244d9797aaa4cdf86df2669a1ab378a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief SAM PINMUX Driver Quick Start
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
+ *
+ * In this use case, the PINMUX module is configured for:
+ * \li One pin in input mode, with pull-up enabled, connected to the GPIO
+ * module
+ * \li Sampling mode of the pin changed to sample on demand
+ *
+ * This use case sets up the PINMUX to configure a physical I/O pin set as
+ * an input with pull-up. and changes the sampling mode of the pin to reduce
+ * power by only sampling the physical pin state when the user application
+ * attempts to read it.
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your application:
+ * \snippet qs_pinmux_basic.c setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
+ * -# Create a PINMUX module pin configuration struct, which can be filled out
+ * to adjust the configuration of a single port pin.
+ * \snippet qs_pinmux_basic.c pinmux_config
+ * -# Initialize the pin configuration struct with the module's default values.
+ * \snippet qs_pinmux_basic.c pinmux_config_defaults
+ * \note This should always be performed before using the configuration
+ * struct to ensure that all values are initialized to known default
+ * settings.
+ *
+ * -# Adjust the configuration struct to request an input pin with pullup
+ * connected to the GPIO peripheral.
+ * \snippet qs_pinmux_basic.c pinmux_update_config_values
+ * -# Configure GPIO10 with the initialized pin configuration struct, to enable
+ * the input sampler on the pin.
+ * \snippet qs_pinmux_basic.c pinmux_set_config
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_pinmux_basic.c main
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
+
+ * -# Adjust the configuration of the pin to enable on-demand sampling mode.
+ * \snippet qs_pinmux_basic.c pinmux_change_input_sampling
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/system.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/system.c
new file mode 100755
index 0000000000000000000000000000000000000000..b814b78d5366cc7b66070eff08978a5eb6c67534
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/system.c
@@ -0,0 +1,102 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <system.h>
+
+/**
+ * \internal
+ * Dummy initialization function, used as a weak alias target for the various
+ * init functions called by \ref system_init().
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+ return;
+}
+
+#if !defined(__DOXYGEN__)
+# if defined(__GNUC__)
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+# elif defined(__ICCARM__)
+void system_clock_init(void);
+void system_board_init(void);
+void _system_events_init(void);
+void _system_extint_init(void);
+# pragma weak system_clock_init=_system_dummy_init
+# pragma weak system_board_init=_system_dummy_init
+# pragma weak _system_events_init=_system_dummy_init
+# pragma weak _system_extint_init=_system_dummy_init
+# endif
+#endif
+
+/**
+ * \brief Initialize system
+ *
+ * This function will call the various initialization functions within the
+ * system namespace. If a given optional system module is not available, the
+ * associated call will effectively be a NOP (No Operation).
+ *
+ * Currently the following initialization functions are supported:
+ * - System clock initialization (via the SYSTEM CLOCK sub-module)
+ * - Board hardware initialization (via the Board module)
+ * - Event system driver initialization (via the EVSYS module)
+ * - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+ /* Configure GCLK and clock sources according to conf_clocks.h */
+ system_clock_init();
+
+ /* Initialize board hardware */
+ system_board_init();
+
+ /* Initialize EVSYS hardware */
+ _system_events_init();
+
+ /* Initialize External hardware */
+ _system_extint_init();
+}
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/system.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/system.h
new file mode 100755
index 0000000000000000000000000000000000000000..f07023afc61c3242affb9eee9cc706dbd160eb8e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/system/system.h
@@ -0,0 +1,577 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_group SAM System Driver (SYSTEM)
+ *
+ * This driver for SAM devices provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals,
+ *
+ * The following peripherals are used by this module:
+ * - SYSCTRL (System Control)
+ * - PM (Power Manager)
+ *
+ * The following devices can use this module:
+ * - SAM D20/D21
+ * - SAM R21
+ * - SAM D10/D11
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_system_prerequisites
+ * - \ref asfdoc_sam0_system_module_overview
+ * - \ref asfdoc_sam0_system_special_considerations
+ * - \ref asfdoc_sam0_system_extra_info
+ * - \ref asfdoc_sam0_system_examples
+ * - \ref asfdoc_sam0_system_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ * - System Core (this module)
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
+ * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
+ *
+ *
+ * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
+ * The various analog modules within the SAM devices (such as AC, ADC and
+ * DAC) require a voltage reference to be configured to act as a reference point
+ * for comparisons and conversions.
+ *
+ * The SAM devices contain multiple references, including an internal
+ * temperature sensor, and a fixed band-gap voltage source. When enabled, the
+ * associated voltage reference can be selected within the desired peripheral
+ * where applicable.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
+ * In some application there may be a need to execute a different program
+ * flow based on how the device was reset. For example, if the cause of reset
+ * was the Watchdog timer (WDT), this might indicate an error in the application
+ * and a form of error handling or error logging might be needed.
+ *
+ * For this reason, an API is provided to retrieve the cause of the last system
+ * reset, so that appropriate action can be taken.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
+ * The SAM devices have several sleep modes, where the sleep mode controls
+ * which clock systems on the device will remain enabled or disabled when the
+ * device enters a low power sleep mode.
+ * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
+ * clock settings of the different sleep modes.
+ *
+ * \anchor asfdoc_sam0_system_module_sleep_mode_table
+ * <table>
+ * <caption>SAM Device Sleep Modes</caption>
+ * <tr>
+ * <th>Sleep mode</th>
+ * <th>CPU clock</th>
+ * <th>AHB clock</th>
+ * <th>APB clocks</th>
+ * <th>Clock sources</th>
+ * <th>System clock</th>
+ * <th>32KHz</th>
+ * <th>Reg mode</th>
+ * <th>RAM mode</th>
+ * </tr>
+ * <tr>
+ * <td>IDLE 0</td>
+ * <td>Stop</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>IDLE 1</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>IDLE 2</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Run</td>
+ * <td>Normal</td>
+ * <td>Normal</td>
+ * </tr>
+ * <tr>
+ * <td>STANDBY</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Stop</td>
+ * <td>Low Power</td>
+ * <td>Source/Drain biasing</td>
+ * </tr>
+ * </table>
+ *
+ * To enter device sleep, one of the available sleep modes must be set, and the
+ * function to enter sleep called. The device will automatically wake up in
+ * response to an interrupt being generated or other device event.
+ *
+ * Some peripheral clocks will remain enabled during sleep, depending on their
+ * configuration; if desired, modules can remain clocked during sleep to allow
+ * them to continue to operate while other parts of the system are powered down
+ * to save power.
+ *
+ *
+ * \section asfdoc_sam0_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_info Extra Information
+ *
+ * For extra information see \ref asfdoc_sam0_system_extra. This includes:
+ * - \ref asfdoc_sam0_system_extra_acronyms
+ * - \ref asfdoc_sam0_system_extra_dependencies
+ * - \ref asfdoc_sam0_system_extra_errata
+ * - \ref asfdoc_sam0_system_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_examples Examples
+ *
+ * For SYSTEM module related examples, please refer to the sub-modules listed in
+ * the \ref asfdoc_sam0_system_module_overview "system module overview".
+ *
+ *
+ * \section asfdoc_sam0_system_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \brief Voltage references within the device.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+ /** Temperature sensor voltage reference. */
+ SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+ /** Bandgap voltage reference. */
+ SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
+};
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+ /** IDLE 0 sleep mode. */
+ SYSTEM_SLEEPMODE_IDLE_0,
+ /** IDLE 1 sleep mode. */
+ SYSTEM_SLEEPMODE_IDLE_1,
+ /** IDLE 2 sleep mode. */
+ SYSTEM_SLEEPMODE_IDLE_2,
+ /** Standby sleep mode. */
+ SYSTEM_SLEEPMODE_STANDBY,
+};
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+ /** The system was last reset by a software reset. */
+ SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST,
+ /** The system was last reset by the watchdog timer. */
+ SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT,
+ /** The system was last reset because the external reset line was pulled low. */
+ SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
+ /** The system was last reset by the BOD33. */
+ SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33,
+ /** The system was last reset by the BOD12. */
+ SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12,
+ /** The system was last reset by the POR (Power on reset). */
+ SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR,
+};
+
+/**
+ * \name System identification
+ * @{
+ */
+
+/**
+ * \brief Retrieve the device identification signature
+ *
+ * Retrieves the signature of the current device.
+ *
+ * \return Device ID signature as a 32-bit integer.
+ */
+static inline uint32_t system_get_device_id(void)
+{
+ return DSU->DID.reg;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Voltage references
+ * @{
+ */
+
+/**
+ * \brief Enable the selected voltage reference
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+ const enum system_voltage_reference vref)
+{
+ switch (vref) {
+ case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+ SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+ break;
+
+ case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+ SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+ break;
+
+ default:
+ Assert(false);
+ return;
+ }
+}
+
+/**
+ * \brief Disable the selected voltage reference
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+ const enum system_voltage_reference vref)
+{
+ switch (vref) {
+ case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+ SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+ break;
+
+ case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+ SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+ break;
+
+ default:
+ Assert(false);
+ return;
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Device sleep
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode Sleep mode to configure for the next sleep operation
+ *
+ * \retval STATUS_OK Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not
+ * available
+ */
+static inline enum status_code system_set_sleepmode(
+ const enum system_sleepmode sleep_mode)
+{
+ switch (sleep_mode) {
+ case SYSTEM_SLEEPMODE_IDLE_0:
+ case SYSTEM_SLEEPMODE_IDLE_1:
+ case SYSTEM_SLEEPMODE_IDLE_2:
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ PM->SLEEP.reg = sleep_mode;
+ break;
+
+ case SYSTEM_SLEEPMODE_STANDBY:
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ break;
+
+ default:
+ return STATUS_ERR_INVALID_ARG;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
+ * instruction to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode until woken by an interrupt.
+ */
+static inline void system_sleep(void)
+{
+ __DSB();
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Reset control
+ * @{
+ */
+
+/**
+ * \brief Check if bugger is present
+ *
+ * Check if debugger is connected to the onboard debug system (DAP)
+ *
+ * \return A bool identifying if a debugger is present
+ *
+ * \retval true Debugger is connected to the system
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+ return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+}
+
+/**
+ * \brief Reset the MCU
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC, all 32kHz sources,
+ * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
+ *
+ */
+static inline void system_reset(void)
+{
+ NVIC_SystemReset();
+}
+
+/**
+ * \brief Return the reset cause
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+ return (enum system_reset_cause)PM->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name System initialization
+ * @{
+ */
+
+void system_init(void);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_sam0_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Definition</th>
+ * </tr>
+ * <tr>
+ * <td>PM</td>
+ * <td>Power Manager</td>
+ * </tr>
+ * <tr>
+ * <td>SYSCTRL</td>
+ * <td>System control interface</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam0_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Added support for SAMD21</td>
+ * </tr>
+ * <tr>
+ * <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
+ * </tr>
+ * <tr>
+ * <td>Added new \c system_get_device_id() function to retrieved the device
+ * ID.</td>
+ * </tr>
+ * <tr>
+ * <td>Initial Release</td>
+ * </tr>
+ * </table>
+ *
+ * \page asfdoc_sam0_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>E</td>
+ * <td>04/2014</td>
+ * <td>Added support for SAMD10/D11.</td>
+ * </tr>
+ * <tr>
+ * <td>D</td>
+ * <td>02/2014</td>
+ * <td>Added support for SAMR21.</td>
+ * </tr>
+ * <tr>
+ * <td>C</td>
+ * <td>01/2014</td>
+ * <td>Added support for SAMD21.</td>
+ * </tr>
+ * <tr>
+ * <td>B</td>
+ * <td>06/2013</td>
+ * <td>Corrected documentation typos.</td>
+ * </tr>
+ * <tr>
+ * <td>A</td>
+ * <td>06/2013</td>
+ * <td>Initial release</td>
+ * </tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_device_udd.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_device_udd.c
new file mode 100755
index 0000000000000000000000000000000000000000..d114700853e2a6b2c34ff6df3cd4ba1a5762e7f7
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_device_udd.c
@@ -0,0 +1,1242 @@
+/**
+ * \file
+ *
+ * \brief USB Device wrapper layer for compliance with common driver UDD
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <string.h>
+#include <stdlib.h>
+
+// Get USB device configuration
+#include "conf_usb.h"
+#include "udd.h"
+#include "usb.h"
+#include "usb_dual.h"
+#include "sleepmgr.h"
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup usb_device_udd_group USB Device Driver Implement (UDD)
+ * USB low-level driver for USB device mode
+ * @{
+ */
+// Check USB device configuration
+#ifdef USB_DEVICE_HS_SUPPORT
+# error The High speed mode is not supported on this part, please remove USB_DEVICE_HS_SUPPORT in conf_usb.h
+#endif
+
+#if !(SAMD21) && !(SAMR21) && !(SAMD11)
+# error The current USB Device Driver supports only SAMD21/R21/D11
+#endif
+
+#ifndef UDC_REMOTEWAKEUP_LPM_ENABLE
+#define UDC_REMOTEWAKEUP_LPM_ENABLE()
+#endif
+#ifndef UDC_REMOTEWAKEUP_LPM_DISABLE
+#define UDC_REMOTEWAKEUP_LPM_DISABLE()
+#endif
+#ifndef UDC_SUSPEND_LPM_EVENT
+#define UDC_SUSPEND_LPM_EVENT()
+#endif
+
+/* for debug text */
+#ifdef USB_DEBUG
+# define dbg_print printf
+#else
+# define dbg_print(...)
+#endif
+
+/** Maximum size of a transfer in multi-packet mode */
+#define UDD_ENDPOINT_MAX_TRANS ((8*1024)-1)
+
+/** USB software device instance structure */
+struct usb_module usb_device;
+
+/**
+ * \name Clock management
+ *
+ * @{
+ */
+#ifndef UDD_CLOCK_GEN
+# define UDD_CLOCK_GEN GCLK_GENERATOR_0
+#endif
+#ifndef UDD_CLOCK_SOURCE
+# define UDD_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL
+#endif
+static inline void udd_wait_clock_ready(void)
+{
+
+ if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DPLL) {
+#define DPLL_READY_FLAG (SYSCTRL_DPLLSTATUS_ENABLE | \
+ SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)
+
+ while((SYSCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
+ }
+
+ if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DFLL) {
+#define DFLL_READY_FLAG (SYSCTRL_PCLKSR_DFLLRDY | \
+ SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC)
+
+ /* In USB recovery mode the status is not checked */
+ if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM)) {
+ while((SYSCTRL->PCLKSR.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
+ } else {
+ while((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY);
+ }
+ }
+
+}
+/** @} */
+
+/**
+ * \name Power management
+ *
+ * @{
+ */
+#ifndef UDD_NO_SLEEP_MGR
+
+#include "sleepmgr.h"
+/** States of USB interface */
+enum udd_usb_state_enum {
+ UDD_STATE_OFF,
+ UDD_STATE_SUSPEND,
+ UDD_STATE_SUSPEND_LPM,
+ UDD_STATE_IDLE,
+};
+
+/** \brief Manages the sleep mode following the USB state
+ *
+ * \param new_state New USB state
+ */
+static void udd_sleep_mode(enum udd_usb_state_enum new_state)
+{
+ enum sleepmgr_mode sleep_mode[] = {
+ SLEEPMGR_ACTIVE, /* UDD_STATE_OFF (not used) */
+ SLEEPMGR_IDLE_2, /* UDD_STATE_SUSPEND */
+ SLEEPMGR_IDLE_1, /* UDD_STATE_SUSPEND_LPM */
+ SLEEPMGR_IDLE_0, /* UDD_STATE_IDLE */
+ };
+
+ static enum udd_usb_state_enum udd_state = UDD_STATE_OFF;
+
+ if (udd_state == new_state) {
+ return; // No change
+ }
+ if (new_state != UDD_STATE_OFF) {
+ /* Lock new limit */
+ sleepmgr_lock_mode(sleep_mode[new_state]);
+ }
+ if (udd_state != UDD_STATE_OFF) {
+ /* Unlock old limit */
+ sleepmgr_unlock_mode(sleep_mode[udd_state]);
+ }
+ udd_state = new_state;
+}
+
+#else
+# define udd_sleep_mode(arg)
+#endif
+/** @} */
+
+/**
+ * \name Control endpoint low level management routine.
+ *
+ * This function performs control endpoint management.
+ * It handles the SETUP/DATA/HANDSHAKE phases of a control transaction.
+ *
+ * @{
+ */
+
+/**
+ * \brief Buffer to store the data received on control endpoint (SETUP/OUT endpoint 0)
+ *
+ * Used to avoid a RAM buffer overflow in case of the payload buffer
+ * is smaller than control endpoint size
+ */
+UDC_BSS(4)
+uint8_t udd_ctrl_buffer[USB_DEVICE_EP_CTRL_SIZE];
+
+/** Bit definitions about endpoint control state machine for udd_ep_control_state */
+typedef enum {
+ UDD_EPCTRL_SETUP = 0, //!< Wait a SETUP packet
+ UDD_EPCTRL_DATA_OUT = 1, //!< Wait a OUT data packet
+ UDD_EPCTRL_DATA_IN = 2, //!< Wait a IN data packet
+ UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP = 3, //!< Wait a IN ZLP packet
+ UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet
+ UDD_EPCTRL_STALL_REQ = 5, //!< STALL enabled on IN & OUT packet
+} udd_ctrl_ep_state_t;
+
+/** Global variable to give and record information of the set up request management */
+udd_ctrl_request_t udd_g_ctrlreq;
+
+/** State of the endpoint control management */
+static udd_ctrl_ep_state_t udd_ep_control_state;
+
+/** Total number of data received/sent during data packet phase with previous payload buffers */
+static uint16_t udd_ctrl_prev_payload_nb_trans;
+
+/** Number of data received/sent to/from udd_g_ctrlreq.payload buffer */
+static uint16_t udd_ctrl_payload_nb_trans;
+
+/** @} */
+
+/**
+ * \name Management of bulk/interrupt/isochronous endpoints
+ *
+ * The UDD manages the data transfer on endpoints:
+ * - Start data transfer on endpoint with USB Device DMA
+ * - Send a ZLP packet if requested
+ * - Call callback registered to signal end of transfer
+ * The transfer abort and stall feature are supported.
+ *
+ * @{
+ */
+
+/**
+ * \brief Buffer to store the data received on bulk/interrupt endpoints
+ *
+ * Used to avoid a RAM buffer overflow in case of the user buffer
+ * is smaller than endpoint size
+ *
+ * \warning The protected interrupt endpoint size is 512 bytes maximum.
+ * \warning The isochronous and endpoint is not protected by this system and
+ * the user must always use a buffer corresponding at endpoint size.
+ */
+#if (defined USB_DEVICE_LOW_SPEED)
+UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][8];
+#elif (defined USB_DEVICE_HS_SUPPORT)
+UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][512];
+#else
+UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][64];
+#endif
+
+/** Structure definition about job registered on an endpoint */
+typedef struct {
+ union {
+ //! Callback to call at the end of transfer
+ udd_callback_trans_t call_trans;
+ //! Callback to call when the endpoint halt is cleared
+ udd_callback_halt_cleared_t call_nohalt;
+ };
+ //! Buffer located in internal RAM to send or fill during job
+ uint8_t *buf;
+ //! Size of buffer to send or fill
+ iram_size_t buf_size;
+ //! Total number of data transferred on endpoint
+ iram_size_t nb_trans;
+ //! Endpoint size
+ uint16_t ep_size;
+ //! A job is registered on this endpoint
+ uint8_t busy:1;
+ //! A short packet is requested for this job on endpoint IN
+ uint8_t b_shortpacket:1;
+ //! The cache buffer is currently used on endpoint OUT
+ uint8_t b_use_out_cache_buffer:1;
+} udd_ep_job_t;
+
+/** Array to register a job on bulk/interrupt/isochronous endpoint */
+static udd_ep_job_t udd_ep_job[2 * USB_DEVICE_MAX_EP];
+
+/** @} */
+
+/**
+ * \brief Get the detailed job by endpoint number
+ * \param[in] ep Endpoint Address
+ * \retval pointer to an udd_ep_job_t structure instance
+ */
+static udd_ep_job_t* udd_ep_get_job(udd_ep_id_t ep)
+{
+ return &udd_ep_job[(2 * (ep & USB_EP_ADDR_MASK) + ((ep & USB_EP_DIR_IN) ? 1 : 0)) - 2];
+}
+
+/**
+ * \brief Endpoint IN process, continue to send packets or zero length packet
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ep_trans_in_next(void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+ udd_ep_id_t ep = ep_callback_para->endpoint_address;
+ uint16_t ep_size, nb_trans;
+ uint16_t next_trans;
+ udd_ep_id_t ep_num;
+ udd_ep_job_t *ptr_job;
+
+ ptr_job = udd_ep_get_job(ep);
+ ep_num = ep & USB_EP_ADDR_MASK;
+
+ ep_size = ptr_job->ep_size;
+ /* Update number of data transferred */
+ nb_trans = ep_callback_para->sent_bytes;
+ ptr_job->nb_trans += nb_trans;
+
+ /* Need to send other data */
+ if (ptr_job->nb_trans != ptr_job->buf_size) {
+ next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+ if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+ /* The USB hardware support a maximum
+ * transfer size of UDD_ENDPOINT_MAX_TRANS Bytes */
+ next_trans = UDD_ENDPOINT_MAX_TRANS -(UDD_ENDPOINT_MAX_TRANS % ep_size);
+ }
+ /* Need ZLP, if requested and last packet is not a short packet */
+ ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ep_size));
+ usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
+ return;
+ }
+
+ /* Need to send a ZLP after all data transfer */
+ if (ptr_job->b_shortpacket) {
+ ptr_job->b_shortpacket = false;
+ /* Start new transfer */
+ usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],0);
+ return;
+ }
+
+ /* Job complete then call callback */
+ ptr_job->busy = false;
+ if (NULL != ptr_job->call_trans) {
+ ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
+ }
+}
+
+/**
+ * \brief Endpoint OUT process, continue to receive packets or zero length packet
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ep_trans_out_next(void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+ udd_ep_id_t ep = ep_callback_para->endpoint_address;
+ uint16_t ep_size, nb_trans;
+ uint16_t next_trans;
+ udd_ep_id_t ep_num;
+ udd_ep_job_t *ptr_job;
+
+ ptr_job = udd_ep_get_job(ep);
+ ep_num = ep & USB_EP_ADDR_MASK;
+
+ ep_size = ptr_job->ep_size;
+ /* Update number of data transferred */
+ nb_trans = ep_callback_para->received_bytes;
+
+ /* Can be necessary to copy data receive from cache buffer to user buffer */
+ if (ptr_job->b_use_out_cache_buffer) {
+ memcpy(&ptr_job->buf[ptr_job->nb_trans], udd_ep_out_cache_buffer[ep_num - 1], ptr_job->buf_size % ep_size);
+ }
+
+ /* Update number of data transferred */
+ ptr_job->nb_trans += nb_trans;
+ if (ptr_job->nb_trans > ptr_job->buf_size) {
+ ptr_job->nb_trans = ptr_job->buf_size;
+ }
+
+ /* If all previous data requested are received and user buffer not full
+ * then need to receive other data */
+ if ((nb_trans == ep_callback_para->out_buffer_size) && (ptr_job->nb_trans != ptr_job->buf_size)) {
+ next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+ if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+ /* The USB hardware support a maximum transfer size
+ * of UDD_ENDPOINT_MAX_TRANS Bytes */
+ next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size);
+ } else {
+ next_trans -= next_trans % ep_size;
+ }
+
+ if (next_trans < ep_size) {
+ /* Use the cache buffer for Bulk or Interrupt size endpoint */
+ ptr_job->b_use_out_cache_buffer = true;
+ usb_device_endpoint_read_buffer_job(&usb_device,ep_num,udd_ep_out_cache_buffer[ep_num - 1],ep_size);
+ } else {
+ usb_device_endpoint_read_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
+ }
+ return;
+ }
+
+ /* Job complete then call callback */
+ ptr_job->busy = false;
+ if (NULL != ptr_job->call_trans) {
+ ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
+ }
+}
+
+/**
+ * \brief Endpoint Transfer Complete callback function, to do the next transfer depends on the direction(IN or OUT)
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ep_transfer_process(struct usb_module *module_inst, void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+ udd_ep_id_t ep = ep_callback_para->endpoint_address;
+
+ if (ep & USB_EP_DIR_IN) {
+ udd_ep_trans_in_next(pointer);
+ } else {
+ udd_ep_trans_out_next(pointer);
+ }
+}
+
+void udd_ep_abort(udd_ep_id_t ep)
+{
+ udd_ep_job_t *ptr_job;
+
+ usb_device_endpoint_abort_job(&usb_device, ep);
+
+ /* Job complete then call callback */
+ ptr_job = udd_ep_get_job(ep);
+ if (!ptr_job->busy) {
+ return;
+ }
+ ptr_job->busy = false;
+ if (NULL != ptr_job->call_trans) {
+ /* It can be a Transfer or stall callback */
+ ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, ptr_job->nb_trans, ep);
+ }
+}
+
+bool udd_is_high_speed(void)
+{
+#if SAMD21 || SAMR21 || SAMD11
+ return false;
+#endif
+}
+
+uint16_t udd_get_frame_number(void)
+{
+ return usb_device_get_frame_number(&usb_device);
+}
+
+uint16_t udd_get_micro_frame_number(void)
+{
+ return usb_device_get_micro_frame_number(&usb_device);
+}
+
+void udd_ep_free(udd_ep_id_t ep)
+{
+ struct usb_device_endpoint_config config_ep;
+ usb_device_endpoint_get_config_defaults(&config_ep);
+
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+ udd_ep_abort(ep);
+
+ config_ep.ep_address = ep;
+ config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_DISABLE;
+ usb_device_endpoint_set_config(&usb_device, &config_ep);
+ usb_device_endpoint_unregister_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+ usb_device_endpoint_disable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+}
+
+bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize)
+{
+ struct usb_device_endpoint_config config_ep;
+ usb_device_endpoint_get_config_defaults(&config_ep);
+
+ config_ep.ep_address = ep;
+
+ if(MaxEndpointSize <= 8) {
+ config_ep.ep_size = USB_ENDPOINT_8_BYTE;
+ } else if(MaxEndpointSize <= 16) {
+ config_ep.ep_size = USB_ENDPOINT_16_BYTE;
+ } else if(MaxEndpointSize <= 32) {
+ config_ep.ep_size = USB_ENDPOINT_32_BYTE;
+ } else if(MaxEndpointSize <= 64) {
+ config_ep.ep_size = USB_ENDPOINT_64_BYTE;
+ } else if(MaxEndpointSize <= 128) {
+ config_ep.ep_size = USB_ENDPOINT_128_BYTE;
+ } else if(MaxEndpointSize <= 256) {
+ config_ep.ep_size = USB_ENDPOINT_256_BYTE;
+ } else if(MaxEndpointSize <= 512) {
+ config_ep.ep_size = USB_ENDPOINT_512_BYTE;
+ } else if(MaxEndpointSize <= 1023) {
+ config_ep.ep_size = USB_ENDPOINT_1023_BYTE;
+ } else {
+ return false;
+ }
+ udd_ep_job_t *ptr_job = udd_ep_get_job(ep);
+ ptr_job->ep_size = MaxEndpointSize;
+
+ bmAttributes = bmAttributes & USB_EP_TYPE_MASK;
+
+ /* Check endpoint type */
+ if(USB_EP_TYPE_ISOCHRONOUS == bmAttributes) {
+ config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS;
+ } else if (USB_EP_TYPE_BULK == bmAttributes) {
+ config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_BULK;
+ } else if (USB_EP_TYPE_INTERRUPT == bmAttributes) {
+ config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_INTERRUPT;
+ } else {
+ return false;
+ }
+
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+ if (STATUS_OK != usb_device_endpoint_set_config(&usb_device, &config_ep)) {
+ return false;
+ }
+ usb_device_endpoint_register_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,udd_ep_transfer_process);
+ usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+ usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
+
+ return true;
+}
+
+bool udd_ep_is_halted(udd_ep_id_t ep)
+{
+ return usb_device_endpoint_is_halted(&usb_device, ep);
+}
+
+bool udd_ep_set_halt(udd_ep_id_t ep)
+{
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+ if (USB_DEVICE_MAX_EP < ep_num) {
+ return false;
+ }
+
+ usb_device_endpoint_set_halt(&usb_device, ep);
+
+ udd_ep_abort(ep);
+ return true;
+}
+
+bool udd_ep_clear_halt(udd_ep_id_t ep)
+{
+ udd_ep_job_t *ptr_job;
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+ if (USB_DEVICE_MAX_EP < ep_num) {
+ return false;
+ }
+ ptr_job = udd_ep_get_job(ep);
+
+ usb_device_endpoint_clear_halt(&usb_device, ep);
+
+ /* If a job is register on clear halt action then execute callback */
+ if (ptr_job->busy == true) {
+ ptr_job->busy = false;
+ ptr_job->call_nohalt();
+ }
+
+ return true;
+}
+
+bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback)
+{
+ udd_ep_id_t ep_num;
+ udd_ep_job_t *ptr_job;
+
+ ep_num = ep & USB_EP_ADDR_MASK;
+ if (USB_DEVICE_MAX_EP < ep_num) {
+ return false;
+ }
+
+ ptr_job = udd_ep_get_job(ep);
+ if (ptr_job->busy == true) {
+ return false; /* Job already on going */
+ }
+
+ /* Wait clear halt endpoint */
+ if (usb_device_endpoint_is_halted(&usb_device, ep)) {
+ /* Endpoint halted then registers the callback */
+ ptr_job->busy = true;
+ ptr_job->call_nohalt = callback;
+ return true;
+ } else if (usb_device_endpoint_is_configured(&usb_device, ep)) {
+ callback(); /* Endpoint not halted then call directly callback */
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/**
+ * \brief Control Endpoint stall sending data
+ */
+static void udd_ctrl_stall_data(void)
+{
+ udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+
+ usb_device_endpoint_set_halt(&usb_device, USB_EP_DIR_IN);
+ usb_device_endpoint_clear_halt(&usb_device, USB_EP_DIR_OUT);
+}
+
+bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t * buf, iram_size_t buf_size, udd_callback_trans_t callback)
+{
+ udd_ep_id_t ep_num;
+ udd_ep_job_t *ptr_job;
+ irqflags_t flags;
+
+ ep_num = ep & USB_EP_ADDR_MASK;
+
+ if ((USB_DEVICE_MAX_EP < ep_num) || (udd_ep_is_halted(ep))) {
+ return false;
+ }
+
+ ptr_job = udd_ep_get_job(ep);
+
+ flags = cpu_irq_save();
+ if (ptr_job->busy == true) {
+ cpu_irq_restore(flags);
+ return false; /* Job already on going */
+ }
+ ptr_job->busy = true;
+ cpu_irq_restore(flags);
+
+ /* No job running, set up a new one */
+ ptr_job->buf = buf;
+ ptr_job->buf_size = buf_size;
+ ptr_job->nb_trans = 0;
+ ptr_job->call_trans = callback;
+ ptr_job->b_shortpacket = b_shortpacket;
+ ptr_job->b_use_out_cache_buffer = false;
+
+ /* Initialize value to simulate a empty transfer */
+ uint16_t next_trans;
+
+ if (ep & USB_EP_DIR_IN) {
+ if (0 != ptr_job->buf_size) {
+ next_trans = ptr_job->buf_size;
+ if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+ next_trans = UDD_ENDPOINT_MAX_TRANS -
+ (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
+ }
+ ptr_job->b_shortpacket = ptr_job->b_shortpacket &&
+ (0 == (next_trans % ptr_job->ep_size));
+ } else if (true == ptr_job->b_shortpacket) {
+ ptr_job->b_shortpacket = false; /* avoid to send zero length packet again */
+ next_trans = 0;
+ } else {
+ ptr_job->busy = false;
+ if (NULL != ptr_job->call_trans) {
+ ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
+ }
+ return true;
+ }
+ return (STATUS_OK ==
+ usb_device_endpoint_write_buffer_job(&usb_device,
+ ep_num,&ptr_job->buf[0],next_trans));
+ } else {
+ if (0 != ptr_job->buf_size) {
+ next_trans = ptr_job->buf_size;
+ if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
+ /* The USB hardware support a maximum transfer size
+ * of UDD_ENDPOINT_MAX_TRANS Bytes */
+ next_trans = UDD_ENDPOINT_MAX_TRANS -
+ (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
+ } else {
+ next_trans -= next_trans % ptr_job->ep_size;
+ }
+ if (next_trans < ptr_job->ep_size) {
+ ptr_job->b_use_out_cache_buffer = true;
+ return (STATUS_OK ==
+ usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
+ udd_ep_out_cache_buffer[ep_num - 1],
+ ptr_job->ep_size));
+ } else {
+ return (STATUS_OK ==
+ usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
+ &ptr_job->buf[0],next_trans));
+ }
+ } else {
+ ptr_job->busy = false;
+ if (NULL != ptr_job->call_trans) {
+ ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
+ }
+ return true;
+ }
+ }
+}
+
+void udd_set_address(uint8_t address)
+{
+ usb_device_set_address(&usb_device,address);
+}
+
+uint8_t udd_getaddress(void)
+{
+ return usb_device_get_address(&usb_device);
+}
+
+void udd_send_remotewakeup(void)
+{
+ uint32_t try = 5;
+ udd_wait_clock_ready();
+ udd_sleep_mode(UDD_STATE_IDLE);
+ while(2 != usb_get_state_machine_status(&usb_device) && try --) {
+ usb_device_send_remote_wake_up(&usb_device);
+ }
+}
+
+void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size )
+{
+ udd_g_ctrlreq.payload = payload;
+ udd_g_ctrlreq.payload_size = payload_size;
+}
+
+/**
+ * \brief Control Endpoint translate the data in buffer into Device Request Struct
+ */
+static void udd_ctrl_fetch_ram(void)
+{
+ udd_g_ctrlreq.req.bmRequestType = udd_ctrl_buffer[0];
+ udd_g_ctrlreq.req.bRequest = udd_ctrl_buffer[1];
+ udd_g_ctrlreq.req.wValue = ((uint16_t)(udd_ctrl_buffer[3]) << 8) + udd_ctrl_buffer[2];
+ udd_g_ctrlreq.req.wIndex = ((uint16_t)(udd_ctrl_buffer[5]) << 8) + udd_ctrl_buffer[4];
+ udd_g_ctrlreq.req.wLength = ((uint16_t)(udd_ctrl_buffer[7]) << 8) + udd_ctrl_buffer[6];
+}
+
+/**
+ * \brief Control Endpoint send out zero length packet
+ */
+static void udd_ctrl_send_zlp_in(void)
+{
+ udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP;
+ usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
+ usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload,0);
+}
+
+/**
+ * \brief Process control endpoint IN transaction
+ */
+static void udd_ctrl_in_sent(void)
+{
+ static bool b_shortpacket = false;
+ uint16_t nb_remain;
+
+ nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
+
+ if (0 == nb_remain) {
+ /* All content of current buffer payload are sent Update number of total data sending by previous payload buffer */
+ udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
+ if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_nb_trans) || b_shortpacket) {
+ /* All data requested are transferred or a short packet has been sent, then it is the end of data phase.
+ * Generate an OUT ZLP for handshake phase */
+ udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
+ usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
+ return;
+ }
+ /* Need of new buffer because the data phase is not complete */
+ if ((!udd_g_ctrlreq.over_under_run) || (!udd_g_ctrlreq.over_under_run())) {
+ /* Under run then send zlp on IN
+ * Here nb_remain=0, this allows to send a IN ZLP */
+ } else {
+ /* A new payload buffer is given */
+ udd_ctrl_payload_nb_trans = 0;
+ nb_remain = udd_g_ctrlreq.payload_size;
+ }
+ }
+
+ /* Continue transfer and send next data */
+ if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) {
+ nb_remain = USB_DEVICE_EP_CTRL_SIZE;
+ b_shortpacket = false;
+ } else {
+ b_shortpacket = true;
+ }
+
+ /* Link payload buffer directly on USB hardware */
+ usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans,nb_remain);
+
+ udd_ctrl_payload_nb_trans += nb_remain;
+}
+
+/**
+ * \brief Process control endpoint OUT transaction
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ctrl_out_received(void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+ uint16_t nb_data;
+ nb_data = ep_callback_para->received_bytes; /* Read data received during OUT phase */
+
+ if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_nb_trans + nb_data)) {
+ /* Payload buffer too small */
+ nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
+ }
+
+ memcpy((uint8_t *) (udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans), udd_ctrl_buffer, nb_data);
+ udd_ctrl_payload_nb_trans += nb_data;
+
+ if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) || \
+ (udd_g_ctrlreq.req.wLength <= (udd_ctrl_prev_payload_nb_trans + udd_ctrl_payload_nb_trans))) {
+ /* End of reception because it is a short packet
+ * or all data are transferred */
+
+ /* Before send ZLP, call intermediate callback
+ * in case of data receive generate a stall */
+ udd_g_ctrlreq.payload_size = udd_ctrl_payload_nb_trans;
+ if (NULL != udd_g_ctrlreq.over_under_run) {
+ if (!udd_g_ctrlreq.over_under_run()) {
+ /* Stall ZLP */
+ udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+ /* Stall all packets on IN & OUT control endpoint */
+ udd_ep_set_halt(0);
+ /* Ack reception of OUT to replace NAK by a STALL */
+ return;
+ }
+ }
+ /* Send IN ZLP to ACK setup request */
+ udd_ctrl_send_zlp_in();
+ return;
+ }
+
+ if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_nb_trans) {
+ /* Overrun then request a new payload buffer */
+ if (!udd_g_ctrlreq.over_under_run) {
+ /* No callback available to request a new payload buffer
+ * Stall ZLP */
+ udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+ /* Stall all packets on IN & OUT control endpoint */
+ udd_ep_set_halt(0);
+ return;
+ }
+ if (!udd_g_ctrlreq.over_under_run()) {
+ /* No new payload buffer delivered
+ * Stall ZLP */
+ udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+ /* Stall all packets on IN & OUT control endpoint */
+ udd_ep_set_halt(0);
+ return;
+ }
+ /* New payload buffer available
+ * Update number of total data received */
+ udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
+
+ /* Reinitialize reception on payload buffer */
+ udd_ctrl_payload_nb_trans = 0;
+ }
+ usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+}
+
+/**
+ * \internal
+ * \brief Endpoint 0 (control) SETUP received callback
+ * \param[in] module_inst pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void _usb_ep0_on_setup(struct usb_module *module_inst, void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+ if (UDD_EPCTRL_SETUP != udd_ep_control_state) {
+ if (NULL != udd_g_ctrlreq.callback) {
+ udd_g_ctrlreq.callback();
+ }
+ udd_ep_control_state = UDD_EPCTRL_SETUP;
+ }
+ if ( 8 != ep_callback_para->received_bytes) {
+ udd_ctrl_stall_data();
+ return;
+ } else {
+ udd_ctrl_fetch_ram();
+ if (false == udc_process_setup()) {
+ udd_ctrl_stall_data();
+ return;
+ } else if (Udd_setup_is_in()) {
+ udd_ctrl_prev_payload_nb_trans = 0;
+ udd_ctrl_payload_nb_trans = 0;
+ udd_ep_control_state = UDD_EPCTRL_DATA_IN;
+ usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+ udd_ctrl_in_sent();
+ } else {
+ if(0 == udd_g_ctrlreq.req.wLength) {
+ udd_ctrl_send_zlp_in();
+ return;
+ } else {
+ udd_ctrl_prev_payload_nb_trans = 0;
+ udd_ctrl_payload_nb_trans = 0;
+ udd_ep_control_state = UDD_EPCTRL_DATA_OUT;
+ /* Initialize buffer size and enable OUT bank */
+ usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+ }
+ }
+ }
+}
+
+/**
+ * \brief Control Endpoint Process when underflow condition has occurred
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ctrl_underflow(void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+ if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) {
+ /* Host want to stop OUT transaction
+ * then stop to wait OUT data phase and wait IN ZLP handshake */
+ udd_ctrl_send_zlp_in();
+ } else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) {
+ /* A OUT handshake is waiting by device,
+ * but host want extra IN data then stall extra IN data */
+ usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
+ }
+}
+
+/**
+ * \brief Control Endpoint Process when overflow condition has occurred
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void udd_ctrl_overflow(void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+ if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) {
+ /* Host want to stop IN transaction
+ * then stop to wait IN data phase and wait OUT ZLP handshake */
+ udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
+ } else if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) {
+ /* A IN handshake is waiting by device,
+ * but host want extra OUT data then stall extra OUT data and following status stage */
+ usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
+ }
+}
+
+/**
+ * \internal
+ * \brief Control endpoint transfer fail callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void _usb_ep0_on_tansfer_fail(struct usb_module *module_inst, void* pointer)
+{
+ struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+ if(ep_callback_para->endpoint_address & USB_EP_DIR_IN) {
+ udd_ctrl_underflow(pointer);
+ } else {
+ udd_ctrl_overflow(pointer);
+ }
+}
+
+/**
+ * \internal
+ * \brief Control endpoint transfer complete callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer.
+ */
+static void _usb_ep0_on_tansfer_ok(struct usb_module *module_inst, void * pointer)
+{
+ if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) { /* handshake Out for status stage */
+ udd_ctrl_out_received(pointer);
+ } else if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) { /* handshake In for status stage */
+ udd_ctrl_in_sent();
+ } else {
+ if (NULL != udd_g_ctrlreq.callback) {
+ udd_g_ctrlreq.callback();
+ }
+ udd_ep_control_state = UDD_EPCTRL_SETUP;
+ }
+}
+
+/**
+ * \brief Enable Control Endpoint
+ * \param[in] module_inst Pointer to USB module instance
+ */
+static void udd_ctrl_ep_enable(struct usb_module *module_inst)
+{
+ /* USB Device Endpoint0 Configuration */
+ struct usb_device_endpoint_config config_ep0;
+
+ usb_device_endpoint_get_config_defaults(&config_ep0);
+ config_ep0.ep_size = (enum usb_endpoint_size)(32 - clz(((uint32_t)Min(Max(USB_DEVICE_EP_CTRL_SIZE, 8), 1024) << 1) - 1) - 1 - 3);
+ usb_device_endpoint_set_config(module_inst,&config_ep0);
+
+ usb_device_endpoint_setup_buffer_job(module_inst,udd_ctrl_buffer);
+
+ usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, _usb_ep0_on_setup );
+ usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,_usb_ep0_on_tansfer_ok );
+ usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,_usb_ep0_on_tansfer_fail );
+ usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP);
+ usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+ usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
+
+#ifdef USB_DEVICE_LPM_SUPPORT
+ // Enable LPM feature
+ usb_device_set_lpm_mode(module_inst, USB_DEVICE_LPM_ACK);
+#endif
+
+ udd_ep_control_state = UDD_EPCTRL_SETUP;
+}
+
+/**
+ * \internal
+ * \brief Control endpoint Suspend callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_suspend(struct usb_module *module_inst, void *pointer)
+{
+ usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+ udd_sleep_mode(UDD_STATE_SUSPEND);
+#ifdef UDC_SUSPEND_EVENT
+ UDC_SUSPEND_EVENT();
+#endif
+}
+
+#ifdef USB_DEVICE_LPM_SUPPORT
+static void _usb_device_lpm_suspend(struct usb_module *module_inst, void *pointer)
+{
+ dbg_print("LPM_SUSP\n");
+
+ uint32_t *lpm_wakeup_enable;
+ lpm_wakeup_enable = (uint32_t *)pointer;
+
+ usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+ usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+
+//#warning Here the sleep mode must be choose to have a DFLL startup time < bmAttribut.BESL
+ udd_sleep_mode(UDD_STATE_SUSPEND_LPM); // Enter in LPM SUSPEND mode
+ if ((*lpm_wakeup_enable)) {
+ UDC_REMOTEWAKEUP_LPM_ENABLE();
+ }
+ if (!(*lpm_wakeup_enable)) {
+ UDC_REMOTEWAKEUP_LPM_DISABLE();
+ }
+ UDC_SUSPEND_LPM_EVENT();
+}
+#endif
+
+/**
+ * \internal
+ * \brief Control endpoint SOF callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_sof_notify(struct usb_module *module_inst, void *pointer)
+{
+ udc_sof_notify();
+#ifdef UDC_SOF_EVENT
+ UDC_SOF_EVENT();
+#endif
+}
+
+/**
+ * \internal
+ * \brief Control endpoint Reset callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_bus_reset(struct usb_module *module_inst, void *pointer)
+{
+ // Reset USB Device Stack Core
+ udc_reset();
+ usb_device_set_address(module_inst,0);
+ udd_ctrl_ep_enable(module_inst);
+}
+
+/**
+ * \internal
+ * \brief Control endpoint Wakeup callback function
+ * \param[in] module_inst Pointer to USB module instance
+ * \param[in] pointer Pointer to the callback parameter from driver layer.
+ */
+static void _usb_on_wakeup(struct usb_module *module_inst, void *pointer)
+{
+ udd_wait_clock_ready();
+
+ usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+#ifdef USB_DEVICE_LPM_SUPPORT
+ usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+#endif
+ udd_sleep_mode(UDD_STATE_IDLE);
+#ifdef UDC_RESUME_EVENT
+ UDC_RESUME_EVENT();
+#endif
+}
+
+void udd_detach(void)
+{
+ usb_device_detach(&usb_device);
+ udd_sleep_mode(UDD_STATE_SUSPEND);
+}
+
+void udd_attach(void)
+{
+ udd_sleep_mode(UDD_STATE_IDLE);
+ usb_device_attach(&usb_device);
+
+ usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND, _usb_on_suspend);
+ usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SOF, _usb_on_sof_notify);
+ usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_RESET, _usb_on_bus_reset);
+ usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP, _usb_on_wakeup);
+
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SOF);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_RESET);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+#ifdef USB_DEVICE_LPM_SUPPORT
+ usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
+ usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+#endif
+}
+
+#if USB_VBUS_EIC
+/**
+ * \name USB VBUS PAD management
+ *
+ * @{
+ */
+
+ /** Check if USB VBus is available */
+# define is_usb_vbus_high() port_pin_get_input_level(USB_VBUS_PIN)
+
+/**
+ * \internal
+ * \brief USB VBUS pin change handler
+ */
+static void _uhd_vbus_handler(void)
+{
+ extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+# ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
+ if (is_usb_vbus_high()) {
+ udd_attach();
+ } else {
+ udd_detach();
+ }
+# endif
+# ifdef UDC_VBUS_EVENT
+ UDC_VBUS_EVENT(is_usb_vbus_high());
+# endif
+ extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+}
+
+/**
+ * \internal
+ * \brief USB VBUS pin configuration
+ */
+static void _usb_vbus_config(void)
+{
+
+ /* Initialize EIC for vbus checking */
+ struct extint_chan_conf eint_chan_conf;
+ extint_chan_get_config_defaults(&eint_chan_conf);
+
+ eint_chan_conf.gpio_pin = USB_VBUS_PIN;
+ eint_chan_conf.gpio_pin_mux = USB_VBUS_EIC_MUX;
+ eint_chan_conf.gpio_pin_pull = EXTINT_PULL_NONE;
+ eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+ eint_chan_conf.filter_input_signal = true;
+
+ extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+ extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
+ extint_register_callback(_uhd_vbus_handler,
+ USB_VBUS_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+ extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+}
+/** @} */
+#endif
+
+bool udd_include_vbus_monitoring(void)
+{
+#if USB_VBUS_EIC
+ return true;
+#else
+ return false;
+#endif
+}
+
+void udd_enable(void)
+{
+ irqflags_t flags;
+
+ /* To avoid USB interrupt before end of initialization */
+ flags = cpu_irq_save();
+
+#if USB_ID_EIC
+ if (usb_dual_enable()) {
+ /* The current mode has been started by otg_dual_enable() */
+ cpu_irq_restore(flags);
+ return;
+ }
+#endif
+ struct usb_config config_usb;
+
+ /* USB Module configuration */
+ usb_get_config_defaults(&config_usb);
+ config_usb.source_generator = UDD_CLOCK_GEN;
+ usb_init(&usb_device, USB, &config_usb);
+
+ /* USB Module Enable */
+ usb_enable(&usb_device);
+
+ /* Check clock after enable module, request the clock */
+ udd_wait_clock_ready();
+
+ udd_sleep_mode(UDD_STATE_SUSPEND);
+
+#if USB_VBUS_EIC
+ _usb_vbus_config();
+ if (is_usb_vbus_high()) {
+ /* USB Attach */
+ _uhd_vbus_handler();
+ }
+#else
+ // No VBus detect, assume always high
+# ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
+ udd_attach();
+# endif
+#endif
+
+ cpu_irq_restore(flags);
+}
+
+void udd_disable(void)
+{
+ irqflags_t flags;
+
+ udd_detach();
+
+ udd_sleep_mode(UDD_STATE_OFF);
+
+ flags = cpu_irq_save();
+ usb_dual_disable();
+ cpu_irq_restore(flags);
+}
+/** @} */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.c
new file mode 100755
index 0000000000000000000000000000000000000000..0eab4b33ae0023e2fff2d2447742150736052c26
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.c
@@ -0,0 +1,175 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Dual Role driver file.
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include "usb_dual.h"
+
+#ifndef UDD_ENABLE
+# define udc_start()
+# define udc_stop()
+#else
+#include <udc.h>
+#endif
+
+#ifndef UHD_ENABLE
+# define uhc_start(void)
+# define uhc_stop(b_id_stop)
+#else
+#include <uhc.h>
+#endif
+
+/* State of USB dual role initialization */
+static bool _initialized = false;
+
+#define _usb_is_id_device() port_pin_get_input_level(USB_ID_PIN)
+
+#if USB_ID_EIC
+static void usb_id_handler(void);
+
+/**
+ * \name USB ID PAD management
+ *
+ * @{
+ */
+
+/**
+ * USB ID pin configuration
+ */
+static void usb_id_config(void)
+{
+ struct extint_chan_conf eint_chan_conf;
+ extint_chan_get_config_defaults(&eint_chan_conf);
+
+ eint_chan_conf.gpio_pin = USB_ID_PIN;
+ eint_chan_conf.gpio_pin_mux = USB_ID_EIC_MUX;
+ eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+ eint_chan_conf.filter_input_signal = true;
+
+ extint_chan_disable_callback(USB_ID_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+ extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf);
+ extint_register_callback(usb_id_handler,
+ USB_ID_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+ extint_chan_enable_callback(USB_ID_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+}
+
+/**
+ * USB ID pin change handler
+ */
+static void usb_id_handler(void)
+{
+ extint_chan_disable_callback(USB_ID_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+ if (_usb_is_id_device()) {
+ uhc_stop(false);
+ UHC_MODE_CHANGE(false);
+ udc_start();
+ } else {
+ udc_stop();
+ UHC_MODE_CHANGE(true);
+ uhc_start();
+ }
+ extint_chan_enable_callback(USB_ID_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+}
+#endif
+/** @} */
+
+/**
+ * \brief Initialize the USB peripheral and set right role according to ID pin
+ *
+ * \return \c true if the ID pin management has been started, otherwise \c false.
+ */
+bool usb_dual_enable(void)
+{
+ if (_initialized) {
+ return false; // Dual role already initialized
+ }
+
+#if USB_ID_EIC
+ _initialized = true;
+
+ struct port_config pin_conf;
+ port_get_config_defaults(&pin_conf);
+
+ /* Set USB ID Pin as inputs */
+ pin_conf.direction = PORT_PIN_DIR_INPUT;
+ pin_conf.input_pull = PORT_PIN_PULL_UP;
+ port_pin_set_config(USB_ID_PIN, &pin_conf);
+
+ usb_id_config();
+ if (_usb_is_id_device()) {
+ UHC_MODE_CHANGE(false);
+ udc_start();
+ } else {
+ UHC_MODE_CHANGE(true);
+ uhc_start();
+ }
+
+ /**
+ * End of host or device startup,
+ * the current mode selected is already started now
+ */
+ return true; // ID pin management has been enabled
+#else
+ return false; // ID pin management has not been enabled
+#endif
+}
+
+/**
+ * \brief Deinitialize the dual role driver
+ */
+void usb_dual_disable(void)
+{
+ if (!_initialized) {
+ return; // Dual role not initialized
+ }
+ _initialized = false;
+
+#if USB_ID_EIC
+ extint_chan_disable_callback(USB_ID_EIC_LINE,
+ EXTINT_CALLBACK_TYPE_DETECT);
+#endif
+}
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.h
new file mode 100755
index 0000000000000000000000000000000000000000..8399433a1ba6615a1fcd8ee5c2bad00f00379c89
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.h
@@ -0,0 +1,110 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Dual Role driver header file.
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _USB_DUAL_H_
+#define _USB_DUAL_H_
+
+#include "compiler.h"
+#include "preprocessor.h"
+
+/* Get USB pads pins configuration in board configuration */
+#include "conf_board.h"
+#include "board.h"
+//#include <extint.h>
+#include "port.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_dual_group USB dual role driver
+ * USB low-level driver for dual role features
+ *
+ * @{
+ */
+
+bool usb_dual_enable(void);
+void usb_dual_disable(void);
+
+/**
+ * @name USB ID pin management
+ *
+ * The ID pin come from the USB connector (A and B receptable) and
+ * allows to select the USB mode between host or device.
+ * The ID pin can be managed through EIC pin.
+ * This feature is optional, and it is enabled if USB_ID_PIN
+ * is defined in board.h and CONF_BOARD_USB_ID_DETECT defined in
+ * conf_board.h.
+*
+* @{
+*/
+#ifdef BOOTLOADER_USES_HOST
+#define USB_ID_DETECT (defined(CONF_BOARD_USB_ID_DETECT))
+#define USB_ID_EIC (defined(USB_ID_PIN) && USB_ID_DETECT)
+/** @} */
+
+/**
+ * @name USB Vbus management
+ *
+ * The VBus line can be monitored through a EIC pin and
+ * a basic resistor voltage divider.
+ * This feature is optional, and it is enabled if USB_VBUS_PIN
+ * is defined in board.h and CONF_BOARD_USB_VBUS_DETECT defined in
+ * conf_board.h.
+ *
+ * @{
+ */
+#define USB_VBUS_DETECT (defined(CONF_BOARD_USB_VBUS_DETECT))
+#define USB_VBUS_EIC (defined(USB_VBUS_PIN) && USB_VBUS_DETECT)
+#endif //BOOTLOADER_USES_HOST
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _USB_DUAL_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/usb.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/usb.c
new file mode 100755
index 0000000000000000000000000000000000000000..dd21b8d0fc1565a7ef144d7c9b3e00ba9eca9a3d
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/usb.c
@@ -0,0 +1,2066 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Driver.
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <string.h>
+#include "usb.h"
+
+/** Fields definition from a LPM TOKEN */
+#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0)
+#define USB_LPM_ATTRIBUT_BESL_MASK (0xF << 4)
+#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8)
+#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0)
+#define USB_LPM_ATTRIBUT_BESL(value) ((value & 0xF) << 4)
+#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8)
+#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1)
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define USB_EP_ADDR_MASK 0x0f
+
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define USB_EP_DIR_IN 0x80
+
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define USB_EP_DIR_OUT 0x00
+
+#if SAMD21 || SAMD11
+/**
+ * \name Macros for USB device those are not realized in head file
+ *
+ * @{
+ */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 USB_DEVICE_EPINTENCLR_TRCPT(1)
+#define USB_DEVICE_EPINTENCLR_TRCPT1 USB_DEVICE_EPINTENCLR_TRCPT(2)
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 USB_DEVICE_EPINTENCLR_TRFAIL(1)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 USB_DEVICE_EPINTENCLR_TRFAIL(2)
+#define USB_DEVICE_EPINTENCLR_STALL0 USB_DEVICE_EPINTENCLR_STALL(1)
+#define USB_DEVICE_EPINTENCLR_STALL1 USB_DEVICE_EPINTENCLR_STALL(2)
+
+#define USB_DEVICE_EPINTENSET_TRCPT0 USB_DEVICE_EPINTENSET_TRCPT(1)
+#define USB_DEVICE_EPINTENSET_TRCPT1 USB_DEVICE_EPINTENSET_TRCPT(2)
+#define USB_DEVICE_EPINTENSET_TRFAIL0 USB_DEVICE_EPINTENSET_TRFAIL(1)
+#define USB_DEVICE_EPINTENSET_TRFAIL1 USB_DEVICE_EPINTENSET_TRFAIL(2)
+#define USB_DEVICE_EPINTENSET_STALL0 USB_DEVICE_EPINTENSET_STALL(1)
+#define USB_DEVICE_EPINTENSET_STALL1 USB_DEVICE_EPINTENSET_STALL(2)
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0 USB_DEVICE_EPINTFLAG_TRCPT(1)
+#define USB_DEVICE_EPINTFLAG_TRCPT1 USB_DEVICE_EPINTFLAG_TRCPT(2)
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 USB_DEVICE_EPINTFLAG_TRFAIL(1)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 USB_DEVICE_EPINTFLAG_TRFAIL(2)
+#define USB_DEVICE_EPINTFLAG_STALL0 USB_DEVICE_EPINTFLAG_STALL(1)
+#define USB_DEVICE_EPINTFLAG_STALL1 USB_DEVICE_EPINTFLAG_STALL(2)
+
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 USB_DEVICE_EPSTATUSSET_STALLRQ(1)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 USB_DEVICE_EPSTATUSSET_STALLRQ(2)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 USB_DEVICE_EPSTATUSCLR_STALLRQ(1)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 USB_DEVICE_EPSTATUSCLR_STALLRQ(2)
+/** @} */
+#endif
+
+/**
+ * \name USB SRAM data containing pipe descriptor table
+ * The content of the USB SRAM can be :
+ * - modified by USB hardware interface to update pipe status.
+ * Thereby, it is read by software.
+ * - modified by USB software to control pipe.
+ * Thereby, it is read by hardware.
+ * This data section is volatile.
+ *
+ * @{
+ */
+COMPILER_PACK_SET(1)
+COMPILER_WORD_ALIGNED
+union {
+ UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
+ UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
+} usb_descriptor_table;
+COMPILER_PACK_RESET()
+/** @} */
+
+/**
+ * \brief Local USB module instance
+ */
+static struct usb_module *_usb_instances;
+
+#if !SAMD11
+/**
+ * \brief Host pipe callback structure variable
+ */
+static struct usb_pipe_callback_parameter pipe_callback_para;
+#endif
+
+/* Device LPM callback variable */
+static uint32_t device_callback_lpm_wakeup_enable;
+
+/**
+ * \brief Device endpoint callback parameter variable, used to transfer info to UDD wrapper layer
+ */
+static struct usb_endpoint_callback_parameter ep_callback_para;
+
+/**
+ * \internal USB Device IRQ Mask Bits Map
+ */
+static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = {
+ USB_DEVICE_INTFLAG_SOF,
+ USB_DEVICE_INTFLAG_EORST,
+ USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
+ USB_DEVICE_INTFLAG_RAMACER,
+ USB_DEVICE_INTFLAG_SUSPEND,
+ USB_DEVICE_INTFLAG_LPMNYET,
+ USB_DEVICE_INTFLAG_LPMSUSP,
+};
+
+/**
+ * \internal USB Device IRQ Mask Bits Map
+ */
+static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = {
+ USB_DEVICE_EPINTFLAG_TRCPT_Msk,
+ USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
+ USB_DEVICE_EPINTFLAG_RXSTP,
+ USB_DEVICE_EPINTFLAG_STALL_Msk
+};
+
+#if !SAMD11
+/**
+ * \brief Bit mask for pipe job busy status
+ */
+uint32_t host_pipe_job_busy_status = 0;
+
+/**
+ * \brief Registers a USB host callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ * \param[in] callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK The callback was registered successfully.
+ */
+enum status_code usb_host_register_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type,
+ usb_host_callback_t callback_func)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(callback_func);
+
+ /* Register callback function */
+ module_inst->host_callback[callback_type] = callback_func;
+
+ /* Set the bit corresponding to the callback_type */
+ module_inst->host_registered_callback_mask |= (1 << callback_type);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB host callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK The callback was unregistered successfully.
+ */
+enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+
+ /* Unregister callback function */
+ module_inst->host_callback[callback_type] = NULL;
+
+ /* Clear the bit corresponding to the callback_type */
+ module_inst->host_registered_callback_mask &= ~(1 << callback_type);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB host callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host generate callback events.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully.
+ */
+enum status_code usb_host_enable_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Enable callback */
+ module_inst->host_enabled_callback_mask |= (1 << callback_type);
+
+ if (callback_type == USB_HOST_CALLBACK_SOF) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+ }
+ if (callback_type == USB_HOST_CALLBACK_RESET) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+ }
+ if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+ }
+ if (callback_type == USB_HOST_CALLBACK_DNRSM) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+ }
+ if (callback_type == USB_HOST_CALLBACK_UPRSM) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+ }
+ if (callback_type == USB_HOST_CALLBACK_RAMACER) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+ }
+ if (callback_type == USB_HOST_CALLBACK_CONNECT) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+ }
+ if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
+ module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB host callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK The callback was disabled successfully.
+ */
+enum status_code usb_host_disable_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Disable callback */
+ module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
+
+ if (callback_type == USB_HOST_CALLBACK_SOF) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
+ }
+ if (callback_type == USB_HOST_CALLBACK_RESET) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
+ }
+ if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
+ }
+ if (callback_type == USB_HOST_CALLBACK_DNRSM) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
+ }
+ if (callback_type == USB_HOST_CALLBACK_UPRSM) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
+ }
+ if (callback_type == USB_HOST_CALLBACK_RAMACER) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
+ }
+ if (callback_type == USB_HOST_CALLBACK_CONNECT) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
+ }
+ if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
+ module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an USB host pipe configuration structure to defaults.
+ *
+ * Initializes a given USB host pipe configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li device address is 0
+ * \li endpoint address is 0
+ * \li pipe type is control
+ * \li interval is 0
+ * \li pipe size is 8
+ *
+ * \param[out] ep_config Configuration structure to initialize to default values
+ */
+void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
+{
+ /* Sanity check arguments */
+ Assert(ep_config);
+ /* Write default config to config struct */
+ ep_config->device_address = 0;
+ ep_config->endpoint_address = 0;
+ ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+ ep_config->binterval = 0;
+ ep_config->size = 8;
+}
+
+/**
+ * \brief Writes an USB host pipe configuration to the hardware module.
+ *
+ * Writes out a given configuration of an USB host pipe
+ * configuration to the hardware module. If the pipe is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] ep_config Configuration settings for the pipe
+ *
+ * \return Status of the host pipe configuration operation.
+ * \retval STATUS_OK The host pipe was configured successfully.
+ */
+enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
+ struct usb_host_pipe_config *ep_config)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+ Assert(ep_config);
+
+ /* set pipe config */
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
+ module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
+ ep_config->binterval;
+ if (ep_config->endpoint_address == 0) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+ USB_HOST_PIPE_TOKEN_SETUP;
+ } else if (ep_config->endpoint_address & USB_EP_DIR_IN) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+ USB_HOST_PIPE_TOKEN_IN;
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
+ USB_HOST_PSTATUSSET_BK0RDY;
+ } else {
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+ USB_HOST_PIPE_TOKEN_OUT;
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
+ USB_HOST_PSTATUSCLR_BK0RDY;
+ }
+
+ memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
+ sizeof(usb_descriptor_table.usb_pipe_table[0]));
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
+ ep_config->device_address;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
+ ep_config->endpoint_address & USB_EP_ADDR_MASK;
+ if (ep_config->size == 1023) {
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
+ } else {
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
+ (32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
+ }
+
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Gets an USB host pipe configuration.
+ *
+ * Gets out the configuration of an USB host pipe from the hardware module.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[out] ep_config Configuration settings for the pipe
+ *
+ * \return Status of the get host pipe configuration operation.
+ * \retval STATUS_OK The host pipe configuration was read successfully.
+ */
+enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
+ struct usb_host_pipe_config *ep_config)
+{
+ uint32_t size;
+
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+ Assert(ep_config);
+ /* get pipe config from setting register */
+ ep_config->device_address =
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
+ ep_config->endpoint_address =
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
+
+ if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
+ USB_HOST_PIPE_TOKEN_IN) {
+ ep_config->endpoint_address |= USB_EP_DIR_IN;
+ }
+
+ ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
+ ep_config->binterval =
+ module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
+ size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
+ if (size == 0x07) {
+ ep_config->size = 1023;
+ } else {
+ ep_config->size = (8 << size);
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Registers a USB host pipe callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_pipe_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] callback_type Callback type given by an enum
+ * \param[in] callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK The callback was registered successfully.
+ */
+enum status_code usb_host_pipe_register_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type,
+ usb_host_pipe_callback_t callback_func)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(pipe_num < USB_PIPE_NUM);
+ Assert(callback_func);
+
+ /* Register callback function */
+ module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
+
+ /* Set the bit corresponding to the callback_type */
+ module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB host pipe callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK The callback was unregistered successfully.
+ */
+enum status_code usb_host_pipe_unregister_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ /* Unregister callback function */
+ module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
+
+ /* Clear the bit corresponding to the callback_type */
+ module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB host pipe callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host pipe generate callback events.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully.
+ */
+enum status_code usb_host_pipe_enable_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ /* Enable callback */
+ module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
+
+ if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
+ }
+ if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
+ USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
+ }
+ if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+ }
+ if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB host callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK The callback was disabled successfully.
+ */
+enum status_code usb_host_pipe_disable_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ /* Enable callback */
+ module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+ if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
+ }
+ if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
+ USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
+ }
+ if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
+ }
+ if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
+ module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Sends the setup package.
+ *
+ * Sends the setup package.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] buf Pointer to data buffer
+ *
+ * \return Status of the setup operation.
+ * \retval STATUS_OK The setup job was set successfully.
+ * \retval STATUS_BUSY The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
+ uint8_t pipe_num, uint8_t *buf)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ if (host_pipe_job_busy_status & (1 << pipe_num)) {
+ return STATUS_BUSY;
+ }
+
+ /* Set busy status */
+ host_pipe_job_busy_status |= 1 << pipe_num;
+
+ if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+ USB_HOST_PIPE_TYPE_DISABLE) {
+ return STATUS_ERR_NOT_INITIALIZED;
+ }
+
+ /* get pipe config from setting register */
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+ 8;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+ 0;
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+ USB_HOST_PIPE_TOKEN_SETUP;
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+ usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief USB host pipe read job.
+ *
+ * USB host pipe read job by set and start an in transaction transfer.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] buf Pointer to data buffer
+ * \param[in] buf_size Data buffer size
+ * \note The buffer length should not larger than 0x3FFF
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK The read job was set successfully.
+ * \retval STATUS_BUSY The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
+ uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ if (host_pipe_job_busy_status & (1 << pipe_num)) {
+ return STATUS_BUSY;
+ }
+
+ /* Set busy status */
+ host_pipe_job_busy_status |= 1 << pipe_num;
+
+ if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+ USB_HOST_PIPE_TYPE_DISABLE) {
+ return STATUS_ERR_NOT_INITIALIZED;
+ }
+
+ /* get pipe config from setting register */
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+ 0;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+ buf_size;
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+ USB_HOST_PIPE_TOKEN_IN;
+
+ /* Start transfer */
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+ usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief USB host pipe write job.
+ *
+ * USB host pipe write job by set and start an out transaction transfer.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] buf Pointer to data buffer
+ * \param[in] buf_size Data buffer size
+ * \note The buffer length should not larger than 0x3FFF
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK The write job was set successfully.
+ * \retval STATUS_BUSY The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
+ uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ if (host_pipe_job_busy_status & (1 << pipe_num)) {
+ return STATUS_BUSY;
+ }
+
+ /* Set busy status */
+ host_pipe_job_busy_status |= 1 << pipe_num;
+
+ if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+ USB_HOST_PIPE_TYPE_DISABLE) {
+ return STATUS_ERR_NOT_INITIALIZED;
+ }
+
+ /* get pipe config from setting register */
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+ buf_size;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+ 0;
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+ USB_HOST_PIPE_TOKEN_OUT;
+
+ /* Start transfer */
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+ usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief USB host abort a pipe job.
+ *
+ * USB host pipe abort job by freeze the pipe.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ *
+ * \return Status of the setting operation.
+ * \retval STATUS_OK The abort job was set successfully.
+ * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+ USB_HOST_PIPE_TYPE_DISABLE) {
+ return STATUS_ERR_NOT_INITIALIZED;
+ }
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Sends the LPM package.
+ *
+ * Sends the LPM package.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] buf Pointer to data buffer
+ *
+ * \return Status of the setup operation.
+ * \retval STATUS_OK The setup job was set successfully.
+ * \retval STATUS_BUSY The pipe is busy.
+ * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured.
+ */
+enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
+ uint8_t pipe_num, bool b_remotewakeup, uint8_t besl)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(pipe_num < USB_PIPE_NUM);
+
+ if (host_pipe_job_busy_status & (1 << pipe_num)) {
+ return STATUS_BUSY;
+ }
+
+ /* Set busy status */
+ host_pipe_job_busy_status |= 1 << pipe_num;
+
+ if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+ USB_HOST_PIPE_TYPE_DISABLE) {
+ return STATUS_ERR_NOT_INITIALIZED;
+ }
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
+ USB_HOST_PIPE_TYPE_EXTENDED;
+
+ /* get pipe config from setting register */
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
+ USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
+ USB_LPM_ATTRIBUT_BESL(besl) |
+ USB_LPM_ATTRIBUT_BLINKSTATE_L1;
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+ usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+ return STATUS_OK;
+}
+
+/**
+ * \internal
+ * \brief Function called by USB interrupt to manage USB host interrupts
+ *
+ * USB host interrupt events are split into four sections:
+ * - USB line events
+ * (Device dis/connection, SOF, reset, resume, wakeup, error)
+ * - Pipe events
+ * (End of data transfer, setup, stall, error)
+ */
+static void _usb_host_interrupt_handler(void)
+{
+#if BOOTLOADER_USES_HOST
+
+ uint32_t pipe_int;
+ uint32_t flags;
+
+ /* Manage pipe interrupts */
+ pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
+ if (pipe_int < 32) {
+ /* pipe interrupts */
+
+ /* get interrupt flags */
+ flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
+
+ /* host pipe transfer complete interrupt */
+ if (flags & USB_HOST_PINTFLAG_TRCPT_Msk) {
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_int);
+ /* clear the flag */
+ _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+ USB_HOST_PINTFLAG_TRCPT_Msk;
+ if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+ (1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)) {
+ pipe_callback_para.pipe_num = pipe_int;
+ if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
+ USB_HOST_PIPE_TOKEN_IN) {
+ /* in */
+ pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+ pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+ usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+ } else {
+ /* out */
+ pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+ pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+ usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+ if (0 == pipe_callback_para.transfered_size) {
+ pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+ }
+ }
+ (_usb_instances->host_pipe_callback[pipe_int]
+ [USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
+ }
+ }
+
+ /* host pipe transfer fail interrupt */
+ if (flags & USB_HOST_PINTFLAG_TRFAIL) {
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_int);
+ /* clear the flag */
+ _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+ USB_HOST_PINTFLAG_TRFAIL;
+ }
+
+ /* host pipe error interrupt */
+ if (flags & USB_HOST_PINTFLAG_PERR) {
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_int);
+ /* clear the flag */
+ _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+ USB_HOST_PINTFLAG_PERR;
+ if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+ (1 << USB_HOST_PIPE_CALLBACK_ERROR)) {
+ pipe_callback_para.pipe_num = pipe_int;
+ pipe_callback_para.pipe_error_status =
+ usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
+ (_usb_instances->host_pipe_callback[pipe_int]
+ [USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
+ }
+ }
+
+ /* host pipe transmitted setup interrupt */
+ if (flags & USB_HOST_PINTFLAG_TXSTP) {
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_int);
+ /* clear the flag */
+ _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+ USB_HOST_PINTFLAG_TXSTP;
+ if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+ (1 << USB_HOST_PIPE_CALLBACK_SETUP)) {
+ pipe_callback_para.pipe_num = pipe_int;
+ pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+ (_usb_instances->host_pipe_callback[pipe_int]
+ [USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
+ }
+ }
+
+ /* host pipe stall interrupt */
+ if (flags & USB_HOST_PINTFLAG_STALL) {
+ /* Clear busy status */
+ host_pipe_job_busy_status &= ~(1 << pipe_int);
+ /* clear the flag */
+ _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+ USB_HOST_PINTFLAG_STALL;
+ if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+ (1 << USB_HOST_PIPE_CALLBACK_STALL)) {
+ pipe_callback_para.pipe_num = pipe_int;
+ (_usb_instances->host_pipe_callback[pipe_int]
+ [USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
+ }
+ }
+
+ } else {
+ /* host interrupts */
+
+ /* get interrupt flags */
+ flags = _usb_instances->hw->HOST.INTFLAG.reg;
+
+ /* host SOF interrupt */
+ if (flags & USB_HOST_INTFLAG_HSOF) {
+ /* clear the flag */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
+ }
+ }
+
+ /* host reset interrupt */
+ if (flags & USB_HOST_INTFLAG_RST) {
+ /* Clear busy status */
+ host_pipe_job_busy_status = 0;
+ /* clear the flag */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
+ }
+ }
+
+ /* host upstream resume interrupts */
+ if (flags & USB_HOST_INTFLAG_UPRSM) {
+ /* clear the flags */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
+ }
+ }
+
+ /* host downstream resume interrupts */
+ if (flags & USB_HOST_INTFLAG_DNRSM) {
+ /* clear the flags */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
+ }
+ }
+
+ /* host wakeup interrupts */
+ if (flags & USB_HOST_INTFLAG_WAKEUP) {
+ /* clear the flags */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
+ }
+ }
+
+ /* host ram access interrupt */
+ if (flags & USB_HOST_INTFLAG_RAMACER) {
+ /* Clear busy status */
+ host_pipe_job_busy_status = 0;
+ /* clear the flag */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
+ }
+ }
+
+ /* host connect interrupt */
+ if (flags & USB_HOST_INTFLAG_DCONN) {
+ /* Clear busy status */
+ host_pipe_job_busy_status = 0;
+ /* clear the flag */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
+ }
+ }
+
+ /* host disconnect interrupt */
+ if (flags & USB_HOST_INTFLAG_DDISC) {
+ /* Clear busy status */
+ host_pipe_job_busy_status = 0;
+ /* clear the flag */
+ _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+ if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT)) {
+ (_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
+ }
+ }
+
+ }
+#endif
+}
+
+/**
+ * \brief Sets USB host pipe auto ZLP setting value
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] pipe_num Pipe to configure
+ * \param[in] value Auto ZLP setting value, \c true to enable
+ *
+ */
+void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value)
+{
+ Assert(module_inst);
+
+ usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
+}
+#endif
+
+/**
+ * \brief Registers a USB device callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_host_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ * \param[in] callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK The callback was registered successfully.
+ */
+enum status_code usb_device_register_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type,
+ usb_device_callback_t callback_func)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(callback_func);
+
+ /* Register callback function */
+ module_inst->device_callback[callback_type] = callback_func;
+
+ /* Set the bit corresponding to the callback_type */
+ module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB device callback
+ *
+ * Unregisters an asynchronous callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK The callback was unregistered successfully.
+ */
+enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+
+ /* Unregister callback function */
+ module_inst->device_callback[callback_type] = NULL;
+
+ /* Clear the bit corresponding to the callback_type */
+ module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB device callback generation for a given type.
+ *
+ * Enables asynchronous callbacks for a given logical type.
+ * This must be called before USB host generate callback events.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully.
+ */
+enum status_code usb_device_enable_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* clear related flag */
+ module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
+
+ /* Enable callback */
+ module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
+
+ module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB device callback generation for a given type.
+ *
+ * Disables asynchronous callbacks for a given logical type.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK The callback was disabled successfully.
+ */
+enum status_code usb_device_disable_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* Disable callback */
+ module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
+
+ module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Registers a USB device endpoint callback
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usb_device_endpoint_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] ep_num Endpoint to configure
+ * \param[in] callback_type Callback type given by an enum
+ * \param[in] callback_func Pointer to callback function
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK The callback was registered successfully.
+ */
+enum status_code usb_device_endpoint_register_callback(
+ struct usb_module *module_inst, uint8_t ep_num,
+ enum usb_device_endpoint_callback callback_type,
+ usb_device_endpoint_callback_t callback_func)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(ep_num < USB_EPT_NUM);
+ Assert(callback_func);
+
+ /* Register callback function */
+ module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
+
+ /* Set the bit corresponding to the callback_type */
+ module_inst->deivce_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a USB device endpoint callback
+ *
+ * Unregisters an callback implemented by the user. Removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] ep_num Endpoint to configure
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK The callback was unregistered successfully.
+ */
+enum status_code usb_device_endpoint_unregister_callback(
+ struct usb_module *module_inst, uint8_t ep_num,
+ enum usb_device_endpoint_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(ep_num < USB_EPT_NUM);
+
+ /* Unregister callback function */
+ module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
+
+ /* Clear the bit corresponding to the callback_type */
+ module_inst->deivce_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Enables USB device endpoint callback generation for a given type.
+ *
+ * Enables callbacks for a given logical type.
+ * This must be called before USB host pipe generate callback events.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] ep Endpoint to configure
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK The callback was enabled successfully.
+ */
+enum status_code usb_device_endpoint_enable_callback(
+ struct usb_module *module_inst, uint8_t ep,
+ enum usb_device_endpoint_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+ Assert(ep_num < USB_EPT_NUM);
+
+ /* Enable callback */
+ module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
+ if (ep_num == 0) { // control endpoint
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
+ } else if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+ }
+ }
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
+ if (ep_num == 0) { // control endpoint
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
+ } else if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+ }
+ }
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+ }
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
+ if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+ }
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Disables USB device endpoint callback generation for a given type.
+ *
+ * Disables callbacks for a given logical type.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] ep Endpoint to configure
+ * \param[in] callback_type Callback type given by an enum
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK The callback was disabled successfully.
+ */
+enum status_code usb_device_endpoint_disable_callback(
+ struct usb_module *module_inst, uint8_t ep,
+ enum usb_device_endpoint_callback callback_type)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+ Assert(ep_num < USB_EPT_NUM);
+
+ /* Enable callback */
+ module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
+ if (ep_num == 0) { // control endpoint
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
+ } else if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT0;
+ }
+ }
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
+ if (ep_num == 0) { // control endpoint
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
+ } else if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
+ }
+ }
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
+ }
+
+ if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
+ if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
+ }
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Initializes an USB device endpoint configuration structure to defaults.
+ *
+ * Initializes a given USB device endpoint configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li endpoint address is 0
+ * \li endpoint size is 8 bytes
+ * \li auto_zlp is false
+ * \li endpoint type is control
+ *
+ * \param[out] ep_config Configuration structure to initialize to default values
+ */
+void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config)
+{
+ /* Sanity check arguments */
+ Assert(ep_config);
+
+ /* Write default config to config struct */
+ ep_config->ep_address = 0;
+ ep_config->ep_size = USB_ENDPOINT_8_BYTE;
+ ep_config->auto_zlp = false;
+ ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
+}
+
+/**
+ * \brief Writes an USB device endpoint configuration to the hardware module.
+ *
+ * Writes out a given configuration of an USB device endpoint
+ * configuration to the hardware module. If the pipe is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] module_inst Pointer to USB software instance struct
+ * \param[in] ep_config Configuration settings for the endpoint
+ *
+ * \return Status of the device endpoint configuration operation
+ * \retval STATUS_OK The device endpoint was configured successfully
+ * \retval STATUS_ERR_DENIED The endpoint address is already configured
+ */
+enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
+ struct usb_device_endpoint_config *ep_config)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(ep_config);
+
+ uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
+ uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
+
+ switch (ep_config->ep_type) {
+ case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) | USB_DEVICE_EPCFG_EPTYPE1(0);
+ return STATUS_OK;
+
+ case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
+ (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ if (true == ep_config->auto_zlp) {
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+ } else {
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+ }
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
+ return STATUS_OK;
+
+ case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
+ if (ep_bank) {
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ } else {
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ }
+ break;
+
+ case USB_DEVICE_ENDPOINT_TYPE_BULK:
+ if (ep_bank) {
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ } else {
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ }
+ break;
+
+ case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
+ if (ep_bank) {
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ } else {
+ if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ } else {
+ return STATUS_ERR_DENIED;
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
+
+ if (true == ep_config->auto_zlp) {
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+ } else {
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Check if current endpoint is configured
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep Endpoint address (direction & number)
+ *
+ * \return \c true if endpoint is configured and ready to use
+ */
+bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep)
+{
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+ uint8_t flag;
+
+ if (ep & USB_EP_DIR_IN) {
+ flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+ } else {
+ flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+ }
+ return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
+}
+
+
+/**
+ * \brief Abort ongoing job on the endpoint
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep Endpoint address
+ */
+void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
+{
+ uint8_t ep_num;
+ ep_num = ep & USB_EP_ADDR_MASK;
+
+ // Stop transfer
+ if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ // Eventually ack a transfer occur during abort
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ // Eventually ack a transfer occur during abort
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+ }
+}
+
+/**
+ * \brief Check if endpoint is halted
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep Endpoint address
+ *
+ * \return \c true if the endpoint is halted
+ */
+bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
+{
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+ if (ep & USB_EP_DIR_IN) {
+ return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
+ } else {
+ return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
+ }
+}
+
+/**
+ * \brief Halt the endpoint (send STALL)
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep Endpoint address
+ */
+void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
+{
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+ // Stall endpoint
+ if (ep & USB_EP_DIR_IN) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+ } else {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+ }
+}
+
+/**
+ * \brief Clear endpoint halt state
+ *
+ * \param module_inst Pointer to USB software instance struct
+ * \param ep Endpoint address
+ */
+void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
+{
+ uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+ if (ep & USB_EP_DIR_IN) {
+ if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) {
+ // Remove stall request
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+ if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+ // The Stall has occurred, then reset data toggle
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
+ }
+ }
+ } else {
+ if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) {
+ // Remove stall request
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+ if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+ // The Stall has occurred, then reset data toggle
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
+ }
+ }
+ }
+}
+
+/**
+ * \brief Start write buffer job on a endpoint
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param ep_num Endpoint number
+ * \param pbuf Pointer to buffer
+ * \param buf_size Size of buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+ uint8_t* pbuf, uint32_t buf_size)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(ep_num < USB_EPT_NUM);
+
+ uint8_t flag;
+ flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+ if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
+ return STATUS_ERR_DENIED;
+ };
+
+ /* get endpoint configuration from setting register */
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Start read buffer job on a endpoint
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param ep_num Endpoint number
+ * \param pbuf Pointer to buffer
+ * \param buf_size Size of buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+ uint8_t* pbuf, uint32_t buf_size)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+ Assert(ep_num < USB_EPT_NUM);
+
+ uint8_t flag;
+ flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+ if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
+ return STATUS_ERR_DENIED;
+ };
+
+ /* get endpoint configuration from setting register */
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
+ usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+ module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Start setup packet read job on a endpoint
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param pbuf Pointer to buffer
+ *
+ * \return Status of procedure
+ * \retval STATUS_OK Job started successfully
+ * \retval STATUS_ERR_DENIED Endpoint is not ready
+ */
+enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
+ uint8_t* pbuf)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ /* get endpoint configuration from setting register */
+ usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+ usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+ usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+ module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+ return STATUS_OK;
+}
+
+static void _usb_device_interrupt_handler(void)
+{
+ uint16_t ep_inst;
+ uint16_t flags, flags_run;
+ ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
+
+ /* device interrupt */
+ if (0 == ep_inst) {
+ int i;
+
+ /* get interrupt flags */
+ flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
+ flags_run = flags &
+ _usb_instances->device_enabled_callback_mask &
+ _usb_instances->device_registered_callback_mask;
+
+ for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++) {
+ if (flags & _usb_device_irq_bits[i]) {
+ _usb_instances->hw->DEVICE.INTFLAG.reg =
+ _usb_device_irq_bits[i];
+ }
+ if (flags_run & _usb_device_irq_bits[i]) {
+ if (i == USB_DEVICE_CALLBACK_LPMSUSP) {
+ device_callback_lpm_wakeup_enable =
+ usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
+ & USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
+ }
+ (_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
+ }
+ }
+
+ } else {
+ /* endpoint interrupt */
+
+ for (uint8_t i = 0; i < USB_EPT_NUM; i++) {
+
+ if (ep_inst & (1 << i)) {
+ flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
+ flags_run = flags &
+ _usb_instances->device_endpoint_enabled_callback_mask[i] &
+ _usb_instances->deivce_endpoint_registered_callback_mask[i];
+
+ // endpoint transfer stall interrupt
+ if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) {
+ if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+ ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+ } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+ ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+ }
+
+ if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) {
+ (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
+ }
+ return;
+ }
+
+ // endpoint received setup interrupt
+ if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+ if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) {
+ ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+ (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
+ }
+ return;
+ }
+
+ // endpoint transfer fail interrupt
+ if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
+ if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+ if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
+ usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+ }
+ ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+ if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
+ return;
+ }
+ } else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+ if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
+ usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+ }
+ ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+ if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+ return;
+ }
+ }
+
+ if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
+ (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
+ }
+ return;
+ }
+
+ // endpoint transfer complete interrupt
+ if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
+ if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+ ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+ ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
+
+ } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+ _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+ ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+ ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+ ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
+ }
+ if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
+ (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
+ }
+ return;
+ }
+ }
+ }
+ }
+}
+
+/**
+ * \brief Enable the USB module peripheral
+ *
+ * \param module_inst pointer to USB module instance
+ */
+void usb_enable(struct usb_module *module_inst)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLA.reg |= USB_CTRLA_ENABLE;
+ while (module_inst->hw->HOST.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+}
+
+/**
+ * \brief Disable the USB module peripheral
+ *
+ * \param module_inst pointer to USB module instance
+ */
+void usb_disable(struct usb_module *module_inst)
+{
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+ while (module_inst->hw->HOST.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+}
+
+/**
+ * \brief Interrupt handler for the USB module.
+ */
+void USB_Handler(void)
+{
+ if (_usb_instances->hw->HOST.CTRLA.bit.MODE) {
+#if !SAMD11
+ /*host mode ISR */
+ _usb_host_interrupt_handler();
+#endif
+ } else {
+ /*device mode ISR */
+ _usb_device_interrupt_handler();
+ }
+}
+
+/**
+ * \brief Get the default USB module settings
+ *
+ * \param[out] module_config Configuration structure to initialize to default values
+ */
+void usb_get_config_defaults(struct usb_config *module_config)
+{
+ Assert(module_config);
+
+ /* Sanity check arguments */
+ Assert(module_config);
+ /* Write default configuration to config struct */
+ module_config->select_host_mode = 0;
+ module_config->run_in_standby = 1;
+ module_config->source_generator = GCLK_GENERATOR_0;
+ module_config->speed_mode = USB_SPEED_FULL;
+}
+
+#define NVM_USB_PAD_TRANSN_POS 45
+#define NVM_USB_PAD_TRANSN_SIZE 5
+#define NVM_USB_PAD_TRANSP_POS 50
+#define NVM_USB_PAD_TRANSP_SIZE 5
+#define NVM_USB_PAD_TRIM_POS 55
+#define NVM_USB_PAD_TRIM_SIZE 3
+
+/**
+ * \brief Initializes USB module instance
+ *
+ * Enables the clock and initializes the USB module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst Pointer to the software module instance struct
+ * \param[in] hw Pointer to the USB hardware module
+ * \param[in] module_config Pointer to the USB configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK The module was initialized successfully
+ */
+enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
+ struct usb_config *module_config)
+{
+ /* Sanity check arguments */
+ Assert(hw);
+ Assert(module_inst);
+ Assert(module_config);
+
+ uint32_t i,j;
+ uint32_t pad_transn, pad_transp, pad_trim;
+ struct system_pinmux_config pin_config;
+ struct system_gclk_chan_config gclk_chan_config;
+
+#if !SAMD11
+ host_pipe_job_busy_status = 0;
+#endif
+
+ _usb_instances = module_inst;
+
+ /* Associate the software module instance with the hardware module */
+ module_inst->hw = hw;
+
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_USB);
+
+ /* Set up the USB DP/DN pins */
+ system_pinmux_get_config_defaults(&pin_config);
+ pin_config.mux_position = MUX_PA24G_USB_DM;
+ system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
+ pin_config.mux_position = MUX_PA25G_USB_DP;
+ system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
+
+ /* Setup clock for module */
+ system_gclk_chan_get_config_defaults(&gclk_chan_config);
+ gclk_chan_config.source_generator = module_config->source_generator;
+ system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
+ system_gclk_chan_enable(USB_GCLK_ID);
+
+ /* Reset */
+ hw->HOST.CTRLA.bit.SWRST = 1;
+ while (hw->HOST.SYNCBUSY.bit.SWRST) {
+ /* Sync wait */
+ }
+
+ /* Load Pad Calibration */
+ pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_USB_PAD_TRANSN_POS / 32))
+ >> (NVM_USB_PAD_TRANSN_POS % 32))
+ & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+
+ if (pad_transn == 0x1F) {
+ pad_transn = 5;
+ }
+
+ hw->HOST.PADCAL.bit.TRANSN = pad_transn;
+
+ pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_USB_PAD_TRANSP_POS / 32))
+ >> (NVM_USB_PAD_TRANSP_POS % 32))
+ & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+
+ if (pad_transp == 0x1F) {
+ pad_transp = 29;
+ }
+
+ hw->HOST.PADCAL.bit.TRANSP = pad_transp;
+
+ pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_USB_PAD_TRIM_POS / 32))
+ >> (NVM_USB_PAD_TRIM_POS % 32))
+ & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+
+ if (pad_trim == 0x7) {
+ pad_trim = 3;
+ }
+
+ hw->HOST.PADCAL.bit.TRIM = pad_trim;
+
+ /* Set the configuration */
+ hw->HOST.CTRLA.bit.MODE = module_config->select_host_mode;
+ hw->HOST.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
+ hw->HOST.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
+ if (USB_SPEED_FULL == module_config->speed_mode) {
+ module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_0_Val;
+ } else if(USB_SPEED_LOW == module_config->speed_mode) {
+ module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_1_Val;
+ }
+
+ memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
+ sizeof(usb_descriptor_table.usb_endpoint_table));
+
+#if !SAMD11
+ /* callback related init */
+ for (i = 0; i < USB_HOST_CALLBACK_N; i++) {
+ module_inst->host_callback[i] = NULL;
+ };
+ for (i = 0; i < USB_PIPE_NUM; i++) {
+ for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++) {
+ module_inst->host_pipe_callback[i][j] = NULL;
+ }
+ };
+ module_inst->host_registered_callback_mask = 0;
+ module_inst->host_enabled_callback_mask = 0;
+ for (i = 0; i < USB_PIPE_NUM; i++) {
+ module_inst->host_pipe_registered_callback_mask[i] = 0;
+ module_inst->host_pipe_enabled_callback_mask[i] = 0;
+ }
+#endif
+
+ /* device callback related */
+ for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
+ module_inst->device_callback[i] = NULL;
+ }
+ for (i = 0; i < USB_EPT_NUM; i++) {
+ for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) {
+ module_inst->device_endpoint_callback[i][j] = NULL;
+ }
+ }
+ module_inst->device_registered_callback_mask = 0;
+ module_inst->device_enabled_callback_mask = 0;
+ for (j = 0; j < USB_EPT_NUM; j++) {
+ module_inst->deivce_endpoint_registered_callback_mask[j] = 0;
+ module_inst->device_endpoint_enabled_callback_mask[j] = 0;
+ }
+
+ /* Enable interrupts for this USB module */
+ system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
+
+ return STATUS_OK;
+}
+
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/usb.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/usb.h
new file mode 100755
index 0000000000000000000000000000000000000000..a2e0664a699507d066f156614863f0d28357f371
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/drivers/usb/usb.h
@@ -0,0 +1,820 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Driver
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef USB_H_INCLUDED
+#define USB_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_usb_group SAM Universal Serial Bus (USB)
+ *
+ * The Universal Serial Bus (USB) module complies with the USB 2.1 specification.
+ *
+ * The following peripherals are used by this module:
+ * - USB (Universal Serial Bus)
+ *
+ * The following devices can use this module:
+ * - SAM D21
+ * - SAM R21
+ * - SAM D11
+ *
+ * The USB module covers following mode:
+ * \if USB_DEVICE_MODE
+ * - USB Device Mode
+ * \endif
+ * \if USB_HOST_MODE
+ * - USB Host Mode
+ * \endif
+ *
+ * The USB module covers following speed:
+ * \if USB_HS_MODE
+ * - USB High Speed (480Mbit/s)
+ * \endif
+ * - USB Full Speed (12Mbit/s)
+ * \if USB_LS_MODE
+ * - USB Low Speed (1.5Mbit/s)
+ * \endif
+ *
+ * \if USB_LPM_MODE
+ * The USB module supports Link Power Management (LPM-L1) protocol.
+ * \endif
+ *
+ * USB support needs whole set of enumeration process, to make the device
+ * recognizable and usable. The USB driver is designed to interface to the
+ * USB Stack in Atmel Software Framework (ASF).
+ *
+ * \if USB_DEVICE_MODE
+ * \section asfdoc_sam0_usb_device USB Device Mode
+ * The ASF USB Device Stack has defined the USB Device Driver (UDD) interface,
+ * to support USB device operations. The USB module device driver complies with
+ * this interface, so that the USB Device Stack can work based on the
+ * USB module.
+ *
+ * Refer to <a href="http://www.atmel.com/images/doc8360.pdf">
+ * "ASF - USB Device Stack"</a> for more details.
+ * \endif
+ *
+ * \if USB_HOST_MODE
+ * \section adfdoc_sam0_usb_host USB Host Mode
+ * The ASF USB Host Stack has defined the USB Host Driver (UHD) interface,
+ * to support USB host operations. The USB module host driver complies with
+ * this interface, so that the USB Host Stack can work based on the USB module.
+ *
+ * Refer to <a href="http://www.atmel.com/images/doc8486.pdf">
+ * "ASF - USB Host Stack"</a> for more details.
+ * \endif
+ */
+
+/** Enum for the speed status for the USB module */
+enum usb_speed {
+ USB_SPEED_LOW,
+ USB_SPEED_FULL,
+};
+
+/** Enum for the possible callback types for the USB in host module */
+enum usb_host_callback {
+ USB_HOST_CALLBACK_SOF,
+ USB_HOST_CALLBACK_RESET,
+ USB_HOST_CALLBACK_WAKEUP,
+ USB_HOST_CALLBACK_DNRSM,
+ USB_HOST_CALLBACK_UPRSM,
+ USB_HOST_CALLBACK_RAMACER,
+ USB_HOST_CALLBACK_CONNECT,
+ USB_HOST_CALLBACK_DISCONNECT,
+ USB_HOST_CALLBACK_N,
+};
+
+/** Enum for the possible callback types for the USB pipe in host module */
+enum usb_host_pipe_callback {
+ USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
+ USB_HOST_PIPE_CALLBACK_ERROR,
+ USB_HOST_PIPE_CALLBACK_SETUP,
+ USB_HOST_PIPE_CALLBACK_STALL,
+ USB_HOST_PIPE_CALLBACK_N,
+};
+
+/**
+ * \brief Host pipe types.
+ */
+enum usb_host_pipe_type {
+ USB_HOST_PIPE_TYPE_DISABLE,
+ USB_HOST_PIPE_TYPE_CONTROL,
+ USB_HOST_PIPE_TYPE_ISO,
+ USB_HOST_PIPE_TYPE_BULK,
+ USB_HOST_PIPE_TYPE_INTERRUPT,
+ USB_HOST_PIPE_TYPE_EXTENDED,
+};
+
+/**
+ * \brief Host pipe token types.
+ */
+enum usb_host_pipe_token {
+ USB_HOST_PIPE_TOKEN_SETUP,
+ USB_HOST_PIPE_TOKEN_IN,
+ USB_HOST_PIPE_TOKEN_OUT,
+};
+
+/**
+ * \brief Enumeration for the possible callback types for the USB in device module
+ */
+enum usb_device_callback {
+ USB_DEVICE_CALLBACK_SOF,
+ USB_DEVICE_CALLBACK_RESET,
+ USB_DEVICE_CALLBACK_WAKEUP,
+ USB_DEVICE_CALLBACK_RAMACER,
+ USB_DEVICE_CALLBACK_SUSPEND,
+ USB_DEVICE_CALLBACK_LPMNYET,
+ USB_DEVICE_CALLBACK_LPMSUSP,
+ USB_DEVICE_CALLBACK_N,
+};
+
+/**
+ * \brief Enumeration for the possible callback types for the USB endpoint in device module
+ */
+enum usb_device_endpoint_callback {
+ USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
+ USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
+ USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
+ USB_DEVICE_ENDPOINT_CALLBACK_STALL,
+ USB_DEVICE_EP_CALLBACK_N,
+};
+
+/**
+ * \brief Device Endpoint types.
+ */
+enum usb_device_endpoint_type {
+ USB_DEVICE_ENDPOINT_TYPE_DISABLE,
+ USB_DEVICE_ENDPOINT_TYPE_CONTROL,
+ USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
+ USB_DEVICE_ENDPOINT_TYPE_BULK,
+ USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
+};
+
+/**
+ * \brief Endpoint Size
+ */
+enum usb_endpoint_size {
+ USB_ENDPOINT_8_BYTE,
+ USB_ENDPOINT_16_BYTE,
+ USB_ENDPOINT_32_BYTE,
+ USB_ENDPOINT_64_BYTE,
+ USB_ENDPOINT_128_BYTE,
+ USB_ENDPOINT_256_BYTE,
+ USB_ENDPOINT_512_BYTE,
+ USB_ENDPOINT_1023_BYTE,
+};
+
+/**
+ * \brief Link Power Management Handshake.
+ */
+enum usb_device_lpm_mode {
+ USB_DEVICE_LPM_NOT_SUPPORT,
+ USB_DEVICE_LPM_ACK,
+ USB_DEVICE_LPM_NYET,
+};
+
+/**
+ * \brief Module structure
+ */
+struct usb_module;
+
+/**
+ * \name Host callback functions types
+ * @{
+ */
+typedef void (*usb_host_callback_t)(struct usb_module *module_inst);
+typedef void (*usb_host_pipe_callback_t)(struct usb_module *module_inst, void *);
+/** @} */
+
+/**
+ * \name Device callback functions types
+ * @{
+ */
+typedef void (*usb_device_callback_t)(struct usb_module *module_inst, void* pointer);
+typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, void* pointer);
+/** @} */
+
+
+/** USB configurations */
+struct usb_config {
+ /** \c true for host, \c false for device. */
+ bool select_host_mode;
+ /** When \c true the module is enabled during standby. */
+ bool run_in_standby;
+ /** Generic Clock Generator source channel. */
+ enum gclk_generator source_generator;
+ /** Speed mode */
+ enum usb_speed speed_mode;
+};
+
+/**
+ * \brief USB software module instance structure.
+ *
+ * USB software module instance structure, used to retain software state
+ * information of an associated hardware module instance.
+ *
+ */
+struct usb_module {
+ /** Hardware module pointer of the associated USB peripheral. */
+ Usb *hw;
+
+ /** Array to store host related callback functions */
+ usb_host_callback_t host_callback[USB_HOST_CALLBACK_N];
+ usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N];
+ /** Bit mask for host callbacks registered */
+ uint8_t host_registered_callback_mask;
+ /** Bit mask for host callbacks enabled */
+ uint8_t host_enabled_callback_mask;
+ /** Bit mask for host pipe callbacks registered */
+ uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM];
+ /** Bit mask for host pipe callbacks enabled */
+ uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM];
+
+ /** Array to store device related callback functions */
+ usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
+ usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
+ /** Bit mask for device callbacks registered */
+ uint16_t device_registered_callback_mask;
+ /** Bit mask for device callbacks enabled */
+ uint16_t device_enabled_callback_mask;
+ /** Bit mask for device endpoint callbacks registered */
+ uint8_t deivce_endpoint_registered_callback_mask[USB_EPT_NUM];
+ /** Bit mask for device endpoint callbacks enabled */
+ uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
+};
+
+/** USB host pipe configurations */
+struct usb_host_pipe_config {
+ /** device address */
+ uint8_t device_address;
+ /** endpoint address */
+ uint8_t endpoint_address;
+ /** Pipe type */
+ enum usb_host_pipe_type pipe_type;
+ /** interval */
+ uint8_t binterval;
+ /** pipe size */
+ uint16_t size;
+};
+
+/** USB device endpoint configurations */
+struct usb_device_endpoint_config {
+ /** device address */
+ uint8_t ep_address;
+ /** endpoint size */
+ enum usb_endpoint_size ep_size;
+ /** automatic zero length packet mode, \c true to enable */
+ bool auto_zlp;
+ /** type of endpoint with Bank */
+ enum usb_device_endpoint_type ep_type;
+};
+
+/** USB host pipe callback status parameter structure */
+struct usb_pipe_callback_parameter {
+ /** current pipe number */
+ uint8_t pipe_num;
+ /** pipe error status */
+ uint8_t pipe_error_status;
+ /** actual transferred data size */
+ uint16_t transfered_size;
+ /** required data size */
+ uint16_t required_size;
+};
+
+/** USB device endpoint callback status parameter structure */
+struct usb_endpoint_callback_parameter {
+ uint16_t received_bytes;
+ uint16_t sent_bytes;
+ uint16_t out_buffer_size;
+ uint8_t endpoint_address;
+};
+
+void usb_enable(struct usb_module *module_inst);
+void usb_disable(struct usb_module *module_inst);
+/**
+ * \brief Get the status of USB module's state machine
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ return module_inst->hw->HOST.FSMSTATUS.reg;
+}
+
+void usb_get_config_defaults(struct usb_config *module_config);
+enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
+ struct usb_config *module_config);
+
+/**
+ * \brief Enable the USB host by setting the VBUS OK
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_enable(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1;
+}
+
+/**
+ * \brief Send the USB reset
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_reset(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1;
+}
+
+/**
+ * \brief Enable the USB SOF generation
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_enable_sof(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLB.bit.SOFE = 1;
+}
+
+/**
+ * \brief Disable the USB SOF generation
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_disable_sof(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLB.bit.SOFE = 0;
+}
+
+/**
+ * \brief Check the USB SOF generation status
+ *
+ * \param module_inst Pointer to USB software instance struct
+ *
+ * \return USB SOF generation status, \c true if SOF generation is ON.
+ */
+static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ return module_inst->hw->HOST.CTRLB.bit.SOFE;
+}
+
+/**
+ * \brief Send the USB host resume
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_resume(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLB.bit.RESUME= 1;
+}
+
+/**
+ * \brief Send the USB host LPM resume
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_l1_resume(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1;
+}
+
+/**
+ * \brief Get the speed mode of USB host
+ *
+ * \param module_inst Pointer to USB module instance struct
+ *
+ * \return USB speed mode (\ref usb_speed)
+ */
+static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ if (module_inst->hw->HOST.STATUS.bit.SPEED == 0) {
+ return USB_SPEED_FULL;
+ } else {
+ return USB_SPEED_LOW;
+ }
+}
+
+/**
+ * \brief Get the frame number
+ *
+ * \param module_inst Pointer to USB software instance struct
+ *
+ * \return frame number value
+ */
+static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM);
+}
+
+/**
+ * \brief Attach USB device to the bus
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_attach(struct usb_module *module_inst)
+{
+ module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+}
+
+/**
+ * \brief Detach USB device from the bus
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_detach(struct usb_module *module_inst)
+{
+ module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+}
+
+/**
+ * \brief Get the speed mode of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB Speed mode (\ref usb_speed)
+ */
+static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst)
+{
+ if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) {
+ return USB_SPEED_FULL;
+ } else {
+ return USB_SPEED_LOW;
+ }
+}
+
+/**
+ * \brief Get the address of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device address value
+ */
+static inline uint8_t usb_device_get_address(struct usb_module *module_inst)
+{
+ return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
+}
+
+/**
+ * \brief Set the speed mode of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param address USB device address value
+ */
+static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address)
+{
+ module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
+}
+
+/**
+ * \brief Get the frame number of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device frame number value
+ */
+static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst)
+{
+ return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
+}
+
+/**
+ * \brief Get the micro-frame number of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device micro-frame number value
+ */
+static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst)
+{
+ return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
+}
+
+/**
+ * \brief USB device send the resume wakeup
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst)
+{
+ module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+}
+
+/**
+ * \brief USB device set the LPM mode
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param lpm_mode LPM mode
+ */
+static inline void usb_device_set_lpm_mode(struct usb_module *module_inst,
+ enum usb_device_lpm_mode lpm_mode)
+{
+ module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
+}
+
+/**
+ * \name USB Host Callback management
+ * @{
+ */
+enum status_code usb_host_register_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type,
+ usb_host_callback_t callback_func);
+enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type);
+enum status_code usb_host_enable_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type);
+enum status_code usb_host_disable_callback(struct usb_module *module_inst,
+ enum usb_host_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Device Callback management
+ * @{
+ */
+enum status_code usb_device_register_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type,
+ usb_device_callback_t callback_func);
+enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type);
+enum status_code usb_device_enable_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type);
+enum status_code usb_device_disable_callback(struct usb_module *module_inst,
+ enum usb_device_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Host Pipe configuration
+ * @{
+ */
+void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config);
+enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
+ struct usb_host_pipe_config *ep_config);
+enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
+ struct usb_host_pipe_config *ep_config);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Configuration
+ * @{
+ */
+void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config);
+enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
+ struct usb_device_endpoint_config *ep_config);
+bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep);
+/** @} */
+
+/**
+ * \name USB Host Pipe Callback management
+ * @{
+ */
+enum status_code usb_host_pipe_register_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type,
+ usb_host_pipe_callback_t callback_func);
+enum status_code usb_host_pipe_unregister_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type);
+enum status_code usb_host_pipe_enable_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type);
+enum status_code usb_host_pipe_disable_callback(
+ struct usb_module *module_inst, uint8_t pipe_num,
+ enum usb_host_pipe_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Callback management
+ * @{
+ */
+enum status_code usb_device_endpoint_register_callback(
+ struct usb_module *module_inst, uint8_t ep_num,
+ enum usb_device_endpoint_callback callback_type,
+ usb_device_endpoint_callback_t callback_func);
+enum status_code usb_device_endpoint_unregister_callback(
+ struct usb_module *module_inst, uint8_t ep_num,
+ enum usb_device_endpoint_callback callback_type);
+enum status_code usb_device_endpoint_enable_callback(
+ struct usb_module *module_inst, uint8_t ep,
+ enum usb_device_endpoint_callback callback_type);
+enum status_code usb_device_endpoint_disable_callback(
+ struct usb_module *module_inst, uint8_t ep,
+ enum usb_device_endpoint_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Host Pipe Job management
+ * @{
+ */
+enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
+ uint8_t pipe_num, uint8_t *buf);
+enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
+ uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
+ uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num);
+enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
+ uint8_t pipe_num, bool b_remotewakeup, uint8_t besl);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Job management
+ * @{
+ */
+enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+ uint8_t* pbuf, uint32_t buf_size);
+enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+ uint8_t* pbuf, uint32_t buf_size);
+enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
+ uint8_t* pbuf);
+void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
+/** @} */
+
+/**
+ * \name USB Host Pipe Operations
+ * @{
+ */
+
+/**
+ * \brief Freeze a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num Pipe number
+ */
+static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t pipe_num)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+}
+
+/**
+ * \brief Unfreeze a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num Pipe number
+ */
+static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_t pipe_num)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
+}
+
+/**
+ * \brief Check if the pipe is frozen
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num Pipe number
+ */
+static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8_t pipe_num)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1);
+}
+
+/**
+ * \brief Set the data toggle bit of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num Pipe number
+ */
+static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint8_t pipe_num)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL;
+}
+
+/**
+ * \brief Clear the data toggle bit of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num Pipe number
+ */
+static inline void usb_host_pipe_clear_toggle(struct usb_module *module_inst, uint8_t pipe_num)
+{
+ /* Sanity check arguments */
+ Assert(module_inst);
+ Assert(module_inst->hw);
+
+ module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
+}
+
+/**
+ * \brief Set the auto zero length packet of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num Pipe number
+ * \param value \c true to enable auto ZLP and \c false to disable
+ */
+void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value);
+
+/** @} */
+
+/**
+ * \name USB Device Endpoint Operations
+ * @{
+ */
+
+bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep);
+void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep);
+void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h
new file mode 100755
index 0000000000000000000000000000000000000000..6a19024cf8d193c6dbdec86f82a1e7d9ff6bc34a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h
@@ -0,0 +1,559 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC 0x111
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE 0x00 /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST (0x1u << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE (0x1u << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk (0x1u << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
+#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX (0x1u << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK 0x87u /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE 0x00 /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk (0x3u << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
+#define AC_CTRLB_MASK 0x03u /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE 0x0000 /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk (0x3u << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk (0x1u << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk (0x3u << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
+#define AC_EVCTRL_MASK 0x0313u /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE 0x00 /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk (0x3u << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk (0x1u << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
+#define AC_INTENCLR_MASK 0x13u /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE 0x00 /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk (0x3u << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk (0x1u << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
+#define AC_INTENSET_MASK 0x13u /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE 0x00 /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk (0x3u << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk (0x1u << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
+#define AC_INTFLAG_MASK 0x13u /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE 0x00 /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk (0x3u << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk (0x3u << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
+#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSA) Signal is above window */
+#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSA) Signal is inside window */
+#define AC_STATUSA_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK 0x33u /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE 0x00 /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk (0x3u << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
+#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY (0x1u << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK 0x83u /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE 0x00 /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk (0x3u << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
+#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk (0x3u << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
+#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSC) Signal is above window */
+#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSC) Signal is inside window */
+#define AC_STATUSC_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK 0x33u /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE 0x00 /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0 (0x1u << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk (0x3u << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
+#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0u /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1u /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2u /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3u /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK 0x07u /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE 0x00000000 /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE (0x1u << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE (0x1u << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk (0x3u << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
+#define AC_COMPCTRL_SPEED_LOW_Val 0x0u /**< \brief (AC_COMPCTRL) Low speed */
+#define AC_COMPCTRL_SPEED_HIGH_Val 0x1u /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk (0x3u << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
+#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0u /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define AC_COMPCTRL_INTSEL_RISING_Val 0x1u /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2u /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define AC_COMPCTRL_INTSEL_EOC_Val 0x3u /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk (0x7u << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
+#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXNEG_GND_Val 0x4u /**< \brief (AC_COMPCTRL) Ground */
+#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5u /**< \brief (AC_COMPCTRL) VDD scaler */
+#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6u /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7u /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk (0x3u << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
+#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP (0x1u << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk (0x3u << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
+#define AC_COMPCTRL_OUT_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_ASYNC_Val 0x1u /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_SYNC_Val 0x2u /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST (0x1u << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk (0x7u << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
+#define AC_COMPCTRL_FLEN_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) No filtering */
+#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1u /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2u /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK 0x070BB76Fu /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE 0x00 /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk (0x3Fu << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
+#define AC_SCALER_MASK 0x3Fu /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h
new file mode 100755
index 0000000000000000000000000000000000000000..64cd91b75259f0427257c10c4768892b048f650a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h
@@ -0,0 +1,699 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC 0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE 0x00 /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST (0x1u << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE (0x1u << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY (0x1u << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK 0x07u /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE 0x00 /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk (0xFu << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
+#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0u /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1u /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2u /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3u /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4u /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP (0x1u << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK 0x8Fu /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE 0x00 /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFu << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
+#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0u /**< \brief (ADC_AVGCTRL) 1 sample */
+#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1u /**< \brief (ADC_AVGCTRL) 2 samples */
+#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2u /**< \brief (ADC_AVGCTRL) 4 samples */
+#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3u /**< \brief (ADC_AVGCTRL) 8 samples */
+#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4u /**< \brief (ADC_AVGCTRL) 16 samples */
+#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5u /**< \brief (ADC_AVGCTRL) 32 samples */
+#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6u /**< \brief (ADC_AVGCTRL) 64 samples */
+#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7u /**< \brief (ADC_AVGCTRL) 128 samples */
+#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8u /**< \brief (ADC_AVGCTRL) 256 samples */
+#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9u /**< \brief (ADC_AVGCTRL) 512 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAu /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk (0x7u << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
+#define ADC_AVGCTRL_MASK 0x7Fu /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE 0x00 /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Fu << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
+#define ADC_SAMPCTRL_MASK 0x3Fu /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE 0x0000 /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE (0x1u << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ (0x1u << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN (0x1u << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN (0x1u << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk (0x3u << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
+#define ADC_CTRLB_RESSEL_12BIT_Val 0x0u /**< \brief (ADC_CTRLB) 12-bit result */
+#define ADC_CTRLB_RESSEL_16BIT_Val 0x1u /**< \brief (ADC_CTRLB) For averaging mode output */
+#define ADC_CTRLB_RESSEL_10BIT_Val 0x2u /**< \brief (ADC_CTRLB) 10-bit result */
+#define ADC_CTRLB_RESSEL_8BIT_Val 0x3u /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk (0x7u << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
+#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0u /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1u /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2u /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3u /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4u /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5u /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6u /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7u /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK 0x073Fu /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE 0x00 /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk (0x7u << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
+#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0u /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1u /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2u /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3u /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4u /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK 0x07u /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE 0x00 /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH (0x1u << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START (0x1u << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK 0x03u /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE 0x00000000 /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Fu << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
+#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4u /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5u /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6u /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7u /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8u /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9u /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAu /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBu /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCu /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDu /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEu /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFu /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10u /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11u /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12u /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13u /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18u /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19u /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Au /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bu /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cu /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Fu << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
+#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4u /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5u /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6u /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7u /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18u /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19u /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFu << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFu << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
+#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk (0xFu << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
+#define ADC_INPUTCTRL_GAIN_1X_Val 0x0u /**< \brief (ADC_INPUTCTRL) 1x */
+#define ADC_INPUTCTRL_GAIN_2X_Val 0x1u /**< \brief (ADC_INPUTCTRL) 2x */
+#define ADC_INPUTCTRL_GAIN_4X_Val 0x2u /**< \brief (ADC_INPUTCTRL) 4x */
+#define ADC_INPUTCTRL_GAIN_8X_Val 0x3u /**< \brief (ADC_INPUTCTRL) 8x */
+#define ADC_INPUTCTRL_GAIN_16X_Val 0x4u /**< \brief (ADC_INPUTCTRL) 16x */
+#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFu /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK 0x0FFF1F1Fu /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE 0x00 /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI (0x1u << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI (0x1u << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO (0x1u << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO (0x1u << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK 0x33u /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE 0x00 /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY (0x1u << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN (0x1u << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON (0x1u << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY (0x1u << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK 0x0Fu /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE 0x00 /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY (0x1u << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN (0x1u << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON (0x1u << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY (0x1u << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK 0x0Fu /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE 0x00 /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY (0x1u << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN (0x1u << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON (0x1u << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY (0x1u << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK 0x0Fu /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE 0x00 /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY (0x1u << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK 0x80u /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE 0x0000 /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk (0xFFFFu << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
+#define ADC_RESULT_MASK 0xFFFFu /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE 0x0000 /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk (0xFFFFu << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
+#define ADC_WINLT_MASK 0xFFFFu /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE 0x0000 /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk (0xFFFFu << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
+#define ADC_WINUT_MASK 0xFFFFu /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE 0x0000 /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk (0xFFFu << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
+#define ADC_GAINCORR_MASK 0x0FFFu /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE 0x0000 /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFu << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
+#define ADC_OFFSETCORR_MASK 0x0FFFu /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE 0x0000 /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFu << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
+#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk (0x7u << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
+#define ADC_CALIB_MASK 0x07FFu /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE 0x00 /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN (0x1u << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK 0x01u /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h
new file mode 100755
index 0000000000000000000000000000000000000000..08fb25f29c2180fcd69073119e04d394cc6cbbbb
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h
@@ -0,0 +1,286 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC 0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE 0x00 /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST (0x1u << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE (0x1u << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY (0x1u << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK 0x07u /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
+ uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
+ uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE 0x00 /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN (0x1u << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN (0x1u << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ (0x1u << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD (0x1u << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP (0x1u << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk (0x3u << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
+#define DAC_CTRLB_REFSEL_INT1V_Val 0x0u /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define DAC_CTRLB_REFSEL_AVCC_Val 0x1u /**< \brief (DAC_CTRLB) AVCC */
+#define DAC_CTRLB_REFSEL_VREFP_Val 0x2u /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK 0xDFu /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE 0x00 /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI (0x1u << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO (0x1u << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK 0x03u /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE 0x00 /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN (0x1u << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY (0x1u << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY (0x1u << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK 0x07u /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE 0x00 /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN (0x1u << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY (0x1u << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY (0x1u << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK 0x07u /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE 0x00 /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN (0x1u << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY (0x1u << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY (0x1u << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK 0x07u /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE 0x00 /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY (0x1u << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK 0x80u /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE 0x0000 /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk (0xFFFFu << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
+#define DAC_DATA_MASK 0xFFFFu /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE 0x0000 /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk (0xFFFFu << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
+#define DAC_DATABUF_MASK 0xFFFFu /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
+ RoReg8 Reserved2[0x2];
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h
new file mode 100755
index 0000000000000000000000000000000000000000..dfd112b770e124fac6628293719f6f7fd63e5fbd
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h
@@ -0,0 +1,1033 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC 0x100
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE 0x0000 /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST (0x1u << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE (0x1u << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE (0x1u << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk (0xFu << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
+#define DMAC_CTRL_MASK 0x0F07u /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE 0x0000 /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3u << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0u /**< \brief (DMAC_CRCCTRL) Byte bus access */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1u /**< \brief (DMAC_CRCCTRL) Half-word bus access */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2u /**< \brief (DMAC_CRCCTRL) Word bus access */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3u << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
+#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0u /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1u /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Fu << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
+#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0u /**< \brief (DMAC_CRCCTRL) No action */
+#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1u /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK 0x3F0Fu /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE 0x00000000 /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFu << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
+#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFu /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000 /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFu << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
+#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFu /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE 0x00 /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY (0x1u << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO (0x1u << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK 0x03u /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE 0x00 /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN (0x1u << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK 0x01u /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000 /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFu << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
+#define DMAC_SWTRIGCTRL_MASK 0x00000FFFu /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE 0x00000000 /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFu << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0 (0x1u << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFu << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1 (0x1u << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFu << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2 (0x1u << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFu << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3 (0x1u << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK 0x8F8F8F8Fu /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE 0x0000 /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk (0xFu << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
+#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR (0x1u << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL (0x1u << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP (0x1u << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR (0x1u << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY (0x1u << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND (0x1u << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK 0xE70Fu /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE 0x00000000 /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk (0xFFFu << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
+#define DMAC_INTSTATUS_MASK 0x00000FFFu /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE 0x00000000 /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFu << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
+#define DMAC_BUSYCH_MASK 0x00000FFFu /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE 0x00000000 /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk (0xFFFu << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
+#define DMAC_PENDCH_MASK 0x00000FFFu /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE 0x00000000 /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk (0xFu << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
+#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk (0x1Fu << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
+#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY (0x1u << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFu << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
+#define DMAC_ACTIVE_MASK 0xFFFF9F0Fu /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE 0x00000000 /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFu << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
+#define DMAC_BASEADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE 0x00000000 /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFu << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
+#define DMAC_WRBADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE 0x00 /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk (0xFu << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
+#define DMAC_CHID_MASK 0x0Fu /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE 0x00 /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST (0x1u << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE (0x1u << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK 0x03u /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE 0x00000000 /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk (0x7u << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
+#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0u /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1u /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2u /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3u /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4u /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5u /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6u /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE (0x1u << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE (0x1u << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk (0x3u << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
+#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Fu << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0u /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk (0x3u << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
+#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0u /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2u /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3u /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk (0x3u << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
+#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0u /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1u /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2u /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK 0x03C03F7Fu /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE 0x00 /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR (0x1u << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL (0x1u << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP (0x1u << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK 0x07u /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE 0x00 /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR (0x1u << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL (0x1u << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP (0x1u << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK 0x07u /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE 0x00 /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Transfer Error */
+#define DMAC_CHINTFLAG_TERR (0x1u << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL (0x1u << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP (0x1u << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK 0x07u /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE 0x00 /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND (0x1u << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY (0x1u << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Fetch Error */
+#define DMAC_CHSTATUS_FERR (0x1u << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK 0x07u /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID (0x1u << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk (0x3u << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
+#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0u /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1u /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3u /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk (0x3u << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
+#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0u /**< \brief (DMAC_BTCTRL) No action */
+#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1u /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2u /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3u /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk (0x3u << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
+#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0u /**< \brief (DMAC_BTCTRL) 8-bit access */
+#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1u /**< \brief (DMAC_BTCTRL) 16-bit access */
+#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2u /**< \brief (DMAC_BTCTRL) 32-bit access */
+#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC (0x1u << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC (0x1u << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL (0x1u << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0u /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1u /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk (0x7u << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
+#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */
+#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */
+#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */
+#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 8 */
+#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 16 */
+#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 32 */
+#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 64 */
+#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK 0xFF1Fu /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk (0xFFFFu << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
+#define DMAC_BTCNT_MASK 0xFFFFu /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFu << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
+#define DMAC_SRCADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
+
+#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFu << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
+#define DMAC_DSTADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFu << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
+#define DMAC_DESCADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ RoReg8 Reserved1[0x2];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+ __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_DMAC_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAMD21_DMAC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h
new file mode 100755
index 0000000000000000000000000000000000000000..3e5eb60586e583621b2c1ef816491500082b0c23
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h
@@ -0,0 +1,551 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_COMPONENT_
+#define _SAMD21_DSU_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU 0x200
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE 0x00 /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST (0x1u << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
+#define DSU_CTRL_CRC (0x1u << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
+#define DSU_CTRL_MBIST (0x1u << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
+#define DSU_CTRL_CE (0x1u << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK 0x1Du /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE 0x00 /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE (0x1u << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT (0x1u << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR (0x1u << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL (0x1u << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR (0x1u << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK 0x1Fu /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE 0x10 /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT (0x1u << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES (0x1u << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk (0x3u << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
+#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE (0x1u << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK 0x1Fu /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE 0x00000000 /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFu << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
+#define DSU_ADDR_MASK 0xFFFFFFFCu /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE 0x00000000 /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFu << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
+#define DSU_LENGTH_MASK 0xFFFFFFFCu /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE 0x00000000 /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk (0xFFFFFFFFu << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
+#define DSU_DATA_MASK 0xFFFFFFFFu /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE 0x00000000 /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk (0xFFFFFFFFu << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
+#define DSU_DCC_MASK 0xFFFFFFFFu /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk (0xFFu << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
+#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
+#define DSU_DID_REVISION_Msk (0xFu << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
+#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
+#define DSU_DID_DIE_Msk (0xFu << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
+#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
+#define DSU_DID_SERIES_Msk (0x3Fu << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
+#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
+#define DSU_DID_FAMILY_Msk (0x1Fu << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
+#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk (0xFu << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
+#define DSU_DID_MASK 0xFFBFFFFFu /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE 0x00000002 /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES (0x1u << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT (0x1u << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFu << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
+#define DSU_ENTRY_MASK 0xFFFFF003u /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE 0x00000000 /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk (0xFFFFFFFFu << DSU_END_END_Pos)
+#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
+#define DSU_END_MASK 0xFFFFFFFFu /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE 0x00000000 /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP (0x1u << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK 0x00000001u /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE 0x00000000 /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk (0xFu << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
+#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
+#define DSU_PID4_FKBC_Msk (0xFu << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
+#define DSU_PID4_MASK 0x000000FFu /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE 0x000000D0 /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk (0xFFu << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
+#define DSU_PID0_MASK 0x000000FFu /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE 0x000000FC /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk (0xFu << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
+#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk (0xFu << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
+#define DSU_PID1_MASK 0x000000FFu /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE 0x00000009 /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk (0x7u << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
+#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU (0x1u << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk (0xFu << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
+#define DSU_PID2_MASK 0x000000FFu /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE 0x00000000 /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk (0xFu << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
+#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk (0xFu << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
+#define DSU_PID3_MASK 0x000000FFu /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE 0x0000000D /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk (0xFFu << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
+#define DSU_CID0_MASK 0x000000FFu /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE 0x00000010 /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk (0xFu << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
+#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk (0xFu << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
+#define DSU_CID1_MASK 0x000000FFu /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE 0x00000005 /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk (0xFFu << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
+#define DSU_CID2_MASK 0x000000FFu /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE 0x000000B1 /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk (0xFFu << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
+#define DSU_CID3_MASK 0x000000FFu /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DSU_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h
new file mode 100755
index 0000000000000000000000000000000000000000..1601beba6b24fa082948231ad4d54f77d3f819a0
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h
@@ -0,0 +1,681 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_COMPONENT_
+#define _SAMD21_EIC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC 0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE 0x00 /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST (0x1u << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE (0x1u << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK 0x03u /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE 0x00 /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY (0x1u << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK 0x80u /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE 0x00 /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk (0x7u << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
+#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0u /**< \brief (EIC_NMICTRL) No detection */
+#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1u /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2u /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3u /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4u /**< \brief (EIC_NMICTRL) High-level detection */
+#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5u /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN (0x1u << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK 0x0Fu /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE 0x00 /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI (0x1u << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK 0x01u /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE 0x00000000 /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFu << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
+#define EIC_EVCTRL_MASK 0x0000FFFFu /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk (0xFFFFu << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
+#define EIC_INTENCLR_MASK 0x0000FFFFu /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE 0x00000000 /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk (0xFFFFu << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
+#define EIC_INTENSET_MASK 0x0000FFFFu /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk (0xFFFFu << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
+#define EIC_INTFLAG_MASK 0x0000FFFFu /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE 0x00000000 /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFu << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
+#define EIC_WAKEUP_MASK 0x0000FFFFu /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE 0x00000000 /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk (0x7u << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
+#define EIC_CONFIG_SENSE0_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE0_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define EIC_CONFIG_SENSE0_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define EIC_CONFIG_SENSE0_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both-edges detection */
+#define EIC_CONFIG_SENSE0_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High-level detection */
+#define EIC_CONFIG_SENSE0_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0 (0x1u << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk (0x7u << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
+#define EIC_CONFIG_SENSE1_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE1_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE1_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE1_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE1_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE1_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1 (0x1u << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk (0x7u << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
+#define EIC_CONFIG_SENSE2_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE2_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE2_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE2_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE2_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE2_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2 (0x1u << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk (0x7u << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
+#define EIC_CONFIG_SENSE3_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE3_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE3_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE3_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE3_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE3_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3 (0x1u << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk (0x7u << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
+#define EIC_CONFIG_SENSE4_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE4_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE4_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE4_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE4_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE4_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4 (0x1u << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk (0x7u << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
+#define EIC_CONFIG_SENSE5_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE5_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE5_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE5_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE5_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE5_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5 (0x1u << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk (0x7u << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
+#define EIC_CONFIG_SENSE6_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE6_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE6_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE6_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE6_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE6_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6 (0x1u << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk (0x7u << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
+#define EIC_CONFIG_SENSE7_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE7_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE7_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE7_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE7_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE7_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7 (0x1u << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK 0xFFFFFFFFu /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EIC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h
new file mode 100755
index 0000000000000000000000000000000000000000..c036ecfe138756f971a26d9a6c5a6e131b996a82
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h
@@ -0,0 +1,604 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS 0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE 0x00 /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST (0x1u << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ (0x1u << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK 0x11u /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE 0x00000000 /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk (0xFu << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
+#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT (0x1u << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk (0x7Fu << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
+#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk (0x3u << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0u /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1u /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2u /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk (0x3u << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0u /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1u /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2u /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3u /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK 0x0F7F010Fu /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE 0x0000 /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk (0x1Fu << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
+#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk (0x1Fu << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
+#define EVSYS_USER_CHANNEL_0_Val 0x0u /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK 0x1F1Fu /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FF /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFu << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFu << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
+#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFu << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFu << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
+#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFu /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk (0xFFu << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
+#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk (0xFFu << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
+#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk (0xFu << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
+#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk (0xFu << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
+#define EVSYS_INTENCLR_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk (0xFFu << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
+#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk (0xFFu << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
+#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk (0xFu << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
+#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk (0xFu << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
+#define EVSYS_INTENSET_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk (0xFFu << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
+#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk (0xFFu << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
+#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk (0xFu << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
+#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk (0xFu << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
+#define EVSYS_INTFLAG_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h
new file mode 100755
index 0000000000000000000000000000000000000000..43b8cb64b3a5107f111fcf0eb8272e7787e81eb3
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h
@@ -0,0 +1,234 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_COMPONENT_
+#define _SAMD21_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD21_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK 0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE 0x00 /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST (0x1u << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK 0x01u /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE 0x00 /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY (0x1u << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK 0x80u /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE 0x0000 /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk (0x3Fu << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
+#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk (0xFu << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
+#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0u /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1u /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2u /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3u /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4u /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5u /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6u /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7u /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN (0x1u << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK (0x1u << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK 0xCF3Fu /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE 0x00000000 /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk (0xFu << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
+#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk (0x1Fu << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
+#define GCLK_GENCTRL_SRC_XOSC_Val 0x0u /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1u /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2u /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3u /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4u /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5u /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6u /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7u /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN (0x1u << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC (0x1u << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV (0x1u << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE (0x1u << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL (0x1u << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY (0x1u << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK 0x003F1F0Fu /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE 0x00000000 /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk (0xFu << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
+#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk (0xFFFFu << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
+#define GCLK_GENDIV_MASK 0x00FFFF0Fu /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_GCLK_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h
new file mode 100755
index 0000000000000000000000000000000000000000..4eebf78cb59909b726852e1c33b428ea224050b7
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h
@@ -0,0 +1,639 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_COMPONENT_
+#define _SAMD21_I2S_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S 0x101
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
+ uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE 0x00 /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST (0x1u << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE (0x1u << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk (0x3u << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
+#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
+#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
+#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
+#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
+#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
+#define I2S_CTRLA_SEREN_Msk (0x3u << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
+#define I2S_CTRLA_MASK 0x3Fu /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t :2; /*!< bit: 9..10 Reserved */
+ uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
+ uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
+ uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
+ uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
+ uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
+ uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
+ uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3u << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
+#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0u /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1u /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2u /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3u /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk (0x7u << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
+#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk (0x3u << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
+#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3u /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY (0x1u << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0u /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1u /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL (0x1u << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV (0x1u << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL (0x1u << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL (0x1u << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0u /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN (0x1u << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
+#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV (0x1u << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV (0x1u << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV (0x1u << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK 0xFFFD19FFu /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE 0x0000 /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk (0x3u << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
+#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk (0x3u << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
+#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk (0x3u << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
+#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk (0x3u << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
+#define I2S_INTENCLR_MASK 0x3333u /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE 0x0000 /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk (0x3u << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
+#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk (0x3u << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
+#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk (0x3u << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
+#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk (0x3u << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
+#define I2S_INTENSET_MASK 0x3333u /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE 0x0000 /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk (0x3u << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
+#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk (0x3u << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
+#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk (0x3u << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
+#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk (0x3u << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
+#define I2S_INTFLAG_MASK 0x3333u /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
+ uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
+ uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE 0x0000 /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST (0x1u << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE (0x1u << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk (0x3u << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
+#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
+#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
+#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN_Msk (0x3u << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
+#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
+#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
+#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
+#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
+#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
+#define I2S_SYNCBUSY_DATA_Msk (0x3u << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
+#define I2S_SYNCBUSY_MASK 0x033Fu /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_SERCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+
+#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
+#define I2S_SERCTRL_SERMODE_Msk (0x3u << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
+#define I2S_SERCTRL_SERMODE_RX_Val 0x0u /**< \brief (I2S_SERCTRL) Receive */
+#define I2S_SERCTRL_SERMODE_TX_Val 0x1u /**< \brief (I2S_SERCTRL) Transmit */
+#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2u /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_Msk (0x3u << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
+#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3u /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
+#define I2S_SERCTRL_TXSAME (0x1u << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_SAME_Val 0x1u /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
+#define I2S_SERCTRL_CLKSEL (0x1u << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0u /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1u /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
+#define I2S_SERCTRL_SLOTADJ (0x1u << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
+#define I2S_SERCTRL_DATASIZE_Msk (0x7u << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
+#define I2S_SERCTRL_DATASIZE_32_Val 0x0u /**< \brief (I2S_SERCTRL) 32 bits */
+#define I2S_SERCTRL_DATASIZE_24_Val 0x1u /**< \brief (I2S_SERCTRL) 24 bits */
+#define I2S_SERCTRL_DATASIZE_20_Val 0x2u /**< \brief (I2S_SERCTRL) 20 bits */
+#define I2S_SERCTRL_DATASIZE_18_Val 0x3u /**< \brief (I2S_SERCTRL) 18 bits */
+#define I2S_SERCTRL_DATASIZE_16_Val 0x4u /**< \brief (I2S_SERCTRL) 16 bits */
+#define I2S_SERCTRL_DATASIZE_16C_Val 0x5u /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_8_Val 0x6u /**< \brief (I2S_SERCTRL) 8 bits */
+#define I2S_SERCTRL_DATASIZE_8C_Val 0x7u /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
+#define I2S_SERCTRL_WORDADJ (0x1u << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
+#define I2S_SERCTRL_EXTEND_Msk (0x3u << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
+#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define I2S_SERCTRL_EXTEND_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Extend with ones */
+#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2u /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3u /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
+#define I2S_SERCTRL_BITREV (0x1u << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0u /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1u /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
+#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
+#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
+#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
+#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
+#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
+#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
+#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
+#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS_Msk (0xFFu << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
+#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
+#define I2S_SERCTRL_MONO (0x1u << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_STEREO_Val 0x0u /**< \brief (I2S_SERCTRL) Normal mode */
+#define I2S_SERCTRL_MONO_MONO_Val 0x1u /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
+#define I2S_SERCTRL_DMA (0x1u << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_SINGLE_Val 0x0u /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1u /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
+#define I2S_SERCTRL_RXLOOP (0x1u << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK 0x07FFF7BFu /**< \brief (I2S_SERCTRL) MASK Register */
+
+/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
+#define I2S_DATA_RESETVALUE 0x00000000 /**< \brief (I2S_DATA reset_value) Data n */
+
+#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
+#define I2S_DATA_DATA_Msk (0xFFFFFFFFu << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
+#define I2S_DATA_MASK 0xFFFFFFFFu /**< \brief (I2S_DATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+ RoReg8 Reserved6[0x8];
+ __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_I2S_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h
new file mode 100755
index 0000000000000000000000000000000000000000..fc6e988b35267a9dc007e103141740812340a2f6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h
@@ -0,0 +1,396 @@
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_COMPONENT_
+#define _SAMD21_MTB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB 0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP (0x1u << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFu << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
+#define MTB_POSITION_MASK 0xFFFFFFFCu /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE 0x00000000 /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk (0x1Fu << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
+#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN (0x1u << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN (0x1u << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV (0x1u << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV (0x1u << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ (0x1u << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN (0x1u << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_ 0x800003FFu /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE 0x00000000 /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP (0x1u << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT (0x1u << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFu << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
+#define MTB_FLOW_MASK 0xFFFFFFFBu /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK 0xFFFFFFFFu /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK 0xFFFFFFFFu /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
+#define MTB_PID4_MASK 0xFFFFFFFFu /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
+#define MTB_PID5_MASK 0xFFFFFFFFu /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
+#define MTB_PID6_MASK 0xFFFFFFFFu /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
+#define MTB_PID7_MASK 0xFFFFFFFFu /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
+#define MTB_PID0_MASK 0xFFFFFFFFu /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
+#define MTB_PID1_MASK 0xFFFFFFFFu /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
+#define MTB_PID2_MASK 0xFFFFFFFFu /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
+#define MTB_PID3_MASK 0xFFFFFFFFu /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
+#define MTB_CID0_MASK 0xFFFFFFFFu /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
+#define MTB_CID1_MASK 0xFFFFFFFFu /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
+#define MTB_CID2_MASK 0xFFFFFFFFu /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
+#define MTB_CID3_MASK 0xFFFFFFFFu /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_MTB_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
new file mode 100755
index 0000000000000000000000000000000000000000..b7f1af74a4d974ec06f16c5d08cd39eb0263a274
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
@@ -0,0 +1,530 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL 0x106
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE 0x0000 /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk (0x7Fu << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
+#define NVMCTRL_CTRLA_CMD_ER_Val 0x2u /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_WP_Val 0x4u /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5u /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6u /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define NVMCTRL_CTRLA_CMD_SF_Val 0xAu /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define NVMCTRL_CTRLA_CMD_WL_Val 0xFu /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define NVMCTRL_CTRLA_CMD_LR_Val 0x40u /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_UR_Val 0x41u /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42u /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43u /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44u /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45u /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46u /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFu << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
+#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5u /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK 0xFF7Fu /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk (0xFu << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
+#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0u /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1u /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2u /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW (0x1u << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3u << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0u /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1u /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3u /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk (0x3u << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0u /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1u /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2u /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS (0x1u << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK 0x0007039Eu /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFu << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
+#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk (0x7u << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
+#define NVMCTRL_PARAM_PSZ_8_Val 0x0u /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define NVMCTRL_PARAM_PSZ_16_Val 0x1u /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define NVMCTRL_PARAM_PSZ_32_Val 0x2u /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define NVMCTRL_PARAM_PSZ_64_Val 0x3u /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define NVMCTRL_PARAM_PSZ_128_Val 0x4u /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define NVMCTRL_PARAM_PSZ_256_Val 0x5u /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define NVMCTRL_PARAM_PSZ_512_Val 0x6u /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define NVMCTRL_PARAM_PSZ_1024_Val 0x7u /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_MASK 0x0007FFFFu /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY (0x1u << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR (0x1u << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK 0x03u /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY (0x1u << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR (0x1u << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK 0x03u /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ uint8_t ERROR:1; /*!< bit: 1 Error */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY (0x1u << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR (0x1u << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK 0x03u /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE 0x0000 /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM (0x1u << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD (0x1u << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE (0x1u << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE (0x1u << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME (0x1u << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB (0x1u << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK 0x011Fu /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFu << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
+#define NVMCTRL_ADDR_MASK 0x003FFFFFu /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFu << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
+#define NVMCTRL_LOCK_MASK 0xFFFFu /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_NVMCTRL_CAL
+#define SECTION_NVMCTRL_LOCKBIT
+#define SECTION_NVMCTRL_OTP1
+#define SECTION_NVMCTRL_OTP2
+#define SECTION_NVMCTRL_OTP4
+#define SECTION_NVMCTRL_TEMP_LOG
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk (0x7u << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
+
+#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk (0x1Fu << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
+
+#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk (0x7u << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7u << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7u << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
+
+#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
+
+#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
+#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFu << NVMCTRL_FUSES_NVMP_Pos)
+#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
+
+#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
+#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFu << NVMCTRL_FUSES_NVM_LOCK_Pos)
+#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
+
+#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
+#define NVMCTRL_FUSES_PSZ_Msk (0xFu << NVMCTRL_FUSES_PSZ_Pos)
+#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFu << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
+#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
+#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define SYSCTRL_FUSES_BOD33_EN_Msk (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
+
+#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define SYSCTRL_FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
+
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
+#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
+
+#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk (0x1Fu << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)))
+
+#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk (0x1Fu << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)))
+
+#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk (0x7u << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)))
+
+#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk (0x1u << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk (0x1u << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk (0xFu << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
+
+#define WDT_FUSES_PER_ADDR NVMCTRL_USER
+#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk (0xFu << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
+
+#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk (0x1u << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk (0x1u << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk (0x7u << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h
new file mode 100755
index 0000000000000000000000000000000000000000..e175508b27b6b149aa616f846a64537c9ccc061f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h
@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC_COMPONENT_
+#define _SAMD21_PAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC 0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE 0x00000000 /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk (0x7FFFFFFFu << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))
+#define PAC_WPCLR_MASK 0xFFFFFFFEu /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE 0x00000000 /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk (0x7FFFFFFFu << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))
+#define PAC_WPSET_MASK 0xFFFFFFFEu /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PAC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h
new file mode 100755
index 0000000000000000000000000000000000000000..055d49c5469d972cc663652a66937393ab9d1e73
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h
@@ -0,0 +1,530 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM 0x201
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint8_t reg; /*!< Type used for register access */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE 0x00 /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK 0x00u /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE 0x00 /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk (0x3u << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
+#define PM_SLEEP_IDLE_CPU_Val 0x0u /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define PM_SLEEP_IDLE_AHB_Val 0x1u /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define PM_SLEEP_IDLE_APB_Val 0x2u /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK 0x03u /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE 0x00 /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk (0x7u << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
+#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0u /**< \brief (PM_CPUSEL) Divide by 1 */
+#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1u /**< \brief (PM_CPUSEL) Divide by 2 */
+#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2u /**< \brief (PM_CPUSEL) Divide by 4 */
+#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3u /**< \brief (PM_CPUSEL) Divide by 8 */
+#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4u /**< \brief (PM_CPUSEL) Divide by 16 */
+#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5u /**< \brief (PM_CPUSEL) Divide by 32 */
+#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6u /**< \brief (PM_CPUSEL) Divide by 64 */
+#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7u /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK 0x07u /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE 0x00 /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk (0x7u << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
+#define PM_APBASEL_APBADIV_DIV1_Val 0x0u /**< \brief (PM_APBASEL) Divide by 1 */
+#define PM_APBASEL_APBADIV_DIV2_Val 0x1u /**< \brief (PM_APBASEL) Divide by 2 */
+#define PM_APBASEL_APBADIV_DIV4_Val 0x2u /**< \brief (PM_APBASEL) Divide by 4 */
+#define PM_APBASEL_APBADIV_DIV8_Val 0x3u /**< \brief (PM_APBASEL) Divide by 8 */
+#define PM_APBASEL_APBADIV_DIV16_Val 0x4u /**< \brief (PM_APBASEL) Divide by 16 */
+#define PM_APBASEL_APBADIV_DIV32_Val 0x5u /**< \brief (PM_APBASEL) Divide by 32 */
+#define PM_APBASEL_APBADIV_DIV64_Val 0x6u /**< \brief (PM_APBASEL) Divide by 64 */
+#define PM_APBASEL_APBADIV_DIV128_Val 0x7u /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK 0x07u /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE 0x00 /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk (0x7u << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
+#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0u /**< \brief (PM_APBBSEL) Divide by 1 */
+#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1u /**< \brief (PM_APBBSEL) Divide by 2 */
+#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2u /**< \brief (PM_APBBSEL) Divide by 4 */
+#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3u /**< \brief (PM_APBBSEL) Divide by 8 */
+#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4u /**< \brief (PM_APBBSEL) Divide by 16 */
+#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5u /**< \brief (PM_APBBSEL) Divide by 32 */
+#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6u /**< \brief (PM_APBBSEL) Divide by 64 */
+#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7u /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK 0x07u /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE 0x00 /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk (0x7u << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
+#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0u /**< \brief (PM_APBCSEL) Divide by 1 */
+#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1u /**< \brief (PM_APBCSEL) Divide by 2 */
+#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2u /**< \brief (PM_APBCSEL) Divide by 4 */
+#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3u /**< \brief (PM_APBCSEL) Divide by 8 */
+#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4u /**< \brief (PM_APBCSEL) Divide by 16 */
+#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5u /**< \brief (PM_APBCSEL) Divide by 32 */
+#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6u /**< \brief (PM_APBCSEL) Divide by 64 */
+#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7u /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK 0x07u /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HPB0:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE 0x0000007F /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0 (0x1u << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1 (0x1u << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2 (0x1u << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU (0x1u << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL (0x1u << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC (0x1u << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB (0x1u << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK 0x0000007Fu /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC0:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0 (0x1u << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM (0x1u << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL (0x1u << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK (0x1u << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT (0x1u << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC (0x1u << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC (0x1u << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK 0x0000007Fu /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC1:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t :26; /*!< bit: 6..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1 (0x1u << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU (0x1u << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL (0x1u << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT (0x1u << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC (0x1u << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB (0x1u << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_MASK 0x0000003Fu /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC2:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t TC6:1; /*!< bit: 14 TC6 APB Clock Enable */
+ uint32_t TC7:1; /*!< bit: 15 TC7 APB Clock Enable */
+ uint32_t ADC:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t DAC:1; /*!< bit: 18 DAC APB Clock Enable */
+ uint32_t PTC:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t I2S:1; /*!< bit: 20 I2S APB Clock Enable */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE 0x00010000 /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2 (0x1u << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS (0x1u << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0 (0x1u << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1 (0x1u << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2 (0x1u << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3 (0x1u << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4 (0x1u << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5 (0x1u << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0 (0x1u << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1 (0x1u << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2 (0x1u << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3 (0x1u << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4 (0x1u << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5 (0x1u << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6 (0x1u << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7 (0x1u << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC (0x1u << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC (0x1u << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC (0x1u << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC (0x1u << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S (0x1u << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_MASK 0x001FFFFFu /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE 0x00 /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY (0x1u << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK 0x01u /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE 0x00 /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY (0x1u << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK 0x01u /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE 0x00 /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY (0x1u << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK 0x01u /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE 0x01 /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR (0x1u << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12 (0x1u << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33 (0x1u << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT (0x1u << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT (0x1u << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST (0x1u << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK 0x77u /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ RoReg8 Reserved1[0x6];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h
new file mode 100755
index 0000000000000000000000000000000000000000..77365b54d8da9f0b4a24ff10e0d0d411f245af66
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h
@@ -0,0 +1,395 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_COMPONENT_
+#define _SAMD21_PORT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT 0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE 0x00000000 /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk (0xFFFFFFFFu << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
+#define PORT_DIR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE 0x00000000 /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFu << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
+#define PORT_DIRCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE 0x00000000 /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFu << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
+#define PORT_DIRSET_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE 0x00000000 /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFu << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
+#define PORT_DIRTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE 0x00000000 /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk (0xFFFFFFFFu << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
+#define PORT_OUT_MASK 0xFFFFFFFFu /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE 0x00000000 /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFu << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
+#define PORT_OUTCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE 0x00000000 /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFu << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
+#define PORT_OUTSET_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE 0x00000000 /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFu << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
+#define PORT_OUTTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE 0x00000000 /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk (0xFFFFFFFFu << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
+#define PORT_IN_MASK 0xFFFFFFFFu /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE 0x00000000 /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFu << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
+#define PORT_CTRL_MASK 0xFFFFFFFFu /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE 0x00000000 /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFu << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
+#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN (0x1u << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN (0x1u << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN (0x1u << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR (0x1u << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk (0xFu << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
+#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX (0x1u << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG (0x1u << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL (0x1u << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK 0xDF47FFFFu /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE 0x00 /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk (0xFu << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
+#define PORT_PMUX_PMUXE_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define PORT_PMUX_PMUXE_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define PORT_PMUX_PMUXE_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define PORT_PMUX_PMUXE_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define PORT_PMUX_PMUXE_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define PORT_PMUX_PMUXE_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define PORT_PMUX_PMUXE_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define PORT_PMUX_PMUXE_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk (0xFu << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
+#define PORT_PMUX_PMUXO_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define PORT_PMUX_PMUXO_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define PORT_PMUX_PMUXO_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define PORT_PMUX_PMUXO_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define PORT_PMUX_PMUXO_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define PORT_PMUX_PMUXO_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define PORT_PMUX_PMUXO_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define PORT_PMUX_PMUXO_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK 0xFFu /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE 0x00 /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN (0x1u << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN (0x1u << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN (0x1u << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR (0x1u << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK 0x47u /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_PORT_IOBUS
+
+/*@}*/
+
+#endif /* _SAMD21_PORT_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h
new file mode 100755
index 0000000000000000000000000000000000000000..0fe36bb8a3cf8f63cb4564b2ffe97889cd676f7a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h
@@ -0,0 +1,1062 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_COMPONENT_
+#define _SAMD21_RTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC 0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST (0x1u << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE (0x1u << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk (0x3u << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
+#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0u /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1u /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2u /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR (0x1u << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFu << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
+#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9u /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAu /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK 0x0F8Fu /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST (0x1u << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE (0x1u << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk (0x3u << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
+#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0u /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1u /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2u /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFu << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
+#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9u /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAu /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK 0x0F0Fu /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST (0x1u << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE (0x1u << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk (0x3u << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
+#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0u /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1u /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2u /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP (0x1u << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR (0x1u << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFu << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
+#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9u /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAu /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK 0x0FCFu /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE 0x0010 /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk (0x3Fu << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
+#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT (0x1u << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ (0x1u << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK 0xC03Fu /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1u << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO (0x1u << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK 0x81FFu /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3u << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO (0x1u << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK 0x83FFu /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000 /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFu << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1u << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO (0x1u << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK 0x81FFu /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk (0x1u << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY (0x1u << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF (0x1u << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK 0xC1u /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk (0x3u << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY (0x1u << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF (0x1u << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK 0xC3u /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1u << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY (0x1u << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF (0x1u << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK 0xC1u /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk (0x1u << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY (0x1u << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF (0x1u << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK 0xC1u /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk (0x3u << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY (0x1u << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF (0x1u << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK 0xC3u /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1u << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY (0x1u << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF (0x1u << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK 0xC1u /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk (0x1u << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY (0x1u << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF (0x1u << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK 0xC1u /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk (0x3u << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY (0x1u << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF (0x1u << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK 0xC3u /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00 /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1u << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY (0x1u << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF (0x1u << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK 0xC1u /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE 0x00 /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY (0x1u << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK 0x80u /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE 0x00 /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN (0x1u << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK 0x01u /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE 0x00 /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk (0x7Fu << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
+#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN (0x1u << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK 0xFFu /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE 0x00000000 /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFu << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
+#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFu << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
+#define RTC_MODE1_COUNT_MASK 0xFFFFu /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000 /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Fu << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
+#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Fu << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
+#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Fu << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
+#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10u /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
+#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk (0x1Fu << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
+#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk (0xFu << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
+#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Fu << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
+#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk (0xFFFFu << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
+#define RTC_MODE1_PER_MASK 0xFFFFu /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE 0x00000000 /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFu << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
+#define RTC_MODE0_COMP_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE 0x0000 /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk (0xFFFFu << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
+#define RTC_MODE1_COMP_MASK 0xFFFFu /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE 0x00000000 /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk (0x3Fu << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
+#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Fu << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
+#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk (0x1Fu << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
+#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk (0x1Fu << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
+#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk (0xFu << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
+#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk (0x3Fu << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
+#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFu /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE 0x00 /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk (0x7u << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
+#define RTC_MODE2_MASK_SEL_OFF_Val 0x0u /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define RTC_MODE2_MASK_SEL_SS_Val 0x1u /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2u /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6u /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK 0x07u /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_RTC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h
new file mode 100755
index 0000000000000000000000000000000000000000..c27d9da5af61f87f9ed5d652d2ef8d1036dacc9c
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h
@@ -0,0 +1,1508 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM_COMPONENT_
+#define _SAMD21_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM 0x200
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST (0x1u << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE (0x1u << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7u << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1u << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT (0x1u << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3u << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1u << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1u << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3u << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM (0x1u << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3u << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1u << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Fu /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST (0x1u << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE (0x1u << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7u << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1u << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT (0x1u << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3u << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1u << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3u << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM (0x1u << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1u << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Fu /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST (0x1u << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE (0x1u << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk (0x7u << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1u << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON (0x1u << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3u << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
+#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3u << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
+#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk (0xFu << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
+#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA (0x1u << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL (0x1u << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD (0x1u << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK 0x7F33019Fu /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST (0x1u << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE (0x1u << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7u << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0u /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1u /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2u /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3u /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4u /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5u /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1u << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON (0x1u << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7u << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (0x3u << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3u << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3u << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
+#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFu << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE (0x1u << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL (0x1u << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD (0x1u << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Fu /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN (0x1u << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN (0x1u << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3u << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT (0x1u << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK 0x00070300u /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN (0x1u << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD (0x1u << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN (0x1u << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3u << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
+#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3u << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT (0x1u << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK 0x0007C700u /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7u << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN (0x1u << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE (0x1u << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN (0x1u << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3u << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
+#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN (0x1u << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK 0x0002E247u /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7u << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE (0x1u << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN (0x1u << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE (0x1u << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC (0x1u << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE (0x1u << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN (0x1u << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN (0x1u << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK 0x00032747u /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFu << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFu << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFu << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFu << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
+#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFu /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFu << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
+#define SERCOM_SPI_BAUD_MASK 0xFFu /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFu << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
+#define SERCOM_USART_BAUD_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFu << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7u << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
+#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFu << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7u << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
+#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFu << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
+#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFu /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE 0x00 /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk (0xFFu << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
+#define SERCOM_USART_RXPL_MASK 0xFFu /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB (0x1u << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB (0x1u << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR (0x1u << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK 0x83u /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC (0x1u << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1u << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY (0x1u << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR (0x1u << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK 0x87u /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE (0x1u << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC (0x1u << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC (0x1u << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL (0x1u << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR (0x1u << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK 0x8Fu /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE (0x1u << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC (0x1u << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC (0x1u << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS (0x1u << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (0x1u << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (0x1u << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (0x1u << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK 0xBFu /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB (0x1u << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB (0x1u << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR (0x1u << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK 0x83u /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC (0x1u << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1u << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY (0x1u << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR (0x1u << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK 0x87u /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE (0x1u << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC (0x1u << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC (0x1u << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL (0x1u << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR (0x1u << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK 0x8Fu /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE (0x1u << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC (0x1u << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC (0x1u << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS (0x1u << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (0x1u << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (0x1u << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (0x1u << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK 0xBFu /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB (0x1u << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB (0x1u << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR (0x1u << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK 0x83u /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC (0x1u << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH (0x1u << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY (0x1u << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR (0x1u << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK 0x87u /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE (0x1u << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC (0x1u << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC (0x1u << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL (0x1u << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR (0x1u << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK 0x8Fu /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00 /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE (0x1u << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC (0x1u << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC (0x1u << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS (0x1u << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC (0x1u << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK (0x1u << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR (0x1u << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK 0xBFu /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR (0x1u << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST (0x1u << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK (0x1u << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3u << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT (0x1u << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD (0x1u << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1u << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1u << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR (0x1u << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK 0x07F7u /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR (0x1u << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL (0x1u << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK (0x1u << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR (0x1u << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR (0x1u << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT (0x1u << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD (0x1u << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1u << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS (0x1u << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_MASK 0x06DFu /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF (0x1u << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_MASK 0x0004u /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR (0x1u << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR (0x1u << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF (0x1u << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS (0x1u << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF (0x1u << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL (0x1u << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_MASK 0x003Fu /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1u << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1u << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1u << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007u /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1u << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1u << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003u /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST (0x1u << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1u << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1u << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007u /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (0x1u << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (0x1u << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (0x1u << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK 0x00000007u /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFu << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
+#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN (0x1u << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS (0x1u << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN (0x1u << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFu << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
+#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFu /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN (0x1u << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFu << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN (0x1u << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFu << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
+#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFu /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFu << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFu << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
+#define SERCOM_SPI_ADDR_MASK 0x00FF00FFu /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk (0xFFu << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
+#define SERCOM_I2CM_DATA_MASK 0xFFu /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00 /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk (0xFFu << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
+#define SERCOM_I2CS_DATA_MASK 0xFFu /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE 0x00000000 /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk (0x1FFu << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
+#define SERCOM_SPI_DATA_MASK 0x000001FFu /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE 0x0000 /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk (0x1FFu << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
+#define SERCOM_USART_DATA_MASK 0x01FFu /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1u << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1u << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00 /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1u << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK 0x01u /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h
new file mode 100755
index 0000000000000000000000000000000000000000..00980e4552954772b77ee890134ff28d2f083c61
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h
@@ -0,0 +1,948 @@
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_COMPONENT_
+#define _SAMD21_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSCRDY (0x1u << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1u << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC32KRDY (0x1u << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC8MRDY (0x1u << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRDY (0x1u << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLOOB (0x1u << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKF (0x1u << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKC (0x1u << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRCS (0x1u << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33RDY (0x1u << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33DET (0x1u << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_B33SRDY (0x1u << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKR (0x1u << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKF (0x1u << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLTO (0x1u << SYSCTRL_INTENCLR_DPLLLTO_Pos)
+#define SYSCTRL_INTENCLR_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSCRDY (0x1u << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1u << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC32KRDY (0x1u << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC8MRDY (0x1u << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRDY (0x1u << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLOOB (0x1u << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKF (0x1u << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKC (0x1u << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRCS (0x1u << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33RDY (0x1u << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33DET (0x1u << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_B33SRDY (0x1u << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKR (0x1u << SYSCTRL_INTENSET_DPLLLCKR_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKF (0x1u << SYSCTRL_INTENSET_DPLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLTO (0x1u << SYSCTRL_INTENSET_DPLLLTO_Pos)
+#define SYSCTRL_INTENSET_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY (0x1u << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1u << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY (0x1u << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY (0x1u << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY (0x1u << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB (0x1u << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF (0x1u << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC (0x1u << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS (0x1u << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY (0x1u << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET (0x1u << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY (0x1u << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
+#define SYSCTRL_INTFLAG_DPLLLCKR (0x1u << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
+#define SYSCTRL_INTFLAG_DPLLLCKF (0x1u << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
+#define SYSCTRL_INTFLAG_DPLLLTO (0x1u << SYSCTRL_INTFLAG_DPLLLTO_Pos)
+#define SYSCTRL_INTFLAG_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY (0x1u << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1u << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY (0x1u << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY (0x1u << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY (0x1u << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB (0x1u << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF (0x1u << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC (0x1u << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS (0x1u << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY (0x1u << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET (0x1u << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY (0x1u << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
+#define SYSCTRL_PCLKSR_DPLLLCKR (0x1u << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
+#define SYSCTRL_PCLKSR_DPLLLCKF (0x1u << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
+#define SYSCTRL_PCLKSR_DPLLLTO (0x1u << SYSCTRL_PCLKSR_DPLLLTO_Pos)
+#define SYSCTRL_PCLKSR_MASK 0x00038FFFu /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define SYSCTRL_XOSC_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
+#define SYSCTRL_XOSC_ENABLE (0x1u << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN (0x1u << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
+#define SYSCTRL_XOSC_RUNSTDBY (0x1u << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
+#define SYSCTRL_XOSC_ONDEMAND (0x1u << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
+#define SYSCTRL_XOSC_GAIN_Msk (0x7u << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
+#define SYSCTRL_XOSC_GAIN_0_Val 0x0u /**< \brief (SYSCTRL_XOSC) 2MHz */
+#define SYSCTRL_XOSC_GAIN_1_Val 0x1u /**< \brief (SYSCTRL_XOSC) 4MHz */
+#define SYSCTRL_XOSC_GAIN_2_Val 0x2u /**< \brief (SYSCTRL_XOSC) 8MHz */
+#define SYSCTRL_XOSC_GAIN_3_Val 0x3u /**< \brief (SYSCTRL_XOSC) 16MHz */
+#define SYSCTRL_XOSC_GAIN_4_Val 0x4u /**< \brief (SYSCTRL_XOSC) 30MHz */
+#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC (0x1u << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk (0xFu << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
+#define SYSCTRL_XOSC_MASK 0xFFC6u /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define SYSCTRL_XOSC32K_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
+#define SYSCTRL_XOSC32K_ENABLE (0x1u << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN (0x1u << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K (0x1u << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K (0x1u << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN (0x1u << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY (0x1u << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
+#define SYSCTRL_XOSC32K_ONDEMAND (0x1u << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7u << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK (0x1u << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK 0x17FEu /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080 /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
+#define SYSCTRL_OSC32K_ENABLE (0x1u << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K (0x1u << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K (0x1u << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY (0x1u << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
+#define SYSCTRL_OSC32K_ONDEMAND (0x1u << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk (0x7u << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK (0x1u << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
+#define SYSCTRL_OSC32K_CALIB_Msk (0x7Fu << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
+#define SYSCTRL_OSC32K_MASK 0x007F17CEu /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x1F /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Fu << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK (0x1u << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK 0x9Fu /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
+#define SYSCTRL_OSC8M_RESETVALUE 0x87070382 /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
+#define SYSCTRL_OSC8M_ENABLE (0x1u << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY (0x1u << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
+#define SYSCTRL_OSC8M_ONDEMAND (0x1u << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
+#define SYSCTRL_OSC8M_PRESC_Msk (0x3u << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
+#define SYSCTRL_OSC8M_PRESC_0_Val 0x0u /**< \brief (SYSCTRL_OSC8M) 1 */
+#define SYSCTRL_OSC8M_PRESC_1_Val 0x1u /**< \brief (SYSCTRL_OSC8M) 2 */
+#define SYSCTRL_OSC8M_PRESC_2_Val 0x2u /**< \brief (SYSCTRL_OSC8M) 4 */
+#define SYSCTRL_OSC8M_PRESC_3_Val 0x3u /**< \brief (SYSCTRL_OSC8M) 8 */
+#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
+#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFu << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
+#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk (0x3u << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
+#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0u /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
+#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1u /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
+#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2u /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
+#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3u /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
+#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_MASK 0xCFFF03C2u /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080 /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE (0x1u << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE (0x1u << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE (0x1u << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW (0x1u << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define SYSCTRL_DFLLCTRL_USBCRM (0x1u << SYSCTRL_DFLLCTRL_USBCRM_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1u << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
+#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1u << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS (0x1u << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS (0x1u << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define SYSCTRL_DFLLCTRL_BPLCKC (0x1u << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
+#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
+#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1u << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define SYSCTRL_DFLLCTRL_MASK 0x0FFEu /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFu << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
+#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Fu << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
+#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFu << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
+#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFu /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
+#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFu << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFu << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Fu << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
+#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFu /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00 /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
+#define SYSCTRL_DFLLSYNC_READREQ (0x1u << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK 0x80u /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE (0x1u << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
+#define SYSCTRL_BOD33_HYST (0x1u << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
+#define SYSCTRL_BOD33_ACTION_Msk (0x3u << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
+#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0u /**< \brief (SYSCTRL_BOD33) No action */
+#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1u /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
+#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2u /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
+#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
+#define SYSCTRL_BOD33_RUNSTDBY (0x1u << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
+#define SYSCTRL_BOD33_MODE (0x1u << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN (0x1u << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk (0xFu << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
+#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0u /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
+#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1u /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
+#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2u /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
+#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3u /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
+#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4u /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
+#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5u /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
+#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6u /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
+#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7u /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
+#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8u /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
+#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9u /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
+#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAu /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
+#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBu /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
+#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCu /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
+#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDu /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
+#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEu /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
+#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFu /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
+#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk (0x3Fu << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
+#define SYSCTRL_BOD33_MASK 0x003FF35Eu /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
+#define SYSCTRL_VREG_RESETVALUE 0x0000 /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
+#define SYSCTRL_VREG_RUNSTDBY (0x1u << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO (0x1u << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK 0x2040u /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
+#define SYSCTRL_VREF_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
+
+#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
+#define SYSCTRL_VREF_TSEN (0x1u << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN (0x1u << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
+#define SYSCTRL_VREF_CALIB_Msk (0x7FFu << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
+#define SYSCTRL_VREF_MASK 0x07FF0006u /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
+#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80 /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
+#define SYSCTRL_DPLLCTRLA_ENABLE (0x1u << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1u << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
+#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1u << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define SYSCTRL_DPLLCTRLA_MASK 0xC2u /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
+#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFu << SYSCTRL_DPLLRATIO_LDR_Pos)
+#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFu << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
+#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFu /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
+#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3u << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1u /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2u /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3u /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
+#define SYSCTRL_DPLLCTRLB_LPEN (0x1u << SYSCTRL_DPLLCTRLB_LPEN_Pos)
+#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
+#define SYSCTRL_DPLLCTRLB_WUF (0x1u << SYSCTRL_DPLLCTRLB_WUF_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
+#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3u << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1u /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2u /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
+#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7u << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
+#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1u << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
+#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFu << SYSCTRL_DPLLCTRLB_DIV_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
+#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Fu /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
+#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00 /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
+#define SYSCTRL_DPLLSTATUS_LOCK (0x1u << SYSCTRL_DPLLSTATUS_LOCK_Pos)
+#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
+#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1u << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
+#define SYSCTRL_DPLLSTATUS_ENABLE (0x1u << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
+#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
+#define SYSCTRL_DPLLSTATUS_DIV (0x1u << SYSCTRL_DPLLSTATUS_DIV_Pos)
+#define SYSCTRL_DPLLSTATUS_MASK 0x0Fu /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h
new file mode 100755
index 0000000000000000000000000000000000000000..1ed1557615ac6f81244e57eab296cb79202b0b54
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC_COMPONENT_
+#define _SAMD21_TC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC 0x121
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE 0x0000 /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST (0x1u << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE (0x1u << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk (0x3u << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
+#define TC_CTRLA_MODE_COUNT16_Val 0x0u /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define TC_CTRLA_MODE_COUNT8_Val 0x1u /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define TC_CTRLA_MODE_COUNT32_Val 0x2u /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk (0x3u << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
+#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0u /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1u /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2u /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3u /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk (0x7u << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
+#define TC_CTRLA_PRESCALER_DIV1_Val 0x0u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define TC_CTRLA_PRESCALER_DIV2_Val 0x1u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define TC_CTRLA_PRESCALER_DIV4_Val 0x2u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define TC_CTRLA_PRESCALER_DIV8_Val 0x3u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define TC_CTRLA_PRESCALER_DIV16_Val 0x4u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define TC_CTRLA_PRESCALER_DIV64_Val 0x5u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define TC_CTRLA_PRESCALER_DIV256_Val 0x6u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY (0x1u << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk (0x3u << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
+#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0u /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1u /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2u /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK 0x3F6Fu /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE 0x0000 /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk (0x1Fu << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
+#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT (0x1u << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ (0x1u << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK 0xC01Fu /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE 0x02 /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR (0x1u << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT (0x1u << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk (0x3u << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
+#define TC_CTRLBCLR_CMD_NONE_Val 0x0u /**< \brief (TC_CTRLBCLR) No action */
+#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1u /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define TC_CTRLBCLR_CMD_STOP_Val 0x2u /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK 0xC5u /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE 0x00 /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR (0x1u << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
+#define TC_CTRLBSET_ONESHOT (0x1u << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk (0x3u << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
+#define TC_CTRLBSET_CMD_NONE_Val 0x0u /**< \brief (TC_CTRLBSET) No action */
+#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1u /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define TC_CTRLBSET_CMD_STOP_Val 0x2u /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK 0xC5u /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE 0x00 /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk (0x3u << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
+#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk (0x3u << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
+#define TC_CTRLC_MASK 0x33u /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE 0x00 /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN (0x1u << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK 0x01u /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE 0x0000 /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk (0x7u << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
+#define TC_EVCTRL_EVACT_OFF_Val 0x0u /**< \brief (TC_EVCTRL) Event action disabled */
+#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1u /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define TC_EVCTRL_EVACT_COUNT_Val 0x2u /**< \brief (TC_EVCTRL) Count on event */
+#define TC_EVCTRL_EVACT_START_Val 0x3u /**< \brief (TC_EVCTRL) Start TC on event */
+#define TC_EVCTRL_EVACT_PPW_Val 0x5u /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
+#define TC_EVCTRL_EVACT_PWP_Val 0x6u /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV (0x1u << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI (0x1u << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO (0x1u << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk (0x3u << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
+#define TC_EVCTRL_MASK 0x3137u /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE 0x00 /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF (0x1u << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR (0x1u << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY (0x1u << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk (0x3u << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
+#define TC_INTENCLR_MASK 0x3Bu /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE 0x00 /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF (0x1u << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR (0x1u << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY (0x1u << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk (0x3u << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
+#define TC_INTENSET_MASK 0x3Bu /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow */
+ uint8_t ERR:1; /*!< bit: 1 Error */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE 0x00 /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF (0x1u << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR (0x1u << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY (0x1u << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk (0x3u << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
+#define TC_INTFLAG_MASK 0x3Bu /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE 0x08 /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP (0x1u << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE (0x1u << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY (0x1u << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK 0x98u /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
+#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFu << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
+#define TC_COUNT16_COUNT_MASK 0xFFFFu /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
+#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFu << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
+#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE 0x00 /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk (0xFFu << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
+#define TC_COUNT8_COUNT_MASK 0xFFu /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE 0xFF /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk (0xFFu << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
+#define TC_COUNT8_PER_MASK 0xFFu /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk (0xFFFFu << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
+#define TC_COUNT16_CC_MASK 0xFFFFu /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFu << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
+#define TC_COUNT32_CC_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE 0x00 /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk (0xFFu << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
+#define TC_COUNT8_CC_MASK 0xFFu /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h
new file mode 100755
index 0000000000000000000000000000000000000000..65fad45840b0f4636a4e67762effca142a62e389
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h
@@ -0,0 +1,1608 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC 0x101
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE 0x00000000 /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST (0x1u << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE (0x1u << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk (0x3u << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
+#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0u /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1u /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection. */
+#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2u /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection. */
+#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3u /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection. */
+#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk (0x7u << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
+#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC */
+#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/2 */
+#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/4 */
+#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/8 */
+#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/16 */
+#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/64 */
+#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/256 */
+#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7u /**< \brief (TCC_CTRLA) Prescaler: GCLK_TCC/1024 */
+#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY (0x1u << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk (0x3u << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
+#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0u /**< \brief (TCC_CTRLA) Reload or reset Counter on next GCLK */
+#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1u /**< \brief (TCC_CTRLA) Reload or reset Counter on next prescaler clock */
+#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2u /**< \brief (TCC_CTRLA) Reload or reset Counter on next GCLK */
+#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK (0x1u << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk (0xFu << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
+#define TCC_CTRLA_MASK 0x0F007F63u /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE 0x00 /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR (0x1u << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD (0x1u << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT (0x1u << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk (0x3u << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
+#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0u /**< \brief (TCC_CTRLBCLR) Command disabled: IDX toggles between cycles A and B */
+#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1u /**< \brief (TCC_CTRLBCLR) Set IDX: cycle B will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2u /**< \brief (TCC_CTRLBCLR) Clear IDX: cycle A will be forced in next cycle */
+#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3u /**< \brief (TCC_CTRLBCLR) Hold IDX: the next cycle will be the same as the current cycle. */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk (0x7u << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
+#define TCC_CTRLBCLR_CMD_NONE_Val 0x0u /**< \brief (TCC_CTRLBCLR) No action */
+#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1u /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define TCC_CTRLBCLR_CMD_STOP_Val 0x2u /**< \brief (TCC_CTRLBCLR) Force stop */
+#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3u /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4u /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK 0xFFu /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE 0x00 /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR (0x1u << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock update */
+#define TCC_CTRLBSET_LUPD (0x1u << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT (0x1u << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk (0x3u << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
+#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk (0x7u << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
+#define TCC_CTRLBSET_CMD_NONE_Val 0x0u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_CMD_STOP_Val 0x2u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4u /**< \brief (TCC_CTRLBSET) */
+#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK 0xFFu /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel Buffer 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel Buffer 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel Buffer 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel Buffer 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel Buffer x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE 0x00000000 /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST (0x1u << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE (0x1u << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB (0x1u << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS (0x1u << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT (0x1u << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT (0x1u << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE (0x1u << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER (0x1u << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CC_Msk (0xFu << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
+#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB (0x1u << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB (0x1u << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB (0x1u << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk (0xFu << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
+#define TCC_SYNCBUSY_MASK 0x007F0FFFu /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable FaultA Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 FaultA Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 FaultA Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 FaultA Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 FaultA Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 FaultA Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 FaultA Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 FaultA Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 FaultA Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 FaultA Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 FaultA Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable FaultA Configuration */
+#define TCC_FCTRLA_RESETVALUE 0x00000000 /**< \brief (TCC_FCTRLA reset_value) Recoverable FaultA Configuration */
+
+#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) FaultA Source */
+#define TCC_FCTRLA_SRC_Msk (0x3u << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
+#define TCC_FCTRLA_SRC_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_SRC_ENABLE_Val 0x1u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_SRC_INVERT_Val 0x2u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) FaultA Keeper */
+#define TCC_FCTRLA_KEEP (0x1u << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) FaultA Qualification */
+#define TCC_FCTRLA_QUAL (0x1u << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) FaultA Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk (0x3u << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
+#define TCC_FCTRLA_BLANK_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_BLANK_RISE_Val 0x1u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_BLANK_FALL_Val 0x2u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_BLANK_BOTH_Val 0x3u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_BLANK_DISABLE (TCC_FCTRLA_BLANK_DISABLE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) FaultA Restart */
+#define TCC_FCTRLA_RESTART (0x1u << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) FaultA Halt Mode */
+#define TCC_FCTRLA_HALT_Msk (0x3u << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
+#define TCC_FCTRLA_HALT_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_HALT_HW_Val 0x1u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_HALT_SW_Val 0x2u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_HALT_NR_Val 0x3u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) FaultA Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk (0x3u << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
+#define TCC_FCTRLA_CHSEL_CC0_Val 0x0u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CHSEL_CC1_Val 0x1u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CHSEL_CC2_Val 0x2u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CHSEL_CC3_Val 0x3u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) FaultA Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk (0x7u << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
+#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6u /**< \brief (TCC_FCTRLA) */
+#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) FaultA Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk (0xFFu << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
+#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) FaultA Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk (0xFu << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
+#define TCC_FCTRLA_MASK 0x0FFF7FFBu /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable FaultB Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 FaultB Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 FaultB Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 FaultB Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 FaultB Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 FaultB Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 FaultB Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 FaultB Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 FaultB Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 FaultB Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 FaultB Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable FaultB Configuration */
+#define TCC_FCTRLB_RESETVALUE 0x00000000 /**< \brief (TCC_FCTRLB reset_value) Recoverable FaultB Configuration */
+
+#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) FaultB Source */
+#define TCC_FCTRLB_SRC_Msk (0x3u << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
+#define TCC_FCTRLB_SRC_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_SRC_ENABLE_Val 0x1u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_SRC_INVERT_Val 0x2u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) FaultB Keeper */
+#define TCC_FCTRLB_KEEP (0x1u << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) FaultB Qualification */
+#define TCC_FCTRLB_QUAL (0x1u << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) FaultB Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk (0x3u << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
+#define TCC_FCTRLB_BLANK_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_BLANK_RISE_Val 0x1u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_BLANK_FALL_Val 0x2u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_BLANK_BOTH_Val 0x3u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_BLANK_DISABLE (TCC_FCTRLB_BLANK_DISABLE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) FaultB Restart */
+#define TCC_FCTRLB_RESTART (0x1u << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) FaultB Halt Mode */
+#define TCC_FCTRLB_HALT_Msk (0x3u << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
+#define TCC_FCTRLB_HALT_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_HALT_HW_Val 0x1u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_HALT_SW_Val 0x2u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_HALT_NR_Val 0x3u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) FaultB Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk (0x3u << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
+#define TCC_FCTRLB_CHSEL_CC0_Val 0x0u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CHSEL_CC1_Val 0x1u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CHSEL_CC2_Val 0x2u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CHSEL_CC3_Val 0x3u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) FaultB Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk (0x7u << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
+#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6u /**< \brief (TCC_FCTRLB) */
+#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) FaultB Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk (0xFFu << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
+#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) FaultB Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk (0xFu << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
+#define TCC_FCTRLB_MASK 0x0FFF7FFBu /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE 0x00000000 /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk (0x3u << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
+#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk (0xFu << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
+#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk (0xFFu << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
+#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk (0xFFu << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
+#define TCC_WEXCTRL_MASK 0xFFFF0F03u /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Configuration */
+#define TCC_DRVCTRL_RESETVALUE 0x00000000 /**< \brief (TCC_DRVCTRL reset_value) Driver Configuration */
+
+#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk (0xFFu << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
+#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk (0xFFu << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
+#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk (0xFFu << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
+#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFu << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
+#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFu << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
+#define TCC_DRVCTRL_MASK 0xFFFFFFFFu /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE 0x00 /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN (0x1u << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD (0x1u << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK 0x05u /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE 0x00000000 /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk (0x7u << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
+#define TCC_EVCTRL_EVACT0_OFF_Val 0x0u /**< \brief (TCC_EVCTRL) Event action disabled. */
+#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1u /**< \brief (TCC_EVCTRL) Start restart or re-trigger TC on event */
+#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2u /**< \brief (TCC_EVCTRL) Count on event. Increment or decrement depending on count direction. */
+#define TCC_EVCTRL_EVACT0_START_Val 0x3u /**< \brief (TCC_EVCTRL) Count on event.Start counting on the event rising edge. Further events will not restart the counter; it keeps on counting using prescaled GCLK_TCCx, until it reaches TOP or Zero depending on the direction. */
+#define TCC_EVCTRL_EVACT0_INC_Val 0x4u /**< \brief (TCC_EVCTRL) Increment TC on EVENT. Increment the counter on event, irrespective of count direction */
+#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5u /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7u /**< \brief (TCC_EVCTRL) Non-recoverable Fault */
+#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk (0x7u << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
+#define TCC_EVCTRL_EVACT1_OFF_Val 0x0u /**< \brief (TCC_EVCTRL) Event action disabled. */
+#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1u /**< \brief (TCC_EVCTRL) Re-trigger TC on event */
+#define TCC_EVCTRL_EVACT1_DIR_Val 0x2u /**< \brief (TCC_EVCTRL) Direction control */
+#define TCC_EVCTRL_EVACT1_STOP_Val 0x3u /**< \brief (TCC_EVCTRL) Stop TC on event */
+#define TCC_EVCTRL_EVACT1_DEC_Val 0x4u /**< \brief (TCC_EVCTRL) Decrement TC on event */
+#define TCC_EVCTRL_EVACT1_PPW_Val 0x5u /**< \brief (TCC_EVCTRL) Period captured into CC0 Pulse Width on CC1 */
+#define TCC_EVCTRL_EVACT1_PWP_Val 0x6u /**< \brief (TCC_EVCTRL) Period captured into CC1 Pulse Width on CC0 */
+#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7u /**< \brief (TCC_EVCTRL) Non-recoverable Fault */
+#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk (0x3u << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
+#define TCC_EVCTRL_CNTSEL_START_Val 0x0u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define TCC_EVCTRL_CNTSEL_END_Val 0x1u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles. */
+#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3u /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO (0x1u << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO (0x1u << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO (0x1u << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk (0x3u << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
+#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk (0x3u << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
+#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk (0xFu << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
+#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk (0xFu << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
+#define TCC_EVCTRL_MASK 0x0F0FF7FFu /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE 0x00000000 /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF (0x1u << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG (0x1u << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT (0x1u << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR (0x1u << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS (0x1u << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable FaultA Interrupt Enable */
+#define TCC_INTENCLR_FAULTA (0x1u << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable FaultB Interrupt Enable */
+#define TCC_INTENCLR_FAULTB (0x1u << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0 (0x1u << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1 (0x1u << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk (0xFu << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
+#define TCC_INTENCLR_MASK 0x000FF80Fu /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enabl */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE 0x00000000 /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF (0x1u << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG (0x1u << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT (0x1u << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR (0x1u << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS (0x1u << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable FaultA Interrupt Enable */
+#define TCC_INTENSET_FAULTA (0x1u << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable FaultB Interrupt Enable */
+#define TCC_INTENSET_FAULTB (0x1u << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0 (0x1u << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enabl */
+#define TCC_INTENSET_FAULT1 (0x1u << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk (0xFu << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
+#define TCC_INTENSET_MASK 0x000FF80Fu /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ uint32_t CNT:1; /*!< bit: 2 Counter */
+ uint32_t ERR:1; /*!< bit: 3 Error */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE 0x00000000 /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF (0x1u << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG (0x1u << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT (0x1u << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR (0x1u << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS (0x1u << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable FaultA */
+#define TCC_INTFLAG_FAULTA (0x1u << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable FaultB */
+#define TCC_INTFLAG_FAULTB (0x1u << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0 (0x1u << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1 (0x1u << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk (0xFu << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
+#define TCC_INTFLAG_MASK 0x000FF80Fu /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable FaultA Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable FaultB Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable FaultA State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable FaultB State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE 0x00000001 /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP (0x1u << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX (0x1u << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS (0x1u << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV (0x1u << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV (0x1u << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV (0x1u << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable FaultA Input */
+#define TCC_STATUS_FAULTAIN (0x1u << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable FaultB Input */
+#define TCC_STATUS_FAULTBIN (0x1u << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN (0x1u << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN (0x1u << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable FaultA State */
+#define TCC_STATUS_FAULTA (0x1u << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable FaultB State */
+#define TCC_STATUS_FAULTB (0x1u << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0 (0x1u << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1 (0x1u << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk (0xFu << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
+#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk (0xFu << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
+#define TCC_STATUS_MASK 0x0F0FFFEBu /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Count Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE 0x00000000 /**< \brief (TCC_COUNT reset_value) Count */
+
+#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Count Value */
+#define TCC_COUNT_COUNT_Msk (0xFFFFFFu << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
+#define TCC_COUNT_MASK 0x00FFFFFFu /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE 0x0000 /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk (0xFFu << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
+#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk (0xFFu << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
+#define TCC_PATT_MASK 0xFFFFu /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE 0x00000000 /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk (0x7u << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
+#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk (0x3u << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
+#define TCC_WAVE_RAMP_RAMP1_Val 0x0u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_RAMP_RAMP2A_Val 0x1u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_RAMP_RAMP2_Val 0x2u /**< \brief (TCC_WAVE) */
+#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN (0x1u << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk (0xFu << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
+#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk (0xFu << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
+#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk (0xFu << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
+#define TCC_WAVE_MASK 0x0F0F0FB7u /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE 0xFFFFFFFF /**< \brief (TCC_PER reset_value) Period */
+
+#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk (0xFFFFFFu << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
+#define TCC_PER_MASK 0x00FFFFFFu /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Compare and Capture value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE 0x00000000 /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Compare and Capture value */
+#define TCC_CC_CC_Msk (0xFFFFFFu << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
+#define TCC_CC_MASK 0x00FFFFFFu /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE 0x0000 /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk (0xFFu << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
+#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk (0xFFu << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
+#define TCC_PATTB_MASK 0xFFFFu /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE 0x00000000 /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk (0x7u << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
+#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7u /**< \brief (TCC_WAVEB) */
+#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk (0x3u << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
+#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB (0x1u << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk (0xFu << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
+#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk (0xFu << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
+#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk (0xFu << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
+#define TCC_WAVEB_MASK 0x0F0F0FB7u /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE 0xFFFFFFFF /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Value */
+#define TCC_PERB_PERB_Msk (0xFFFFFFu << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
+#define TCC_PERB_MASK 0x00FFFFFFu /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Compare and Capture buffer value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE 0x00000000 /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Compare and Capture buffer value */
+#define TCC_CCB_CCB_Msk (0xFFFFFFu << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
+#define TCC_CCB_MASK 0x00FFFFFFu /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable FaultA Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable FaultB Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Configuration */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h
new file mode 100755
index 0000000000000000000000000000000000000000..eadabadc7b604a6817cae7869ee313dbe861778e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h
@@ -0,0 +1,1767 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_COMPONENT_
+#define _SAMD21_USB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB 0x101
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE 0x00 /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST (0x1u << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE (0x1u << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY (0x1u << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE (0x1u << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_DEVICE_Val 0x0u /**< \brief (USB_CTRLA) Device Mode */
+#define USB_CTRLA_MODE_HOST_Val 0x1u /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK 0x87u /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE 0x00 /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST (0x1u << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE (0x1u << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK 0x03u /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE 0x0001 /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH (0x1u << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM (0x1u << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3u << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)))
+#define USB_DEVICE_CTRLB_SPDCONF_0_Val 0x0u /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_1_Val 0x1u /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_2_Val 0x2u /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define USB_DEVICE_CTRLB_SPDCONF_3_Val 0x3u /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_0 (USB_DEVICE_CTRLB_SPDCONF_0_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_1 (USB_DEVICE_CTRLB_SPDCONF_1_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_2 (USB_DEVICE_CTRLB_SPDCONF_2_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_3 (USB_DEVICE_CTRLB_SPDCONF_3_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY (0x1u << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ (0x1u << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK (0x1u << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT (0x1u << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2 (0x1u << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK (0x1u << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3u << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)))
+#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0u /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1u /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2u /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3u /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK 0x0FFFu /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE 0x0000 /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME (0x1u << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk (0x3u << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)))
+#define USB_HOST_CTRLB_SPDCONF_0_Val 0x0u /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheralis high-speed capable. */
+#define USB_HOST_CTRLB_SPDCONF_1_Val 0x1u /**< \brief (USB_HOST_CTRLB) reserved */
+#define USB_HOST_CTRLB_SPDCONF_2_Val 0x2u /**< \brief (USB_HOST_CTRLB) reserved */
+#define USB_HOST_CTRLB_SPDCONF_3_Val 0x3u /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Releveant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_0 (USB_HOST_CTRLB_SPDCONF_0_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_1 (USB_HOST_CTRLB_SPDCONF_1_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_2 (USB_HOST_CTRLB_SPDCONF_2_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_3 (USB_HOST_CTRLB_SPDCONF_3_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ (0x1u << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK (0x1u << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE (0x1u << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET (0x1u << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK (0x1u << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME (0x1u << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK 0x0F6Eu /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE 0x00 /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk (0x7Fu << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)))
+#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN (0x1u << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK 0xFFu /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE 0x00 /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk (0xFu << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)))
+#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE (0x1u << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK 0x8Fu /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE 0x40 /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (0x3u << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)))
+#define USB_DEVICE_STATUS_SPEED_0_Val 0x0u /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define USB_DEVICE_STATUS_SPEED_1_Val 0x1u /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define USB_DEVICE_STATUS_SPEED_2_Val 0x2u /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_0 (USB_DEVICE_STATUS_SPEED_0_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_1 (USB_DEVICE_STATUS_SPEED_1_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_2 (USB_DEVICE_STATUS_SPEED_2_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3u << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)))
+#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0u /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1u /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2u /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK 0xCCu /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE 0x00 /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk (0x3u << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)))
+#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (0x3u << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)))
+#define USB_HOST_STATUS_MASK 0xCCu /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE 0x01 /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Fu << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)))
+#define USB_FSMSTATUS_FSMSTATE_1_Val 0x1u /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define USB_FSMSTATUS_FSMSTATE_2_Val 0x2u /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define USB_FSMSTATUS_FSMSTATE_4_Val 0x4u /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define USB_FSMSTATUS_FSMSTATE_8_Val 0x8u /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define USB_FSMSTATUS_FSMSTATE_16_Val 0x10u /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_32_Val 0x20u /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_64_Val 0x40u /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_1 (USB_FSMSTATUS_FSMSTATE_1_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_2 (USB_FSMSTATUS_FSMSTATE_2_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_4 (USB_FSMSTATUS_FSMSTATE_4_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_8 (USB_FSMSTATUS_FSMSTATE_8_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_16 (USB_FSMSTATUS_FSMSTATE_16_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_32 (USB_FSMSTATUS_FSMSTATE_32_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_64 (USB_FSMSTATUS_FSMSTATE_64_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK 0x3Fu /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk (0x7u << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)))
+#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFu << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)))
+#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR (0x1u << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK 0xBFFFu /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE 0x0000 /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk (0x7u << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)))
+#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk (0x7FFu << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)))
+#define USB_HOST_FNUM_MASK 0x3FFFu /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE 0x00 /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFu << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)))
+#define USB_HOST_FLENHIGH_MASK 0xFFu /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (0x1u << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF (0x1u << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF (0x1u << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST (0x1u << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP (0x1u << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM (0x1u << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM (0x1u << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (0x1u << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (0x1u << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (0x1u << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK 0x03FFu /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE 0x0000 /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF (0x1u << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST (0x1u << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP (0x1u << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM (0x1u << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM (0x1u << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER (0x1u << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN (0x1u << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC (0x1u << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK 0x03FCu /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (0x1u << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF (0x1u << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF (0x1u << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST (0x1u << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP (0x1u << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM (0x1u << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM (0x1u << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (0x1u << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (0x1u << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (0x1u << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK 0x03FFu /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE 0x0000 /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF (0x1u << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST (0x1u << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP (0x1u << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM (0x1u << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM (0x1u << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER (0x1u << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN (0x1u << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC (0x1u << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK 0x03FCu /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND (0x1u << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF (0x1u << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF (0x1u << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST (0x1u << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP (0x1u << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM (0x1u << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM (0x1u << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER (0x1u << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET (0x1u << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP (0x1u << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK 0x03FFu /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE 0x0000 /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF (0x1u << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST (0x1u << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP (0x1u << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM (0x1u << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM (0x1u << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER (0x1u << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN (0x1u << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC (0x1u << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK 0x03FCu /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000 /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFu << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)))
+#define USB_DEVICE_EPINTSMRY_MASK 0x00FFu /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE 0x0000 /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFu << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)))
+#define USB_HOST_PINTSMRY_MASK 0x00FFu /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE 0x00000000 /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFu << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)))
+#define USB_DESCADD_MASK 0xFFFFFFFFu /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE 0x0000 /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk (0x1Fu << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)))
+#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk (0x1Fu << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)))
+#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk (0x7u << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)))
+#define USB_PADCAL_MASK 0x77DFu /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7u << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7u << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS (0x1u << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK 0xF7u /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE 0x00 /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk (0x3u << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)))
+#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK (0x1u << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk (0x7u << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)))
+#define USB_HOST_PCFG_MASK 0x3Fu /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE 0x00 /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFu << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)))
+#define USB_HOST_BINTERVAL_MASK 0xFFu /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1u << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1u << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1u << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3u << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1u << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1u << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7u /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00 /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL (0x1u << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK (0x1u << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (0x1u << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY (0x1u << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY (0x1u << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK 0xD5u /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1u << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1u << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (0x1u << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3u << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1u << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1u << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK 0xF7u /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE 0x00 /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL (0x1u << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK (0x1u << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (0x1u << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY (0x1u << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY (0x1u << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK 0xD5u /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1u << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN (0x1u << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK (0x1u << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3u << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY (0x1u << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY (0x1u << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK 0xF7u /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE 0x00 /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL (0x1u << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK (0x1u << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE (0x1u << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY (0x1u << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY (0x1u << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK 0xD5u /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3u << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3u << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP (0x1u << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3u << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)))
+#define USB_DEVICE_EPINTFLAG_MASK 0x7Fu /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE 0x00 /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3u << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL (0x1u << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR (0x1u << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP (0x1u << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL (0x1u << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK 0x3Fu /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3u << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3u << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (0x1u << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3u << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)))
+#define USB_DEVICE_EPINTENCLR_MASK 0x7Fu /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE 0x00 /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3u << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL (0x1u << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR (0x1u << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP (0x1u << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL (0x1u << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK 0x3Fu /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00 /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3u << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3u << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (0x1u << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3u << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)))
+#define USB_DEVICE_EPINTENSET_MASK 0x7Fu /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE 0x00 /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (0x3u << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL (0x1u << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR (0x1u << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP (0x1u << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL (0x1u << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK 0x3Fu /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFu << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)))
+#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFu /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFu << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)))
+#define USB_HOST_ADDR_MASK 0xFFFFFFFFu /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFu << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFu << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7u << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1u << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFu /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFu << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFu << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
+#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk (0x7u << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1u << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFu /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFu << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFu << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)))
+#define USB_DEVICE_EXTREG_MASK 0x7FFFu /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk (0xFu << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFu << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)))
+#define USB_HOST_EXTREG_MASK 0x7FFFu /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (0x1u << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1u << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK 0x03u /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR (0x1u << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (0x1u << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK 0x03u /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000 /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Fu << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFu << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFu << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)))
+#define USB_HOST_CTRL_PIPE_MASK 0xFF7Fu /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (0x1u << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (0x1u << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER (0x1u << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (0x1u << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (0x1u << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7u << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)))
+#define USB_HOST_STATUS_PIPE_MASK 0x00FFu /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ RoReg8 Reserved2[0x5];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ RoReg8 Reserved2[0x5];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_USB_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h
new file mode 100755
index 0000000000000000000000000000000000000000..a5a585835ad4a2db249e262080cb200a8e83b737
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h
@@ -0,0 +1,303 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_COMPONENT_
+#define _SAMD21_WDT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT 0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE 0x00 /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE (0x1u << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN (0x1u << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON (0x1u << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK 0x86u /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE 0xBB /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk (0xFu << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
+#define WDT_CONFIG_PER_0_Val 0x0u /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_PER_1_Val 0x1u /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_PER_2_Val 0x2u /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_PER_3_Val 0x3u /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_PER_4_Val 0x4u /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_PER_5_Val 0x5u /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_PER_6_Val 0x6u /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_PER_7_Val 0x7u /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_PER_8_Val 0x8u /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_PER_9_Val 0x9u /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_PER_10_Val 0xAu /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_PER_11_Val 0xBu /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_0 (WDT_CONFIG_PER_0_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1 (WDT_CONFIG_PER_1_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2 (WDT_CONFIG_PER_2_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_3 (WDT_CONFIG_PER_3_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4 (WDT_CONFIG_PER_4_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_5 (WDT_CONFIG_PER_5_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_6 (WDT_CONFIG_PER_6_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_7 (WDT_CONFIG_PER_7_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_9 (WDT_CONFIG_PER_9_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_10 (WDT_CONFIG_PER_10_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_11 (WDT_CONFIG_PER_11_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk (0xFu << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
+#define WDT_CONFIG_WINDOW_0_Val 0x0u /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_WINDOW_1_Val 0x1u /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_WINDOW_2_Val 0x2u /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_WINDOW_3_Val 0x3u /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_WINDOW_4_Val 0x4u /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_WINDOW_5_Val 0x5u /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_WINDOW_6_Val 0x6u /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_WINDOW_7_Val 0x7u /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_WINDOW_8_Val 0x8u /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_WINDOW_9_Val 0x9u /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_WINDOW_10_Val 0xAu /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_WINDOW_11_Val 0xBu /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_0 (WDT_CONFIG_WINDOW_0_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1 (WDT_CONFIG_WINDOW_1_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2 (WDT_CONFIG_WINDOW_2_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_3 (WDT_CONFIG_WINDOW_3_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4 (WDT_CONFIG_WINDOW_4_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_5 (WDT_CONFIG_WINDOW_5_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_6 (WDT_CONFIG_WINDOW_6_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_7 (WDT_CONFIG_WINDOW_7_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_9 (WDT_CONFIG_WINDOW_9_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_10 (WDT_CONFIG_WINDOW_10_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_11 (WDT_CONFIG_WINDOW_11_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK 0xFFu /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE 0x0B /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk (0xFu << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
+#define WDT_EWCTRL_EWOFFSET_0_Val 0x0u /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_1_Val 0x1u /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_2_Val 0x2u /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_3_Val 0x3u /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_4_Val 0x4u /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_5_Val 0x5u /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_6_Val 0x6u /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_7_Val 0x7u /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8_Val 0x8u /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_9_Val 0x9u /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_10_Val 0xAu /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_11_Val 0xBu /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_0 (WDT_EWCTRL_EWOFFSET_0_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1 (WDT_EWCTRL_EWOFFSET_1_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2 (WDT_EWCTRL_EWOFFSET_2_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_3 (WDT_EWCTRL_EWOFFSET_3_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4 (WDT_EWCTRL_EWOFFSET_4_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_5 (WDT_EWCTRL_EWOFFSET_5_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_6 (WDT_EWCTRL_EWOFFSET_6_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_7 (WDT_EWCTRL_EWOFFSET_7_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_9 (WDT_EWCTRL_EWOFFSET_9_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_10 (WDT_EWCTRL_EWOFFSET_10_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_11 (WDT_EWCTRL_EWOFFSET_11_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK 0x0Fu /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE 0x00 /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW (0x1u << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK 0x01u /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE 0x00 /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW (0x1u << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK 0x01u /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE 0x00 /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW (0x1u << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK 0x01u /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE 0x00 /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY (0x1u << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK 0x80u /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE 0x00 /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk (0xFFu << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
+#define WDT_CLEAR_CLEAR_KEY_Val 0xA5u /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK 0xFFu /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_WDT_COMPONENT_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h
new file mode 100755
index 0000000000000000000000000000000000000000..5beec63a6bd064fc06edae3c5dbfb9266750cbde
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_INSTANCE_
+#define _SAMD21_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */
+#else
+#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_CMP_NUM 2
+#define AC_GCLK_ID_ANA 32
+#define AC_GCLK_ID_DIG 31
+#define AC_NUM_CMP AC_CMP_NUM
+#define AC_PAIRS 1
+
+#endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h
new file mode 100755
index 0000000000000000000000000000000000000000..fedabae534f222372ee2addb010b8656cfb8ddf5
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_INSTANCE_
+#define _SAMD21_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */
+#else
+#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_DMAC_ID_RESRDY 39
+#define ADC_EXTCHANNEL_MSB 19
+#define ADC_GCLK_ID 30
+#define ADC_RESULT_BITS 16
+#define ADC_RESULT_MSB (ADC_RESULT_BITS-1)
+
+#endif /* _SAMD21_ADC_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h
new file mode 100755
index 0000000000000000000000000000000000000000..25c2a89d24100afb901184d17d3ddbb24eb56e63
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_INSTANCE_
+#define _SAMD21_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */
+#else
+#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_DMAC_ID_EMPTY 40
+#define DAC_GCLK_ID 33
+
+#endif /* _SAMD21_DAC_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h
new file mode 100755
index 0000000000000000000000000000000000000000..c82818d2e1b89d2dab107d53b0a796a8c9064747
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h
@@ -0,0 +1,107 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_INSTANCE_
+#define _SAMD21_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */
+#else
+#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_CH_BITS len(bin(DMAC_CH_NUM - 1))-2
+#define DMAC_CH_NUM 12
+#define DMAC_CLK_AHB_ID 5
+#define DMAC_EVIN_NUM 4
+#define DMAC_EVOUT_NUM 4
+#define DMAC_LVL_BITS len(bin(DMAC_LVL_NUM - 1))-2
+#define DMAC_LVL_NUM 4
+#define DMAC_TRIG_BITS len(bin(DMAC_TRIG_NUM - 1))-2
+#define DMAC_TRIG_NUM 45
+
+#endif /* _SAMD21_DMAC_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h
new file mode 100755
index 0000000000000000000000000000000000000000..62b115108e409b8b57f6973d7dcb95ba33d00608
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_INSTANCE_
+#define _SAMD21_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_HSB_ID 3
+
+#endif /* _SAMD21_DSU_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h
new file mode 100755
index 0000000000000000000000000000000000000000..7d6f253f463691451190a290b913c0ef27282790
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_INSTANCE_
+#define _SAMD21_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_CONFIG_NUM ((EIC_EXTINT_NUM+7)/8)
+#define EIC_GCLK_ID 5
+
+#endif /* _SAMD21_EIC_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h
new file mode 100755
index 0000000000000000000000000000000000000000..8f94c5f402a8b8ff0bfa2d7621424c8830e88bed
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h
@@ -0,0 +1,197 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_INSTANCE_
+#define _SAMD21_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS 12
+#define EVSYS_CHANNELS_BITS (len(bin(EVSYS_CHANNELS-1))-2)
+#define EVSYS_CHANNELS_MSB (EVSYS_CHANNELS-1)
+#define EVSYS_EXTEVT_NUM 0
+#define EVSYS_GCLK_ID_0 7
+#define EVSYS_GCLK_ID_1 8
+#define EVSYS_GCLK_ID_2 9
+#define EVSYS_GCLK_ID_3 10
+#define EVSYS_GCLK_ID_4 11
+#define EVSYS_GCLK_ID_5 12
+#define EVSYS_GCLK_ID_6 13
+#define EVSYS_GCLK_ID_7 14
+#define EVSYS_GCLK_ID_8 15
+#define EVSYS_GCLK_ID_9 16
+#define EVSYS_GCLK_ID_10 17
+#define EVSYS_GCLK_ID_11 18
+#define EVSYS_GCLK_ID_LSB 7
+#define EVSYS_GCLK_ID_MSB 18
+#define EVSYS_GCLK_ID_SIZE 12
+#define EVSYS_GENERATORS 73
+#define EVSYS_GENERATORS_BITS (len(bin(EVSYS_GENERATORS-1))-2)
+#define EVSYS_USERS 29
+#define EVSYS_USERS_BITS (len(bin(EVSYS_USERS-1))-2)
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0 1
+#define EVSYS_ID_GEN_RTC_CMP_1 2
+#define EVSYS_ID_GEN_RTC_OVF 3
+#define EVSYS_ID_GEN_RTC_PER_0 4
+#define EVSYS_ID_GEN_RTC_PER_1 5
+#define EVSYS_ID_GEN_RTC_PER_2 6
+#define EVSYS_ID_GEN_RTC_PER_3 7
+#define EVSYS_ID_GEN_RTC_PER_4 8
+#define EVSYS_ID_GEN_RTC_PER_5 9
+#define EVSYS_ID_GEN_RTC_PER_6 10
+#define EVSYS_ID_GEN_RTC_PER_7 11
+#define EVSYS_ID_GEN_EIC_EXTINT_0 12
+#define EVSYS_ID_GEN_EIC_EXTINT_1 13
+#define EVSYS_ID_GEN_EIC_EXTINT_2 14
+#define EVSYS_ID_GEN_EIC_EXTINT_3 15
+#define EVSYS_ID_GEN_EIC_EXTINT_4 16
+#define EVSYS_ID_GEN_EIC_EXTINT_5 17
+#define EVSYS_ID_GEN_EIC_EXTINT_6 18
+#define EVSYS_ID_GEN_EIC_EXTINT_7 19
+#define EVSYS_ID_GEN_EIC_EXTINT_8 20
+#define EVSYS_ID_GEN_EIC_EXTINT_9 21
+#define EVSYS_ID_GEN_EIC_EXTINT_10 22
+#define EVSYS_ID_GEN_EIC_EXTINT_11 23
+#define EVSYS_ID_GEN_EIC_EXTINT_12 24
+#define EVSYS_ID_GEN_EIC_EXTINT_13 25
+#define EVSYS_ID_GEN_EIC_EXTINT_14 26
+#define EVSYS_ID_GEN_EIC_EXTINT_15 27
+#define EVSYS_ID_GEN_EIC_EXTINT_16 28
+#define EVSYS_ID_GEN_EIC_EXTINT_17 29
+#define EVSYS_ID_GEN_DMAC_CH_0 30
+#define EVSYS_ID_GEN_DMAC_CH_1 31
+#define EVSYS_ID_GEN_DMAC_CH_2 32
+#define EVSYS_ID_GEN_DMAC_CH_3 33
+#define EVSYS_ID_GEN_TCC0_OVF 34
+#define EVSYS_ID_GEN_TCC0_TRG 35
+#define EVSYS_ID_GEN_TCC0_CNT 36
+#define EVSYS_ID_GEN_TCC0_MCX_0 37
+#define EVSYS_ID_GEN_TCC0_MCX_1 38
+#define EVSYS_ID_GEN_TCC0_MCX_2 39
+#define EVSYS_ID_GEN_TCC0_MCX_3 40
+#define EVSYS_ID_GEN_TCC1_OVF 41
+#define EVSYS_ID_GEN_TCC1_TRG 42
+#define EVSYS_ID_GEN_TCC1_CNT 43
+#define EVSYS_ID_GEN_TCC1_MCX_0 44
+#define EVSYS_ID_GEN_TCC1_MCX_1 45
+#define EVSYS_ID_GEN_TCC2_OVF 46
+#define EVSYS_ID_GEN_TCC2_TRG 47
+#define EVSYS_ID_GEN_TCC2_CNT 48
+#define EVSYS_ID_GEN_TCC2_MCX_0 49
+#define EVSYS_ID_GEN_TCC2_MCX_1 50
+#define EVSYS_ID_GEN_TC3_OVF 51
+#define EVSYS_ID_GEN_TC3_MCX_0 52
+#define EVSYS_ID_GEN_TC3_MCX_1 53
+#define EVSYS_ID_GEN_TC4_OVF 54
+#define EVSYS_ID_GEN_TC4_MCX_0 55
+#define EVSYS_ID_GEN_TC4_MCX_1 56
+#define EVSYS_ID_GEN_TC5_OVF 57
+#define EVSYS_ID_GEN_TC5_MCX_0 58
+#define EVSYS_ID_GEN_TC5_MCX_1 59
+#define EVSYS_ID_GEN_TC6_OVF 60
+#define EVSYS_ID_GEN_TC6_MCX_0 61
+#define EVSYS_ID_GEN_TC6_MCX_1 62
+#define EVSYS_ID_GEN_TC7_OVF 63
+#define EVSYS_ID_GEN_TC7_MCX_0 64
+#define EVSYS_ID_GEN_TC7_MCX_1 65
+#define EVSYS_ID_GEN_ADC_RESRDY 66
+#define EVSYS_ID_GEN_ADC_WINMON 67
+#define EVSYS_ID_GEN_AC_COMP_0 68
+#define EVSYS_ID_GEN_AC_COMP_1 69
+#define EVSYS_ID_GEN_AC_WIN_0 70
+#define EVSYS_ID_GEN_DAC_EMPTY 71
+#define EVSYS_ID_GEN_PTC_EOC 72
+#define EVSYS_ID_GEN_PTC_WCOMP 73
+
+// USERS
+#define EVSYS_ID_USER_DMAC_CH_0 0
+#define EVSYS_ID_USER_DMAC_CH_1 1
+#define EVSYS_ID_USER_DMAC_CH_2 2
+#define EVSYS_ID_USER_DMAC_CH_3 3
+#define EVSYS_ID_USER_TCC0_EV_0 4
+#define EVSYS_ID_USER_TCC0_EV_1 5
+#define EVSYS_ID_USER_TCC0_MC_0 6
+#define EVSYS_ID_USER_TCC0_MC_1 7
+#define EVSYS_ID_USER_TCC0_MC_2 8
+#define EVSYS_ID_USER_TCC0_MC_3 9
+#define EVSYS_ID_USER_TCC1_EV_0 10
+#define EVSYS_ID_USER_TCC1_EV_1 11
+#define EVSYS_ID_USER_TCC1_MC_0 12
+#define EVSYS_ID_USER_TCC1_MC_1 13
+#define EVSYS_ID_USER_TCC2_EV_0 14
+#define EVSYS_ID_USER_TCC2_EV_1 15
+#define EVSYS_ID_USER_TCC2_MC_0 16
+#define EVSYS_ID_USER_TCC2_MC_1 17
+#define EVSYS_ID_USER_TC3_EVU 18
+#define EVSYS_ID_USER_TC4_EVU 19
+#define EVSYS_ID_USER_TC5_EVU 20
+#define EVSYS_ID_USER_TC6_EVU 21
+#define EVSYS_ID_USER_TC7_EVU 22
+#define EVSYS_ID_USER_ADC_START 23
+#define EVSYS_ID_USER_ADC_SYNC 24
+#define EVSYS_ID_USER_AC_SOC_0 25
+#define EVSYS_ID_USER_AC_SOC_1 26
+#define EVSYS_ID_USER_DAC_START 27
+#define EVSYS_ID_USER_PTC_STCONV 28
+
+#endif /* _SAMD21_EVSYS_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h
new file mode 100755
index 0000000000000000000000000000000000000000..04869ef9d54e908981cc0ca352c82c03c5960c03
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_INSTANCE_
+#define _SAMD21_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#else
+#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS 16
+#define GCLK_GEN_NUM 9
+#define GCLK_GEN_NUM_MSB (GCLK_GEN_NUM-1)
+#define GCLK_GEN_SOURCE_NUM_MSB (GCLK_SOURCE_NUM-1)
+#define GCLK_NUM 37
+#define GCLK_SOURCE_DFLL48M 7
+#define GCLK_SOURCE_FDPLL 8
+#define GCLK_SOURCE_GCLKGEN1 2
+#define GCLK_SOURCE_GCLKIN 1
+#define GCLK_SOURCE_NUM 9
+#define GCLK_SOURCE_OSCULP32K 3
+#define GCLK_SOURCE_OSC8M 6
+#define GCLK_SOURCE_OSC32K 4
+#define GCLK_SOURCE_XOSC 0
+#define GCLK_SOURCE_XOSC32K 5
+
+#endif /* _SAMD21_GCLK_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h
new file mode 100755
index 0000000000000000000000000000000000000000..3c92cde046a800eb1bdd117a2979b53fa72b3c1e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_INSTANCE_
+#define _SAMD21_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */
+#else
+#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM 2
+#define I2S_DMAC_ID_RX_0 41
+#define I2S_DMAC_ID_RX_1 42
+#define I2S_DMAC_ID_RX_LSB 41
+#define I2S_DMAC_ID_RX_MSB 42
+#define I2S_DMAC_ID_RX_SIZE 2
+#define I2S_DMAC_ID_TX_0 43
+#define I2S_DMAC_ID_TX_1 44
+#define I2S_DMAC_ID_TX_LSB 43
+#define I2S_DMAC_ID_TX_MSB 44
+#define I2S_DMAC_ID_TX_SIZE 2
+#define I2S_GCLK_ID_0 35
+#define I2S_GCLK_ID_1 36
+#define I2S_GCLK_ID_LSB 35
+#define I2S_GCLK_ID_MSB 36
+#define I2S_GCLK_ID_SIZE 2
+#define I2S_MAX_SLOTS 8
+#define I2S_SER_NUM 2
+
+#endif /* _SAMD21_I2S_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h
new file mode 100755
index 0000000000000000000000000000000000000000..ba3afe8cd3b63c6f4966aafe80b8f0f17cad7d28
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief Instance description for MTB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_INSTANCE_
+#define _SAMD21_MTB_INSTANCE_
+
+/* ========== Register definition for MTB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */
+#else
+#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAMD21_MTB_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
new file mode 100755
index 0000000000000000000000000000000000000000..2e7861466344d699e8c131ccf4caed6a14bec772
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
@@ -0,0 +1,92 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_INSTANCE_
+#define _SAMD21_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00004000)
+#define NVMCTRL_AUX1_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00006000)
+#define NVMCTRL_AUX2_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00008000)
+#define NVMCTRL_AUX3_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x0000A000)
+#define NVMCTRL_CLK_AHB_ID 4
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE (NVMCTRL_PAGES*NVMCTRL_PAGE_SIZE)
+#define NVMCTRL_LOCKBIT_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00002000)
+#define NVMCTRL_PAGES 4096
+#define NVMCTRL_PAGE_HW (NVMCTRL_PAGE_SIZE/2)
+#define NVMCTRL_PAGE_SIZE (1<<NVMCTRL_PSZ_BITS)
+#define NVMCTRL_PAGE_W (NVMCTRL_PAGE_SIZE/4)
+#define NVMCTRL_PMSB 3
+#define NVMCTRL_PSZ_BITS 6
+#define NVMCTRL_ROW_PAGES 4
+#define NVMCTRL_ROW_SIZE (NVMCTRL_PAGE_SIZE*NVMCTRL_ROW_PAGES)
+#define NVMCTRL_TEMP_LOG_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00006030)
+#define NVMCTRL_USER_PAGE_ADDRESS (FLASH_ADDR + NVMCTRL_USER_PAGE_OFFSET)
+#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+
+#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h
new file mode 100755
index 0000000000000000000000000000000000000000..2eafeae7e6d70b136f3549e8eb9b28c38f61cbd9
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC0
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC0_INSTANCE_
+#define _SAMD21_PAC0_INSTANCE_
+
+/* ========== Register definition for PAC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#else
+#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC0 peripheral ========== */
+#define PAC0_WPROT_DEFAULT_VAL 0x00000000
+
+#endif /* _SAMD21_PAC0_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h
new file mode 100755
index 0000000000000000000000000000000000000000..2ad49e4bf91c9aa7a33e3bc411a03f4f038ce0e4
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC1
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC1_INSTANCE_
+#define _SAMD21_PAC1_INSTANCE_
+
+/* ========== Register definition for PAC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#else
+#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC1 peripheral ========== */
+#define PAC1_WPROT_DEFAULT_VAL 0x00000000
+
+#endif /* _SAMD21_PAC1_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h
new file mode 100755
index 0000000000000000000000000000000000000000..5a9cde7351c82f62b2374097f7f11ec77b786445
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC2
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC2_INSTANCE_
+#define _SAMD21_PAC2_INSTANCE_
+
+/* ========== Register definition for PAC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#else
+#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC2 peripheral ========== */
+#define PAC2_WPROT_DEFAULT_VAL 0x00800000
+
+#endif /* _SAMD21_PAC2_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h
new file mode 100755
index 0000000000000000000000000000000000000000..e8d992ac1e9454883c5553e1262205ca56783150
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_INSTANCE_
+#define _SAMD21_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */
+#else
+#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_CTRL_MCSEL_DFLL48M 3
+#define PM_CTRL_MCSEL_GCLK 0
+#define PM_CTRL_MCSEL_OSC8M 1
+#define PM_CTRL_MCSEL_XOSC 2
+#define PM_PM_CLK_APB_NUM 2
+
+#endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h
new file mode 100755
index 0000000000000000000000000000000000000000..d65cbbac0011ff8cc182b4a00eec89c1254a60f9
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS 84
+#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_DRVSTR 1
+#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_ODRAIN 0
+#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
+#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 }
+#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 }
+#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 }
+#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE }
+#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
+#define PORT_SLEWLIM 0
+#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h
new file mode 100755
index 0000000000000000000000000000000000000000..6815a328b5c63162c2fc43e605589112c28f2d86
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h
@@ -0,0 +1,117 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_INSTANCE_
+#define _SAMD21_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM 1
+#define RTC_COMP16_NUM 2
+#define RTC_COMP32_NUM RTC_ALARM_NUM
+#define RTC_GCLK_ID 4
+#define RTC_NUM_OF_ALARMS RTC_ALARM_NUM
+#define RTC_NUM_OF_COMP16 RTC_COMP16_NUM
+#define RTC_NUM_OF_COMP32 RTC_COMP32_NUM
+
+#endif /* _SAMD21_RTC_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h
new file mode 100755
index 0000000000000000000000000000000000000000..5062b37840c04b279f3c7712b5b4fdd0a42218b2
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM0_INSTANCE_
+#define _SAMD21_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
+#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
+#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
+#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
+#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
+#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
+#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
+#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
+#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_DMAC_ID_RX 1
+#define SERCOM0_DMAC_ID_TX 2
+#define SERCOM0_GCLK_ID_CORE 20
+#define SERCOM0_GCLK_ID_SLOW 19
+#define SERCOM0_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h
new file mode 100755
index 0000000000000000000000000000000000000000..d23b7cc08af129f3f51d323e65731a6be46ec2ae
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM1_INSTANCE_
+#define _SAMD21_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
+#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
+#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
+#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
+#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
+#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
+#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
+#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
+#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_DMAC_ID_RX 3
+#define SERCOM1_DMAC_ID_TX 4
+#define SERCOM1_GCLK_ID_CORE 21
+#define SERCOM1_GCLK_ID_SLOW 19
+#define SERCOM1_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h
new file mode 100755
index 0000000000000000000000000000000000000000..dccc6193461156064f716632af39f8a29b0067af
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM2_INSTANCE_
+#define _SAMD21_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
+#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
+#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
+#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
+#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
+#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
+#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
+#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
+#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_DMAC_ID_RX 5
+#define SERCOM2_DMAC_ID_TX 6
+#define SERCOM2_GCLK_ID_CORE 22
+#define SERCOM2_GCLK_ID_SLOW 19
+#define SERCOM2_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h
new file mode 100755
index 0000000000000000000000000000000000000000..d2c74a24424e71357ab8d1b14027e9cefa442b92
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM3_INSTANCE_
+#define _SAMD21_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
+#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
+#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
+#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
+#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
+#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
+#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
+#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
+#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_DMAC_ID_RX 7
+#define SERCOM3_DMAC_ID_TX 8
+#define SERCOM3_GCLK_ID_CORE 23
+#define SERCOM3_GCLK_ID_SLOW 19
+#define SERCOM3_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h
new file mode 100755
index 0000000000000000000000000000000000000000..a162f17b3b8f51416aa15e64590b12f240f86533
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM4_INSTANCE_
+#define _SAMD21_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
+#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
+#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
+#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
+#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
+#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
+#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
+#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
+#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_DMAC_ID_RX 9
+#define SERCOM4_DMAC_ID_TX 10
+#define SERCOM4_GCLK_ID_CORE 24
+#define SERCOM4_GCLK_ID_SLOW 19
+#define SERCOM4_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h
new file mode 100755
index 0000000000000000000000000000000000000000..0ec6826fd99e189f0e8d2910c12811647a767ae8
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom5.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM5_INSTANCE_
+#define _SAMD21_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
+#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
+#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
+#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
+#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
+#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
+#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
+#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
+#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_DMAC_ID_RX 11
+#define SERCOM5_DMAC_ID_TX 12
+#define SERCOM5_GCLK_ID_CORE 25
+#define SERCOM5_GCLK_ID_SLOW 19
+#define SERCOM5_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
new file mode 100755
index 0000000000000000000000000000000000000000..973689ad38761f3146a840c9477cfe214160a6e6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SYSCTRL
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_INSTANCE_
+#define _SAMD21_SYSCTRL_INSTANCE_
+
+/* ========== Register definition for SYSCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#else
+#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SYSCTRL peripheral ========== */
+#define SYSCTRL_BGAP_CALIB_MSB 11
+#define SYSCTRL_BOD33_CALIB_MSB 5
+#define SYSCTRL_DFLL48M_COARSE_MSB 5
+#define SYSCTRL_DFLL48M_FINE_MSB 9
+#define SYSCTRL_GCLK_ID_DFLL48 0
+#define SYSCTRL_GCLK_ID_FDPLL 1
+#define SYSCTRL_GCLK_ID_FDPLL32K 2
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB 1
+#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB 48
+#define SYSCTRL_VREF_STATUS_MSB 7
+#define SYSCTRL_VREG_LEVEL_MSB 2
+#define SYSCTRL_BOD12_VERSION 0x111
+#define SYSCTRL_BOD33_VERSION 0x111
+#define SYSCTRL_DFLL48M_VERSION 0x300
+#define SYSCTRL_FDPLL_VERSION 0x110
+#define SYSCTRL_OSCULP32K_VERSION 0x111
+#define SYSCTRL_OSC8M_VERSION 0x120
+#define SYSCTRL_OSC32K_VERSION 0x110
+#define SYSCTRL_VREF_VERSION 0x200
+#define SYSCTRL_VREG_VERSION 0x201
+#define SYSCTRL_XOSC_VERSION 0x111
+#define SYSCTRL_XOSC32K_VERSION 0x111
+
+#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h
new file mode 100755
index 0000000000000000000000000000000000000000..e93d2aa5ef27800ea635df056c0a5f7cb3adf43d
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc3.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC3_INSTANCE_
+#define _SAMD21_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC8_NUM 2
+#define TC3_CC16_NUM 2
+#define TC3_CC32_NUM 2
+#define TC3_DITHERING_EXT 0
+#define TC3_DMAC_ID_MC_0 25
+#define TC3_DMAC_ID_MC_1 26
+#define TC3_DMAC_ID_MC_LSB 25
+#define TC3_DMAC_ID_MC_MSB 26
+#define TC3_DMAC_ID_MC_SIZE 2
+#define TC3_DMAC_ID_OVF 24
+#define TC3_GCLK_ID 27
+#define TC3_MASTER 0
+#define TC3_OW_NUM 2
+#define TC3_PERIOD_EXT 0
+#define TC3_SHADOW_EXT 0
+
+#endif /* _SAMD21_TC3_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h
new file mode 100755
index 0000000000000000000000000000000000000000..7c44fe3f1823ca8b44ea214529a84486ba7cbed8
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc4.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC4_INSTANCE_
+#define _SAMD21_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC8_NUM 2
+#define TC4_CC16_NUM 2
+#define TC4_CC32_NUM 2
+#define TC4_DITHERING_EXT 0
+#define TC4_DMAC_ID_MC_0 28
+#define TC4_DMAC_ID_MC_1 29
+#define TC4_DMAC_ID_MC_LSB 28
+#define TC4_DMAC_ID_MC_MSB 29
+#define TC4_DMAC_ID_MC_SIZE 2
+#define TC4_DMAC_ID_OVF 27
+#define TC4_GCLK_ID 28
+#define TC4_MASTER 1
+#define TC4_OW_NUM 2
+#define TC4_PERIOD_EXT 0
+#define TC4_SHADOW_EXT 0
+
+#endif /* _SAMD21_TC4_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h
new file mode 100755
index 0000000000000000000000000000000000000000..8531688e887c95ebb446750f61f602b31c265fa0
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc5.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC5_INSTANCE_
+#define _SAMD21_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC8_NUM 2
+#define TC5_CC16_NUM 2
+#define TC5_CC32_NUM 2
+#define TC5_DITHERING_EXT 0
+#define TC5_DMAC_ID_MC_0 31
+#define TC5_DMAC_ID_MC_1 32
+#define TC5_DMAC_ID_MC_LSB 31
+#define TC5_DMAC_ID_MC_MSB 32
+#define TC5_DMAC_ID_MC_SIZE 2
+#define TC5_DMAC_ID_OVF 30
+#define TC5_GCLK_ID 28
+#define TC5_MASTER 0
+#define TC5_OW_NUM 2
+#define TC5_PERIOD_EXT 0
+#define TC5_SHADOW_EXT 0
+
+#endif /* _SAMD21_TC5_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h
new file mode 100755
index 0000000000000000000000000000000000000000..40015bc3f3c44467f0d07a661b6c56de3cfc747b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc6.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC6_INSTANCE_
+#define _SAMD21_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC8_NUM 2
+#define TC6_CC16_NUM 2
+#define TC6_CC32_NUM 2
+#define TC6_DITHERING_EXT 0
+#define TC6_DMAC_ID_MC_0 34
+#define TC6_DMAC_ID_MC_1 35
+#define TC6_DMAC_ID_MC_LSB 34
+#define TC6_DMAC_ID_MC_MSB 35
+#define TC6_DMAC_ID_MC_SIZE 2
+#define TC6_DMAC_ID_OVF 33
+#define TC6_GCLK_ID 29
+#define TC6_MASTER 1
+#define TC6_OW_NUM 2
+#define TC6_PERIOD_EXT 0
+#define TC6_SHADOW_EXT 0
+
+#endif /* _SAMD21_TC6_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h
new file mode 100755
index 0000000000000000000000000000000000000000..ee2f765dcc49ce397a52fe494f0d7cf34659de0b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tc7.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC7_INSTANCE_
+#define _SAMD21_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC8_NUM 2
+#define TC7_CC16_NUM 2
+#define TC7_CC32_NUM 2
+#define TC7_DITHERING_EXT 0
+#define TC7_DMAC_ID_MC_0 37
+#define TC7_DMAC_ID_MC_1 38
+#define TC7_DMAC_ID_MC_LSB 37
+#define TC7_DMAC_ID_MC_MSB 38
+#define TC7_DMAC_ID_MC_SIZE 2
+#define TC7_DMAC_ID_OVF 36
+#define TC7_GCLK_ID 29
+#define TC7_MASTER 0
+#define TC7_OW_NUM 2
+#define TC7_PERIOD_EXT 0
+#define TC7_SHADOW_EXT 0
+
+#endif /* _SAMD21_TC7_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h
new file mode 100755
index 0000000000000000000000000000000000000000..a337a5e312a4d4f926054d1356e5575896e9ef30
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc0.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC0_INSTANCE_
+#define _SAMD21_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable FaultA Configuration */
+#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable FaultB Configuration */
+#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Configuration */
+#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable FaultA Configuration */
+#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable FaultB Configuration */
+#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Configuration */
+#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM 4
+#define TCC0_DITHERING 1
+#define TCC0_DMAC_ID_MC_0 14
+#define TCC0_DMAC_ID_MC_1 15
+#define TCC0_DMAC_ID_MC_2 16
+#define TCC0_DMAC_ID_MC_3 17
+#define TCC0_DMAC_ID_MC_LSB 14
+#define TCC0_DMAC_ID_MC_MSB 17
+#define TCC0_DMAC_ID_MC_SIZE 4
+#define TCC0_DMAC_ID_OVF 13
+#define TCC0_DTI 1
+#define TCC0_EXT (TCC0_DITHERING*16+TCC0_PG*8+TCC0_SWAP*4+TCC0_DTI*2+TCC0_OTMX*1)
+#define TCC0_GCLK_ID 26
+#define TCC0_MASTER 0
+#define TCC0_OTMX 1
+#define TCC0_OW_NUM 8
+#define TCC0_PG 1
+#define TCC0_SIZE 24
+#define TCC0_SWAP 1
+
+#endif /* _SAMD21_TCC0_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h
new file mode 100755
index 0000000000000000000000000000000000000000..60a9974eb4418130f15de9344f7f24d8de527768
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc1.h
@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC1_INSTANCE_
+#define _SAMD21_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable FaultA Configuration */
+#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable FaultB Configuration */
+#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Configuration */
+#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable FaultA Configuration */
+#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable FaultB Configuration */
+#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Configuration */
+#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM 2
+#define TCC1_DITHERING 1
+#define TCC1_DMAC_ID_MC_0 19
+#define TCC1_DMAC_ID_MC_1 20
+#define TCC1_DMAC_ID_MC_LSB 19
+#define TCC1_DMAC_ID_MC_MSB 20
+#define TCC1_DMAC_ID_MC_SIZE 2
+#define TCC1_DMAC_ID_OVF 18
+#define TCC1_DTI 0
+#define TCC1_EXT (TCC1_DITHERING*16+TCC1_PG*8+TCC1_SWAP*4+TCC1_DTI*2+TCC1_OTMX*1)
+#define TCC1_GCLK_ID 26
+#define TCC1_MASTER 1
+#define TCC1_OTMX 0
+#define TCC1_OW_NUM 4
+#define TCC1_PG 1
+#define TCC1_SIZE 24
+#define TCC1_SWAP 0
+
+#endif /* _SAMD21_TCC1_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h
new file mode 100755
index 0000000000000000000000000000000000000000..4141fa28cb1087355d791086a08c470de251480d
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/tcc2.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC2_INSTANCE_
+#define _SAMD21_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable FaultA Configuration */
+#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable FaultB Configuration */
+#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Configuration */
+#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable FaultA Configuration */
+#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable FaultB Configuration */
+#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Configuration */
+#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM 2
+#define TCC2_DITHERING 0
+#define TCC2_DMAC_ID_MC_0 22
+#define TCC2_DMAC_ID_MC_1 23
+#define TCC2_DMAC_ID_MC_LSB 22
+#define TCC2_DMAC_ID_MC_MSB 23
+#define TCC2_DMAC_ID_MC_SIZE 2
+#define TCC2_DMAC_ID_OVF 21
+#define TCC2_DTI 0
+#define TCC2_EXT (TCC2_DITHERING*16+TCC2_PG*8+TCC2_SWAP*4+TCC2_DTI*2+TCC2_OTMX*1)
+#define TCC2_GCLK_ID 27
+#define TCC2_MASTER 0
+#define TCC2_OTMX 0
+#define TCC2_OW_NUM 2
+#define TCC2_PG 0
+#define TCC2_SIZE 16
+#define TCC2_SWAP 0
+
+#endif /* _SAMD21_TCC2_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h
new file mode 100755
index 0000000000000000000000000000000000000000..e926d3cc52e0eb2d88d74831309054772da4a2ad
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/usb.h
@@ -0,0 +1,342 @@
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_INSTANCE_
+#define _SAMD21_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_EPT_NBR USB_EPT_NUM
+#define USB_EPT_NUM 8
+#define USB_GCLK_ID 6
+#define USB_PIPE_NUM 8
+
+#endif /* _SAMD21_USB_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h
new file mode 100755
index 0000000000000000000000000000000000000000..fd07c29fcfb3bd760d29749dbeac673bab2f4351
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/instance/wdt.h
@@ -0,0 +1,71 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_INSTANCE_
+#define _SAMD21_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for WDT peripheral ========== */
+#define WDT_GCLK_ID 3
+
+#endif /* _SAMD21_WDT_INSTANCE_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
new file mode 100755
index 0000000000000000000000000000000000000000..6d6f84dec8a36068628ea5726d487762919d03a0
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e15a.h
@@ -0,0 +1,670 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_PIO_
+#define _SAMD21E15A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21E15A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
new file mode 100755
index 0000000000000000000000000000000000000000..e2de358af688fbd422a7da59f79fb7fad331b34a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h
@@ -0,0 +1,670 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_PIO_
+#define _SAMD21E16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21E16A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
new file mode 100755
index 0000000000000000000000000000000000000000..550f4b48cde03fcb1cc5e2340ec56edd23b98393
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h
@@ -0,0 +1,670 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_PIO_
+#define _SAMD21E17A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21E17A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
new file mode 100755
index 0000000000000000000000000000000000000000..72926dd35be592d7cc846178009221032eaea77a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h
@@ -0,0 +1,670 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_PIO_
+#define _SAMD21E18A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21E18A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
new file mode 100755
index 0000000000000000000000000000000000000000..349d2e18bd59839efc2b216acbecee4c9efc292a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h
@@ -0,0 +1,952 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_PIO_
+#define _SAMD21G15A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21G15A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
new file mode 100755
index 0000000000000000000000000000000000000000..9a8f06ce04db02a4dd105a9bbec34ee72b530ca4
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h
@@ -0,0 +1,952 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_PIO_
+#define _SAMD21G16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21G16A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
new file mode 100755
index 0000000000000000000000000000000000000000..5ebf7a30fde162908053cf49ff502d128eb7a305
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h
@@ -0,0 +1,952 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_PIO_
+#define _SAMD21G17A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21G17A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
new file mode 100755
index 0000000000000000000000000000000000000000..e54aefe32161c1affd98d3a876a409f66dc4c1c2
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h
@@ -0,0 +1,952 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_PIO_
+#define _SAMD21G18A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+
+#endif /* _SAMD21G18A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
new file mode 100755
index 0000000000000000000000000000000000000000..97e632f380010fdcce96e36ee596e59f8a5defdf
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h
@@ -0,0 +1,1242 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_PIO_
+#define _SAMD21J15A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1u << 14)
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1u << 15)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1u << 16)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1u << 12)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1u << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB31F_SERCOM4_PAD1 63 /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */
+#define MUX_PB31F_SERCOM4_PAD1 5
+#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1)
+#define PORT_PB31F_SERCOM4_PAD1 (1u << 31)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB30F_SERCOM4_PAD2 62 /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
+#define MUX_PB30F_SERCOM4_PAD2 5
+#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
+#define PORT_PB30F_SERCOM4_PAD2 (1u << 30)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)
+#define PIN_PB17C_SERCOM5_PAD0 49 /**< \brief SERCOM5 signal: PAD0 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD0 2
+#define PINMUX_PB17C_SERCOM5_PAD0 ((PIN_PB17C_SERCOM5_PAD0 << 16) | MUX_PB17C_SERCOM5_PAD0)
+#define PORT_PB17C_SERCOM5_PAD0 (1u << 17)
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)
+#define PIN_PB16C_SERCOM5_PAD1 48 /**< \brief SERCOM5 signal: PAD1 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD1 2
+#define PINMUX_PB16C_SERCOM5_PAD1 ((PIN_PB16C_SERCOM5_PAD1 << 16) | MUX_PB16C_SERCOM5_PAD1)
+#define PORT_PB16C_SERCOM5_PAD1 (1u << 16)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PB30E_TCC0_WO0 62 /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1u << 30)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PB31E_TCC0_WO1 63 /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1u << 31)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PB16F_TCC0_WO4 48 /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1u << 16)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PB17F_TCC0_WO5 49 /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1u << 17)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PB12F_TCC0_WO6 44 /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1u << 12)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PB13F_TCC0_WO7 45 /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1u << 13)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PB30F_TCC1_WO2 62 /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1u << 30)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+#define PIN_PB31F_TCC1_WO3 63 /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1u << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1u << 12)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1u << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1u << 14)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1u << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1u << 2)
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1u << 16)
+#define PIN_PB03E_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1u << 3)
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1u << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1u << 20)
+#define PIN_PB00E_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1u << 0)
+#define PIN_PB22E_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1u << 22)
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1u << 21)
+#define PIN_PB01E_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1u << 1)
+#define PIN_PB23E_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1u << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1u << 0)
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1u << 1)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1u << 4)
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1u << 5)
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1u << 6)
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PB12G_I2S_FS1 44 /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1u << 12)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB17G_I2S_MCK0 49 /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1u << 17)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+#define PIN_PB16G_I2S_SD1 48 /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1u << 16)
+
+#endif /* _SAMD21J15A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
new file mode 100755
index 0000000000000000000000000000000000000000..4a4ad446a01994b044974c4bb098036344aa5d70
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h
@@ -0,0 +1,1242 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_PIO_
+#define _SAMD21J16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1u << 14)
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1u << 15)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1u << 16)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1u << 12)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1u << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB31F_SERCOM4_PAD1 63 /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */
+#define MUX_PB31F_SERCOM4_PAD1 5
+#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1)
+#define PORT_PB31F_SERCOM4_PAD1 (1u << 31)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB30F_SERCOM4_PAD2 62 /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
+#define MUX_PB30F_SERCOM4_PAD2 5
+#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
+#define PORT_PB30F_SERCOM4_PAD2 (1u << 30)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)
+#define PIN_PB17C_SERCOM5_PAD0 49 /**< \brief SERCOM5 signal: PAD0 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD0 2
+#define PINMUX_PB17C_SERCOM5_PAD0 ((PIN_PB17C_SERCOM5_PAD0 << 16) | MUX_PB17C_SERCOM5_PAD0)
+#define PORT_PB17C_SERCOM5_PAD0 (1u << 17)
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)
+#define PIN_PB16C_SERCOM5_PAD1 48 /**< \brief SERCOM5 signal: PAD1 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD1 2
+#define PINMUX_PB16C_SERCOM5_PAD1 ((PIN_PB16C_SERCOM5_PAD1 << 16) | MUX_PB16C_SERCOM5_PAD1)
+#define PORT_PB16C_SERCOM5_PAD1 (1u << 16)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PB30E_TCC0_WO0 62 /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1u << 30)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PB31E_TCC0_WO1 63 /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1u << 31)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PB16F_TCC0_WO4 48 /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1u << 16)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PB17F_TCC0_WO5 49 /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1u << 17)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PB12F_TCC0_WO6 44 /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1u << 12)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PB13F_TCC0_WO7 45 /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1u << 13)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PB30F_TCC1_WO2 62 /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1u << 30)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+#define PIN_PB31F_TCC1_WO3 63 /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1u << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1u << 12)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1u << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1u << 14)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1u << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1u << 2)
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1u << 16)
+#define PIN_PB03E_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1u << 3)
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1u << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1u << 20)
+#define PIN_PB00E_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1u << 0)
+#define PIN_PB22E_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1u << 22)
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1u << 21)
+#define PIN_PB01E_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1u << 1)
+#define PIN_PB23E_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1u << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1u << 0)
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1u << 1)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1u << 4)
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1u << 5)
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1u << 6)
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PB12G_I2S_FS1 44 /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1u << 12)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB17G_I2S_MCK0 49 /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1u << 17)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+#define PIN_PB16G_I2S_SD1 48 /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1u << 16)
+
+#endif /* _SAMD21J16A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
new file mode 100755
index 0000000000000000000000000000000000000000..af55498aad7c77511afb0859d39d51cf2b382ba6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h
@@ -0,0 +1,1242 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J17A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_PIO_
+#define _SAMD21J17A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1u << 14)
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1u << 15)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1u << 16)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1u << 12)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1u << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB31F_SERCOM4_PAD1 63 /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */
+#define MUX_PB31F_SERCOM4_PAD1 5
+#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1)
+#define PORT_PB31F_SERCOM4_PAD1 (1u << 31)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB30F_SERCOM4_PAD2 62 /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
+#define MUX_PB30F_SERCOM4_PAD2 5
+#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
+#define PORT_PB30F_SERCOM4_PAD2 (1u << 30)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)
+#define PIN_PB17C_SERCOM5_PAD0 49 /**< \brief SERCOM5 signal: PAD0 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD0 2
+#define PINMUX_PB17C_SERCOM5_PAD0 ((PIN_PB17C_SERCOM5_PAD0 << 16) | MUX_PB17C_SERCOM5_PAD0)
+#define PORT_PB17C_SERCOM5_PAD0 (1u << 17)
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)
+#define PIN_PB16C_SERCOM5_PAD1 48 /**< \brief SERCOM5 signal: PAD1 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD1 2
+#define PINMUX_PB16C_SERCOM5_PAD1 ((PIN_PB16C_SERCOM5_PAD1 << 16) | MUX_PB16C_SERCOM5_PAD1)
+#define PORT_PB16C_SERCOM5_PAD1 (1u << 16)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PB30E_TCC0_WO0 62 /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1u << 30)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PB31E_TCC0_WO1 63 /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1u << 31)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PB16F_TCC0_WO4 48 /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1u << 16)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PB17F_TCC0_WO5 49 /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1u << 17)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PB12F_TCC0_WO6 44 /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1u << 12)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PB13F_TCC0_WO7 45 /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1u << 13)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PB30F_TCC1_WO2 62 /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1u << 30)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+#define PIN_PB31F_TCC1_WO3 63 /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1u << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1u << 12)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1u << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1u << 14)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1u << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1u << 2)
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1u << 16)
+#define PIN_PB03E_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1u << 3)
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1u << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1u << 20)
+#define PIN_PB00E_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1u << 0)
+#define PIN_PB22E_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1u << 22)
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1u << 21)
+#define PIN_PB01E_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1u << 1)
+#define PIN_PB23E_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1u << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1u << 0)
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1u << 1)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1u << 4)
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1u << 5)
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1u << 6)
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PB12G_I2S_FS1 44 /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1u << 12)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB17G_I2S_MCK0 49 /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1u << 17)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+#define PIN_PB16G_I2S_SD1 48 /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1u << 16)
+
+#endif /* _SAMD21J17A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
new file mode 100755
index 0000000000000000000000000000000000000000..a80d78752aa3c45f1735be14c45ddff47ae69319
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h
@@ -0,0 +1,1242 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_PIO_
+#define _SAMD21J18A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1u << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1u << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1u << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1u << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1u << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1u << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1u << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1u << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1u << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1u << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1u << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1u << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1u << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1u << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for CORE peripheral ========== */
+#define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
+#define MUX_PA30G_CORE_SWCLK 6
+#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
+#define PORT_PA30G_CORE_SWCLK (1u << 30)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46 /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1u << 14)
+#define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1u << 22)
+#define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1u << 14)
+#define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1u << 27)
+#define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1u << 28)
+#define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1u << 30)
+#define PIN_PB15H_GCLK_IO1 47 /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1u << 15)
+#define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1u << 23)
+#define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1u << 15)
+#define PIN_PB16H_GCLK_IO2 48 /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1u << 16)
+#define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1u << 16)
+#define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1u << 17)
+#define PIN_PB17H_GCLK_IO3 49 /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1u << 17)
+#define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1u << 10)
+#define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1u << 20)
+#define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1u << 10)
+#define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1u << 11)
+#define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1u << 21)
+#define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1u << 11)
+#define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1u << 22)
+#define PIN_PB12H_GCLK_IO6 44 /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1u << 12)
+#define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1u << 23)
+#define PIN_PB13H_GCLK_IO7 45 /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1u << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PB00A_EIC_EXTINT0 32 /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PB16A_EIC_EXTINT0 48 /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1u << 16)
+#define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1u << 0)
+#define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PB01A_EIC_EXTINT1 33 /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PB17A_EIC_EXTINT1 49 /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1u << 17)
+#define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1u << 1)
+#define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1u << 18)
+#define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1u << 2)
+#define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1u << 19)
+#define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1u << 3)
+#define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1u << 20)
+#define PIN_PB04A_EIC_EXTINT4 36 /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1u << 4)
+#define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1u << 21)
+#define PIN_PB05A_EIC_EXTINT5 37 /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1u << 5)
+#define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PB06A_EIC_EXTINT6 38 /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1u << 6)
+#define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1u << 22)
+#define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PB07A_EIC_EXTINT7 39 /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1u << 7)
+#define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1u << 23)
+#define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1u << 28)
+#define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1u << 8)
+#define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1u << 9)
+#define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1u << 30)
+#define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1u << 10)
+#define PIN_PA18A_EIC_EXTINT10 18 /**< \brief EIC signal: EXTINT10 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT10 0
+#define PINMUX_PA18A_EIC_EXTINT10 ((PIN_PA18A_EIC_EXTINT10 << 16) | MUX_PA18A_EIC_EXTINT10)
+#define PORT_PA18A_EIC_EXTINT10 (1u << 18)
+#define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1u << 31)
+#define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1u << 11)
+#define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1u << 24)
+#define PIN_PB12A_EIC_EXTINT12 44 /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1u << 12)
+#define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1u << 25)
+#define PIN_PB13A_EIC_EXTINT13 45 /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1u << 13)
+#define PIN_PB14A_EIC_EXTINT14 46 /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PB30A_EIC_EXTINT14 62 /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1u << 30)
+#define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1u << 14)
+#define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1u << 27)
+#define PIN_PB15A_EIC_EXTINT15 47 /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1u << 15)
+#define PIN_PB31A_EIC_EXTINT15 63 /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1u << 31)
+#define PIN_PA12A_EIC_EXTINT17 12 /**< \brief EIC signal: EXTINT17 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT17 0
+#define PINMUX_PA12A_EIC_EXTINT17 ((PIN_PA12A_EIC_EXTINT17 << 16) | MUX_PA12A_EIC_EXTINT17)
+#define PORT_PA12A_EIC_EXTINT17 (1u << 12)
+#define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1u << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24 /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1u << 24)
+#define PIN_PA25G_USB_DP 25 /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1u << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23 /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1u << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
+#define PIN_PA13A_SERCOM0_PAD0 13 /**< \brief SERCOM0 signal: PAD0 on PA13 mux A */
+#define MUX_PA13A_SERCOM0_PAD0 0
+#define PINMUX_PA13A_SERCOM0_PAD0 ((PIN_PA13A_SERCOM0_PAD0 << 16) | MUX_PA13A_SERCOM0_PAD0)
+#define PORT_PA13A_SERCOM0_PAD0 (1u << 13)
+#define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
+#define PIN_PA15A_SERCOM2_PAD0 15 /**< \brief SERCOM2 signal: PAD0 on PA15 mux A */
+#define MUX_PA15A_SERCOM2_PAD0 0
+#define PINMUX_PA15A_SERCOM2_PAD0 ((PIN_PA15A_SERCOM2_PAD0 << 16) | MUX_PA15A_SERCOM2_PAD0)
+#define PORT_PA15A_SERCOM2_PAD0 (1u << 15)
+#define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
+#define PIN_PA27F_SERCOM3_PAD0 27 /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */
+#define MUX_PA27F_SERCOM3_PAD0 5
+#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0)
+#define PORT_PA27F_SERCOM3_PAD0 (1u << 27)
+#define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
+#define PIN_PA28F_SERCOM3_PAD1 28 /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */
+#define MUX_PA28F_SERCOM3_PAD1 5
+#define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1)
+#define PORT_PA28F_SERCOM3_PAD1 (1u << 28)
+#define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44 /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1u << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45 /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1u << 13)
+#define PIN_PB31F_SERCOM4_PAD1 63 /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */
+#define MUX_PB31F_SERCOM4_PAD1 5
+#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1)
+#define PORT_PB31F_SERCOM4_PAD1 (1u << 31)
+#define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46 /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1u << 14)
+#define PIN_PB30F_SERCOM4_PAD2 62 /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */
+#define MUX_PB30F_SERCOM4_PAD2 5
+#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2)
+#define PORT_PB30F_SERCOM4_PAD2 (1u << 30)
+#define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47 /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1u << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48 /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1u << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62 /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1u << 30)
+#define PIN_PB17C_SERCOM5_PAD0 49 /**< \brief SERCOM5 signal: PAD0 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD0 2
+#define PINMUX_PB17C_SERCOM5_PAD0 ((PIN_PB17C_SERCOM5_PAD0 << 16) | MUX_PB17C_SERCOM5_PAD0)
+#define PORT_PB17C_SERCOM5_PAD0 (1u << 17)
+#define PIN_PB17C_SERCOM5_PAD1 49 /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1u << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63 /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1u << 31)
+#define PIN_PB16C_SERCOM5_PAD1 48 /**< \brief SERCOM5 signal: PAD1 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD1 2
+#define PINMUX_PB16C_SERCOM5_PAD1 ((PIN_PB16C_SERCOM5_PAD1 << 16) | MUX_PB16C_SERCOM5_PAD1)
+#define PORT_PB16C_SERCOM5_PAD1 (1u << 16)
+#define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32 /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1u << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33 /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1u << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4 /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1u << 4)
+#define PIN_PA08E_TCC0_WO0 8 /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1u << 8)
+#define PIN_PB30E_TCC0_WO0 62 /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1u << 30)
+#define PIN_PA16F_TCC0_WO0 16 /**< \brief TCC0 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO0 5
+#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0)
+#define PORT_PA16F_TCC0_WO0 (1u << 16)
+#define PIN_PA05E_TCC0_WO1 5 /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1u << 5)
+#define PIN_PA09E_TCC0_WO1 9 /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1u << 9)
+#define PIN_PB31E_TCC0_WO1 63 /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1u << 31)
+#define PIN_PA17F_TCC0_WO1 17 /**< \brief TCC0 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO1 5
+#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1)
+#define PORT_PA17F_TCC0_WO1 (1u << 17)
+#define PIN_PA10F_TCC0_WO2 10 /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1u << 10)
+#define PIN_PA18F_TCC0_WO2 18 /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1u << 18)
+#define PIN_PA11F_TCC0_WO3 11 /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1u << 11)
+#define PIN_PA19F_TCC0_WO3 19 /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1u << 19)
+#define PIN_PA14F_TCC0_WO4 14 /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1u << 14)
+#define PIN_PA22F_TCC0_WO4 22 /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1u << 22)
+#define PIN_PB10F_TCC0_WO4 42 /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1u << 10)
+#define PIN_PB16F_TCC0_WO4 48 /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1u << 16)
+#define PIN_PA15F_TCC0_WO5 15 /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1u << 15)
+#define PIN_PA23F_TCC0_WO5 23 /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1u << 23)
+#define PIN_PB11F_TCC0_WO5 43 /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1u << 11)
+#define PIN_PB17F_TCC0_WO5 49 /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1u << 17)
+#define PIN_PA12F_TCC0_WO6 12 /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1u << 12)
+#define PIN_PA20F_TCC0_WO6 20 /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1u << 20)
+#define PIN_PB12F_TCC0_WO6 44 /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1u << 12)
+#define PIN_PA16F_TCC0_WO6 16 /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1u << 16)
+#define PIN_PA13F_TCC0_WO7 13 /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1u << 13)
+#define PIN_PA21F_TCC0_WO7 21 /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1u << 21)
+#define PIN_PB13F_TCC0_WO7 45 /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1u << 13)
+#define PIN_PA17F_TCC0_WO7 17 /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1u << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6 /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1u << 6)
+#define PIN_PA10E_TCC1_WO0 10 /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1u << 10)
+#define PIN_PA30E_TCC1_WO0 30 /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1u << 30)
+#define PIN_PA07E_TCC1_WO1 7 /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1u << 7)
+#define PIN_PA11E_TCC1_WO1 11 /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1u << 11)
+#define PIN_PA31E_TCC1_WO1 31 /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1u << 31)
+#define PIN_PA08F_TCC1_WO2 8 /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1u << 8)
+#define PIN_PA24F_TCC1_WO2 24 /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1u << 24)
+#define PIN_PB30F_TCC1_WO2 62 /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1u << 30)
+#define PIN_PA09F_TCC1_WO3 9 /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1u << 9)
+#define PIN_PA25F_TCC1_WO3 25 /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1u << 25)
+#define PIN_PB31F_TCC1_WO3 63 /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1u << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12 /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1u << 12)
+#define PIN_PA16E_TCC2_WO0 16 /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1u << 16)
+#define PIN_PA00E_TCC2_WO0 0 /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1u << 0)
+#define PIN_PA13E_TCC2_WO1 13 /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1u << 13)
+#define PIN_PA17E_TCC2_WO1 17 /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1u << 17)
+#define PIN_PA01E_TCC2_WO1 1 /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1u << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1u << 18)
+#define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1u << 14)
+#define PIN_PA19E_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1u << 19)
+#define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1u << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1u << 22)
+#define PIN_PB08E_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1u << 8)
+#define PIN_PB12E_TC4_WO0 44 /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1u << 12)
+#define PIN_PA23E_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1u << 23)
+#define PIN_PB09E_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1u << 9)
+#define PIN_PB13E_TC4_WO1 45 /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1u << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1u << 24)
+#define PIN_PB10E_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1u << 10)
+#define PIN_PB14E_TC5_WO0 46 /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1u << 14)
+#define PIN_PA25E_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1u << 25)
+#define PIN_PB11E_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1u << 11)
+#define PIN_PB15E_TC5_WO1 47 /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1u << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1u << 2)
+#define PIN_PB16E_TC6_WO0 48 /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1u << 16)
+#define PIN_PB03E_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1u << 3)
+#define PIN_PB17E_TC6_WO1 49 /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1u << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1u << 20)
+#define PIN_PB00E_TC7_WO0 32 /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1u << 0)
+#define PIN_PB22E_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1u << 22)
+#define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1u << 21)
+#define PIN_PB01E_TC7_WO1 33 /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1u << 1)
+#define PIN_PB23E_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1u << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1u << 2)
+#define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1u << 3)
+#define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1u << 8)
+#define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1u << 9)
+#define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1u << 4)
+#define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1u << 5)
+#define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1u << 6)
+#define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1u << 7)
+#define PIN_PB00B_ADC_AIN8 32 /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1u << 0)
+#define PIN_PB01B_ADC_AIN9 33 /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1u << 1)
+#define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1u << 2)
+#define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1u << 3)
+#define PIN_PB04B_ADC_AIN12 36 /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1u << 4)
+#define PIN_PB05B_ADC_AIN13 37 /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1u << 5)
+#define PIN_PB06B_ADC_AIN14 38 /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1u << 6)
+#define PIN_PB07B_ADC_AIN15 39 /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1u << 7)
+#define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1u << 8)
+#define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1u << 9)
+#define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1u << 10)
+#define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1u << 11)
+#define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1u << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1u << 4)
+#define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1u << 5)
+#define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1u << 6)
+#define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1u << 7)
+#define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1u << 12)
+#define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1u << 18)
+#define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1u << 13)
+#define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1u << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1u << 2)
+#define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1u << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11 /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1u << 11)
+#define PIN_PA21G_I2S_FS0 21 /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1u << 21)
+#define PIN_PB12G_I2S_FS1 44 /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1u << 12)
+#define PIN_PA09G_I2S_MCK0 9 /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1u << 9)
+#define PIN_PB17G_I2S_MCK0 49 /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1u << 17)
+#define PIN_PB10G_I2S_MCK1 42 /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1u << 10)
+#define PIN_PA10G_I2S_SCK0 10 /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1u << 10)
+#define PIN_PA20G_I2S_SCK0 20 /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1u << 20)
+#define PIN_PB11G_I2S_SCK1 43 /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1u << 11)
+#define PIN_PA07G_I2S_SD0 7 /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1u << 7)
+#define PIN_PA19G_I2S_SD0 19 /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1u << 19)
+#define PIN_PA08G_I2S_SD1 8 /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1u << 8)
+#define PIN_PB16G_I2S_SD1 48 /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1u << 16)
+
+#endif /* _SAMD21J18A_PIO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h
new file mode 100755
index 0000000000000000000000000000000000000000..5bcb77e4ad6f6be142d49d6e36aefd8b419669dd
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Top header file for SAMD21
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _SAMD21_
+#define _SAMD21_
+
+/**
+ * \defgroup SAMD21_definitions SAMD21 Device Definitions
+ * \brief SAMD21 CMSIS Definitions.
+ */
+
+#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
+#include "samd21e15a.h"
+#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
+#include "samd21e16a.h"
+#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
+#include "samd21e17a.h"
+#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
+#include "samd21e18a.h"
+#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
+#include "samd21g15a.h"
+#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
+#include "samd21g16a.h"
+#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
+#include "samd21g17a.h"
+#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
+#include "samd21g18a.h"
+#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
+#include "samd21j15a.h"
+#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
+#include "samd21j16a.h"
+#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
+#include "samd21j17a.h"
+#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
+#include "samd21j18a.h"
+#else
+ #error Library does not support the specified device.
+#endif
+
+#endif /* _SAMD21_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h
new file mode 100755
index 0000000000000000000000000000000000000000..5eeb32a81ac32f2d9ff71bdf682c305794378687
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e15a.h
@@ -0,0 +1,543 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_
+#define _SAMD21E15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
+ * This file defines all structures and symbols for SAMD21E15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x8000 /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x1000 /* 4 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x1001000D
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h
new file mode 100755
index 0000000000000000000000000000000000000000..1732fe89949ded2811a7ddeb545080312c38810f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e16a.h
@@ -0,0 +1,543 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_
+#define _SAMD21E16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
+ * This file defines all structures and symbols for SAMD21E16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x10000 /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x2000 /* 8 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x1001000C
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h
new file mode 100755
index 0000000000000000000000000000000000000000..bad36c60f2c18ff26fb6636494824c46bb413903
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e17a.h
@@ -0,0 +1,543 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_
+#define _SAMD21E17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
+ * This file defines all structures and symbols for SAMD21E17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000 /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x1001000B
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h
new file mode 100755
index 0000000000000000000000000000000000000000..83970668939ef7fa7f3ac587fe64e89c1c62c9af
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21e18a.h
@@ -0,0 +1,543 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_
+#define _SAMD21E18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
+ * This file defines all structures and symbols for SAMD21E18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000 /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x1001000A
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E18A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h
new file mode 100755
index 0000000000000000000000000000000000000000..fbc1116eb73ac6b3ae9595ba91ec100d172954ca
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g15a.h
@@ -0,0 +1,555 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_
+#define _SAMD21G15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
+ * This file defines all structures and symbols for SAMD21G15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x8000 /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x1000 /* 4 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010008
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h
new file mode 100755
index 0000000000000000000000000000000000000000..d8aa2460f9be73feb48ba255226d981c6966edf6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g16a.h
@@ -0,0 +1,555 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_
+#define _SAMD21G16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
+ * This file defines all structures and symbols for SAMD21G16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x10000 /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x2000 /* 8 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010007
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h
new file mode 100755
index 0000000000000000000000000000000000000000..0cad9c7fefc4df494ec52768c5b0ac3ea3f87170
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g17a.h
@@ -0,0 +1,555 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_
+#define _SAMD21G17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
+ * This file defines all structures and symbols for SAMD21G17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000 /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010006
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h
new file mode 100755
index 0000000000000000000000000000000000000000..76273e118161a30984da334e67216cd4b18d055e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21g18a.h
@@ -0,0 +1,555 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_
+#define _SAMD21G18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
+ * This file defines all structures and symbols for SAMD21G18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000 /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010005
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h
new file mode 100755
index 0000000000000000000000000000000000000000..a3f771ecc203abcb140440b3d63b2d03b1da5255
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j15a.h
@@ -0,0 +1,567 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_
+#define _SAMD21J15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
+ * This file defines all structures and symbols for SAMD21J15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x8000 /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x1000 /* 4 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010003
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h
new file mode 100755
index 0000000000000000000000000000000000000000..eaa2ec1d2b6f7a458ee14a56a5324555350fecae
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j16a.h
@@ -0,0 +1,567 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_
+#define _SAMD21J16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
+ * This file defines all structures and symbols for SAMD21J16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x10000 /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x2000 /* 8 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010002
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h
new file mode 100755
index 0000000000000000000000000000000000000000..5e956b9ae64447a9f685b11871d15920ac0696c2
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j17a.h
@@ -0,0 +1,567 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_
+#define _SAMD21J17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
+ * This file defines all structures and symbols for SAMD21J17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000 /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000 /* 16 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010001
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h
new file mode 100755
index 0000000000000000000000000000000000000000..1a1d7e8bd4e938670cf9c245eb0bb5bbee5ace7d
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/include/samd21j18a.h
@@ -0,0 +1,567 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400U) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400U) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000U) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000 /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000 /* 32 kB */
+#define FLASH_ADDR (0x00000000U) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
+
+#define DSU_DID_RESETVALUE 0x10010000
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
new file mode 100755
index 0000000000000000000000000000000000000000..d95be7cb8487c17c64c967c11c4e36ad824653bc
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
@@ -0,0 +1,201 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD21
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ (void*) (&_estack),
+
+ (void*) Reset_Handler,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
+ (void*) AC_Handler, /* 24 Analog Comparators */
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+ (void*) I2S_Handler /* 27 Inter-IC Sound Interface */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the relocate segment */
+ pSrc = &_etext;
+ pDest = &_srelocate;
+
+ if (pSrc != pDest) {
+ for (; pDest < &_erelocate;) {
+ *pDest++ = *pSrc++;
+ }
+ }
+
+ /* Clear the zero segment */
+ for (pDest = &_szero; pDest < &_ezero;) {
+ *pDest++ = 0;
+ }
+
+ /* Set the vector table base address */
+ pSrc = (uint32_t *) & _sfixed;
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+ /* Initialize the C library */
+ __libc_init_array();
+
+ /* Branch to main function */
+ main();
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
new file mode 100755
index 0000000000000000000000000000000000000000..917f3b056002caf9fcb6133416d630173cc9fb2f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.c
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ * the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+ // Keep the default device state after reset
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ // Not implemented
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h
new file mode 100755
index 0000000000000000000000000000000000000000..5cf7d402c8d96238d9115c74decd0cce4bdbbbc1
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/cmsis/samd21/source/system_samd21.h
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/compiler.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/compiler.h
new file mode 100755
index 0000000000000000000000000000000000000000..1d3fd78d536e0d682777f3b2185b01b1245f5c72
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/compiler.h
@@ -0,0 +1,1169 @@
+/**
+ * \file
+ *
+ * \brief Commonly used includes, types and macros.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef UTILS_COMPILER_H_INCLUDED
+#define UTILS_COMPILER_H_INCLUDED
+
+/**
+ * \defgroup group_sam0_utils Compiler abstraction layer and code utilities
+ *
+ * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices.
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.
+ *
+ * @{
+ */
+
+#if (defined __ICCARM__)
+# include <intrinsics.h>
+#endif
+
+#include <stddef.h>
+#include <parts.h>
+#include <status_codes.h>
+#include <preprocessor.h>
+#include <io.h>
+
+#ifndef __ASSEMBLY__
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * \def UNUSED
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define UNUSED(v) (void)(v)
+
+/**
+ * \def barrier
+ * \brief Memory barrier
+ */
+#ifdef __GNUC__
+# define barrier() asm volatile("" ::: "memory")
+#else
+# define barrier() asm ("")
+#endif
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg The pragma directive as it would appear after \e \#pragma
+ * (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#elif (defined __ICCARM__)
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
+#endif
+
+/**
+ * \brief Set word-aligned boundary.
+ */
+#if (defined __GNUC__) || defined(__CC_ARM)
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
+#elif (defined __ICCARM__)
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
+#endif
+
+/**
+ * \def __always_inline
+ * \brief The function should always be inlined.
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and inline the function no matter how big it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+# define __always_inline __forceinline
+#elif (defined __GNUC__)
+# define __always_inline __attribute__((__always_inline__))
+#elif (defined __ICCARM__)
+# define __always_inline _Pragma("inline=forced")
+#endif
+
+/**
+ * \def __no_inline
+ * \brief The function should never be inlined
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and not inline the function no matter how small it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+# define __no_inline __attribute__((noinline))
+#elif (defined __GNUC__)
+# define __no_inline __attribute__((noinline))
+#elif (defined __ICCARM__)
+# define __no_inline _Pragma("inline=never")
+#endif
+
+
+/** \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is false. If it is, a fatal error is
+ * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO
+ * is defined, a unit test version of the macro is used, to allow execution
+ * of further tests after a false expression.
+ *
+ * \param[in] expr Expression to evaluate and supposed to be nonzero.
+ */
+#if defined(_ASSERT_ENABLE_)
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
+# include "unit_test/suite.h"
+# else
+# undef TEST_SUITE_DEFINE_ASSERT_MACRO
+# define Assert(expr) \
+ {\
+ if (!(expr)) asm("BKPT #0");\
+ }
+# endif
+#else
+# define Assert(expr) ((void) 0)
+#endif
+
+/* Define WEAK attribute */
+#if defined ( __CC_ARM )
+# define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ )
+# define WEAK __weak
+#elif defined ( __GNUC__ )
+# define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined ( __CC_ARM )
+# define NO_INIT __attribute__((zero_init))
+#elif defined ( __ICCARM__ )
+# define NO_INIT __no_init
+#elif defined ( __GNUC__ )
+# define NO_INIT __attribute__((section(".no_init")))
+#endif
+
+#include "interrupt.h"
+
+/** \name Usual Types
+ * @{ */
+#ifndef __cplusplus
+# if !defined(__bool_true_false_are_defined)
+typedef unsigned char bool;
+# endif
+#endif
+typedef uint16_t le16_t;
+typedef uint16_t be16_t;
+typedef uint32_t le32_t;
+typedef uint32_t be32_t;
+typedef uint32_t iram_size_t;
+/** @} */
+
+/** \name Aliasing Aggregate Types
+ * @{ */
+
+/** 16-bit union. */
+typedef union
+{
+ int16_t s16;
+ uint16_t u16;
+ int8_t s8[2];
+ uint8_t u8[2];
+} Union16;
+
+/** 32-bit union. */
+typedef union
+{
+ int32_t s32;
+ uint32_t u32;
+ int16_t s16[2];
+ uint16_t u16[2];
+ int8_t s8[4];
+ uint8_t u8[4];
+} Union32;
+
+/** 64-bit union. */
+typedef union
+{
+ int64_t s64;
+ uint64_t u64;
+ int32_t s32[2];
+ uint32_t u32[2];
+ int16_t s16[4];
+ uint16_t u16[4];
+ int8_t s8[8];
+ uint8_t u8[8];
+} Union64;
+
+/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+ int64_t *s64ptr;
+ uint64_t *u64ptr;
+ int32_t *s32ptr;
+ uint32_t *u32ptr;
+ int16_t *s16ptr;
+ uint16_t *u16ptr;
+ int8_t *s8ptr;
+ uint8_t *u8ptr;
+} UnionPtr;
+
+/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+ volatile int64_t *s64ptr;
+ volatile uint64_t *u64ptr;
+ volatile int32_t *s32ptr;
+ volatile uint32_t *u32ptr;
+ volatile int16_t *s16ptr;
+ volatile uint16_t *u16ptr;
+ volatile int8_t *s8ptr;
+ volatile uint8_t *u8ptr;
+} UnionVPtr;
+
+/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+ const int64_t *s64ptr;
+ const uint64_t *u64ptr;
+ const int32_t *s32ptr;
+ const uint32_t *u32ptr;
+ const int16_t *s16ptr;
+ const uint16_t *u16ptr;
+ const int8_t *s8ptr;
+ const uint8_t *u8ptr;
+} UnionCPtr;
+
+/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef union
+{
+ const volatile int64_t *s64ptr;
+ const volatile uint64_t *u64ptr;
+ const volatile int32_t *s32ptr;
+ const volatile uint32_t *u32ptr;
+ const volatile int16_t *s16ptr;
+ const volatile uint16_t *u16ptr;
+ const volatile int8_t *s8ptr;
+ const volatile uint8_t *u8ptr;
+} UnionCVPtr;
+
+/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+ int64_t *s64ptr;
+ uint64_t *u64ptr;
+ int32_t *s32ptr;
+ uint32_t *u32ptr;
+ int16_t *s16ptr;
+ uint16_t *u16ptr;
+ int8_t *s8ptr;
+ uint8_t *u8ptr;
+} StructPtr;
+
+/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+ volatile int64_t *s64ptr;
+ volatile uint64_t *u64ptr;
+ volatile int32_t *s32ptr;
+ volatile uint32_t *u32ptr;
+ volatile int16_t *s16ptr;
+ volatile uint16_t *u16ptr;
+ volatile int8_t *s8ptr;
+ volatile uint8_t *u8ptr;
+} StructVPtr;
+
+/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+ const int64_t *s64ptr;
+ const uint64_t *u64ptr;
+ const int32_t *s32ptr;
+ const uint32_t *u32ptr;
+ const int16_t *s16ptr;
+ const uint16_t *u16ptr;
+ const int8_t *s8ptr;
+ const uint8_t *u8ptr;
+} StructCPtr;
+
+/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
+typedef struct
+{
+ const volatile int64_t *s64ptr;
+ const volatile uint64_t *u64ptr;
+ const volatile int32_t *s32ptr;
+ const volatile uint32_t *u32ptr;
+ const volatile int16_t *s16ptr;
+ const volatile uint16_t *u16ptr;
+ const volatile int8_t *s8ptr;
+ const volatile uint8_t *u8ptr;
+} StructCVPtr;
+
+/** @} */
+
+#endif /* #ifndef __ASSEMBLY__ */
+
+/** \name Usual Constants
+ * @{ */
+#define DISABLE 0
+#define ENABLE 1
+
+#ifndef __cplusplus
+# if !defined(__bool_true_false_are_defined)
+# define false 0
+# define true 1
+# endif
+#endif
+/** @} */
+
+#ifndef __ASSEMBLY__
+
+/** \name Optimization Control
+ * @{ */
+
+/**
+ * \def likely(exp)
+ * \brief The expression \a exp is likely to be true
+ */
+#if !defined(likely) || defined(__DOXYGEN__)
+# define likely(exp) (exp)
+#endif
+
+/**
+ * \def unlikely(exp)
+ * \brief The expression \a exp is unlikely to be true
+ */
+#if !defined(unlikely) || defined(__DOXYGEN__)
+# define unlikely(exp) (exp)
+#endif
+
+/**
+ * \def is_constant(exp)
+ * \brief Determine if an expression evaluates to a constant value.
+ *
+ * \param[in] exp Any expression
+ *
+ * \return true if \a exp is constant, false otherwise.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define is_constant(exp) __builtin_constant_p(exp)
+#else
+# define is_constant(exp) (0)
+#endif
+
+/** @} */
+
+/** \name Bit-Field Handling
+ * @{ */
+
+/** \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read bits from.
+ * \param[in] mask Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask) ((value) & (mask))
+
+/** \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue to write bits to.
+ * \param[in] mask Bit-mask indicating bits to write.
+ * \param[in] bits Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
+ ((bits ) & (mask)))
+
+/** \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value of which to test bits.
+ * \param[in] mask Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)
+
+/** \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue of which to clear bits.
+ * \param[in] mask Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
+
+/** \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue of which to set bits.
+ * \param[in] mask Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))
+
+/** \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue of which to toggle bits.
+ * \param[in] mask Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
+
+/** \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param[in] value Value to read a bit-field from.
+ * \param[in] mask Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))
+
+/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param[in] lvalue C lvalue to write a bit-field to.
+ * \param[in] mask Bit-mask indicating the bit-field to write.
+ * \param[in] bitfield Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask)))
+
+/** @} */
+
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define clz(u) __builtin_clz(u)
+#else
+# define clz(u) (((u) == 0) ? 32 : \
+ ((u) & (1ul << 31)) ? 0 : \
+ ((u) & (1ul << 30)) ? 1 : \
+ ((u) & (1ul << 29)) ? 2 : \
+ ((u) & (1ul << 28)) ? 3 : \
+ ((u) & (1ul << 27)) ? 4 : \
+ ((u) & (1ul << 26)) ? 5 : \
+ ((u) & (1ul << 25)) ? 6 : \
+ ((u) & (1ul << 24)) ? 7 : \
+ ((u) & (1ul << 23)) ? 8 : \
+ ((u) & (1ul << 22)) ? 9 : \
+ ((u) & (1ul << 21)) ? 10 : \
+ ((u) & (1ul << 20)) ? 11 : \
+ ((u) & (1ul << 19)) ? 12 : \
+ ((u) & (1ul << 18)) ? 13 : \
+ ((u) & (1ul << 17)) ? 14 : \
+ ((u) & (1ul << 16)) ? 15 : \
+ ((u) & (1ul << 15)) ? 16 : \
+ ((u) & (1ul << 14)) ? 17 : \
+ ((u) & (1ul << 13)) ? 18 : \
+ ((u) & (1ul << 12)) ? 19 : \
+ ((u) & (1ul << 11)) ? 20 : \
+ ((u) & (1ul << 10)) ? 21 : \
+ ((u) & (1ul << 9)) ? 22 : \
+ ((u) & (1ul << 8)) ? 23 : \
+ ((u) & (1ul << 7)) ? 24 : \
+ ((u) & (1ul << 6)) ? 25 : \
+ ((u) & (1ul << 5)) ? 26 : \
+ ((u) & (1ul << 4)) ? 27 : \
+ ((u) & (1ul << 3)) ? 28 : \
+ ((u) & (1ul << 2)) ? 29 : \
+ ((u) & (1ul << 1)) ? 30 : \
+ 31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define ctz(u) __builtin_ctz(u)
+#else
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \
+ (u) & (1ul << 1) ? 1 : \
+ (u) & (1ul << 2) ? 2 : \
+ (u) & (1ul << 3) ? 3 : \
+ (u) & (1ul << 4) ? 4 : \
+ (u) & (1ul << 5) ? 5 : \
+ (u) & (1ul << 6) ? 6 : \
+ (u) & (1ul << 7) ? 7 : \
+ (u) & (1ul << 8) ? 8 : \
+ (u) & (1ul << 9) ? 9 : \
+ (u) & (1ul << 10) ? 10 : \
+ (u) & (1ul << 11) ? 11 : \
+ (u) & (1ul << 12) ? 12 : \
+ (u) & (1ul << 13) ? 13 : \
+ (u) & (1ul << 14) ? 14 : \
+ (u) & (1ul << 15) ? 15 : \
+ (u) & (1ul << 16) ? 16 : \
+ (u) & (1ul << 17) ? 17 : \
+ (u) & (1ul << 18) ? 18 : \
+ (u) & (1ul << 19) ? 19 : \
+ (u) & (1ul << 20) ? 20 : \
+ (u) & (1ul << 21) ? 21 : \
+ (u) & (1ul << 22) ? 22 : \
+ (u) & (1ul << 23) ? 23 : \
+ (u) & (1ul << 24) ? 24 : \
+ (u) & (1ul << 25) ? 25 : \
+ (u) & (1ul << 26) ? 26 : \
+ (u) & (1ul << 27) ? 27 : \
+ (u) & (1ul << 28) ? 28 : \
+ (u) & (1ul << 29) ? 29 : \
+ (u) & (1ul << 30) ? 30 : \
+ (u) & (1ul << 31) ? 31 : \
+ 32)
+#endif
+
+/** @} */
+
+
+/** \name Bit Reversing
+ * @{ */
+
+/** \brief Reverses the bits of \a u8.
+ *
+ * \param[in] u8 U8 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u8 with reversed bits.
+ */
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
+
+/** \brief Reverses the bits of \a u16.
+ *
+ * \param[in] u16 U16 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u16 with reversed bits.
+ */
+#define bit_reverse16(u16) ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16))
+
+/** \brief Reverses the bits of \a u32.
+ *
+ * \param[in] u32 U32 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u32 with reversed bits.
+ */
+#define bit_reverse32(u32) __RBIT(u32)
+
+/** \brief Reverses the bits of \a u64.
+ *
+ * \param[in] u64 U64 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u64 with reversed bits.
+ */
+#define bit_reverse64(u64) ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\
+ ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32)))
+
+/** @} */
+
+
+/** \name Alignment
+ * @{ */
+
+/** \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n) (!Tst_bits( val, (n) - 1 ) )
+
+/** \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align(val, n) ( Rd_bits( val, (n) - 1 ) )
+
+/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param[in] lval Input/output lvalue.
+ * \param[in] n Boundary.
+ * \param[in] alg Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )
+
+/** \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up( val, n) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/** \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param[in] val Input value.
+ * \param[in] n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n) ( (val) & ~((n) - 1))
+
+/** @} */
+
+
+/** \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ * - Abs, Min and Max to apply to constant expressions (values known at
+ * compile time);
+ * - abs, min and max to apply to non-constant expressions (values unknown at
+ * compile time), abs is found in stdlib.h.
+ *
+ * @{ */
+
+/** \brief Takes the absolute value of \a a.
+ *
+ * \param[in] a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))
+
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b) (((a) < (b)) ? (a) : (b))
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b) (((a) > (b)) ? (a) : (b))
+
+/** \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define min(a, b) Min(a, b)
+
+/** \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param[in] a Input value.
+ * \param[in] b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define max(a, b) Max(a, b)
+
+/** @} */
+
+
+/** \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param[in] addr Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr) ((*(void (*)(void))(addr))())
+
+
+/** \name MCU Endianism Handling
+ * ARM is MCU little endian.
+ *
+ * @{ */
+#define BE16(x) Swap16(x)
+#define LE16(x) (x)
+
+#define le16_to_cpu(x) (x)
+#define cpu_to_le16(x) (x)
+#define LE16_TO_CPU(x) (x)
+#define CPU_TO_LE16(x) (x)
+
+#define be16_to_cpu(x) Swap16(x)
+#define cpu_to_be16(x) Swap16(x)
+#define BE16_TO_CPU(x) Swap16(x)
+#define CPU_TO_BE16(x) Swap16(x)
+
+#define le32_to_cpu(x) (x)
+#define cpu_to_le32(x) (x)
+#define LE32_TO_CPU(x) (x)
+#define CPU_TO_LE32(x) (x)
+
+#define be32_to_cpu(x) swap32(x)
+#define cpu_to_be32(x) swap32(x)
+#define BE32_TO_CPU(x) swap32(x)
+#define CPU_TO_BE32(x) swap32(x)
+/** @} */
+
+
+/** \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but GCC's
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ * at compile time);
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ * unknown at compile time).
+ *
+ * @{ */
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\
+ ((uint16_t)(u16) << 8)))
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\
+ ((uint32_t)Swap16((uint32_t)(u32)) << 16)))
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\
+ ((uint64_t)Swap32((uint64_t)(u64)) << 32)))
+
+/** \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param[in] u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap16(u16) Swap16(u16)
+
+/** \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param[in] u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+# define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32)))
+#else
+# define swap32(u32) Swap32(u32)
+#endif
+
+/** \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param[in] u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+# define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64)))
+#else
+# define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\
+ ((uint64_t)swap32((uint64_t)(u64)) << 32)))
+#endif
+
+/** @} */
+
+
+/** \name Target Abstraction
+ *
+ * @{ */
+
+#define _GLOBEXT_ extern /**< extern storage-class specifier. */
+#define _CONST_TYPE_ const /**< const type qualifier. */
+#define _MEM_TYPE_SLOW_ /**< Slow memory type. */
+#define _MEM_TYPE_MEDFAST_ /**< Fairly fast memory type. */
+#define _MEM_TYPE_FAST_ /**< Fast memory type. */
+
+#define memcmp_ram2ram memcmp /**< Target-specific memcmp of RAM to RAM. */
+#define memcmp_code2ram memcmp /**< Target-specific memcmp of RAM to NVRAM. */
+#define memcpy_ram2ram memcpy /**< Target-specific memcpy from RAM to RAM. */
+#define memcpy_code2ram memcpy /**< Target-specific memcpy from NVRAM to RAM. */
+
+/** @} */
+
+/**
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
+ * integer arithmetic.
+ *
+ * \param[in] a An integer
+ * \param[in] b Another integer
+ *
+ * \return (\a a / \a b) rounded up to the nearest integer.
+ */
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))
+
+#endif /* #ifndef __ASSEMBLY__ */
+#ifdef __ICCARM__
+/** \name Compiler Keywords
+ *
+ * Port of some keywords from GCC to IAR Embedded Workbench.
+ *
+ * @{ */
+
+#define __asm__ asm
+#define __inline__ inline
+#define __volatile__
+
+/** @} */
+
+#endif
+
+#define FUNC_PTR void *
+/**
+ * \def unused
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define unused(v) do { (void)(v); } while(0)
+
+/* Define RAMFUNC attribute */
+#if defined ( __CC_ARM ) /* Keil uVision 4 */
+# define RAMFUNC __attribute__ ((section(".ramfunc")))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define RAMFUNC __ramfunc
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define RAMFUNC __attribute__ ((section(".ramfunc")))
+#endif
+
+/* Define OPTIMIZE_HIGH attribute */
+#if defined ( __CC_ARM ) /* Keil uVision 4 */
+# define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define OPTIMIZE_HIGH _Pragma("optimize=high")
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define OPTIMIZE_HIGH __attribute__((optimize(s)))
+#endif
+#define PASS 0
+#define FAIL 1
+#define LOW 0
+#define HIGH 1
+
+typedef int8_t S8 ; //!< 8-bit signed integer.
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.
+typedef int16_t S16; //!< 16-bit signed integer.
+typedef uint16_t U16; //!< 16-bit unsigned integer.
+typedef int32_t S32; //!< 32-bit signed integer.
+typedef uint32_t U32; //!< 32-bit unsigned integer.
+typedef int64_t S64; //!< 64-bit signed integer.
+typedef uint64_t U64; //!< 64-bit unsigned integer.
+typedef float F32; //!< 32-bit floating-point number.
+typedef double F64; //!< 64-bit floating-point number.
+
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
+
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
+
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
+
+#if defined(__ICCARM__)
+#define SHORTENUM __packed
+#elif defined(__GNUC__)
+#define SHORTENUM __attribute__((packed))
+#endif
+
+/* No operation */
+#if defined(__ICCARM__)
+#define nop() __no_operation()
+#elif defined(__GNUC__)
+#define nop() (__NOP())
+#endif
+
+#define FLASH_DECLARE(x) const x
+#define FLASH_EXTERN(x) extern const x
+#define PGM_READ_BYTE(x) *(x)
+#define PGM_READ_WORD(x) *(x)
+#define MEMCPY_ENDIAN memcpy
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
+
+/*Defines the Flash Storage for the request and response of MAC*/
+#define CMD_ID_OCTET (0)
+
+/* Converting of values from CPU endian to little endian. */
+#define CPU_ENDIAN_TO_LE16(x) (x)
+#define CPU_ENDIAN_TO_LE32(x) (x)
+#define CPU_ENDIAN_TO_LE64(x) (x)
+
+/* Converting of values from little endian to CPU endian. */
+#define LE16_TO_CPU_ENDIAN(x) (x)
+#define LE32_TO_CPU_ENDIAN(x) (x)
+#define LE64_TO_CPU_ENDIAN(x) (x)
+
+/* Converting of constants from little endian to CPU endian. */
+#define CLE16_TO_CPU_ENDIAN(x) (x)
+#define CLE32_TO_CPU_ENDIAN(x) (x)
+#define CLE64_TO_CPU_ENDIAN(x) (x)
+
+/* Converting of constants from CPU endian to little endian. */
+#define CCPU_ENDIAN_TO_LE16(x) (x)
+#define CCPU_ENDIAN_TO_LE32(x) (x)
+#define CCPU_ENDIAN_TO_LE64(x) (x)
+
+#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))
+#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))
+
+/**
+ * @brief Converts a 64-Bit value into a 8 Byte array
+ *
+ * @param[in] value 64-Bit value
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
+{
+ uint8_t index = 0;
+
+ while (index < 8)
+ {
+ data[index++] = value & 0xFF;
+ value = value >> 8;
+ }
+}
+
+/**
+ * @brief Converts a 16-Bit value into a 2 Byte array
+ *
+ * @param[in] value 16-Bit value
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/*
+ * @brief Converts a 2 Byte array into a 16-Bit value
+ *
+ * @param data Specifies the pointer to the 2 Byte array
+ *
+ * @return 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
+{
+ return (data[0] | ((uint16_t)data[1] << 8));
+}
+
+/* Converts a 4 Byte array into a 32-Bit value */
+static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
+{
+ union
+ {
+ uint32_t u32;
+ uint8_t u8[4];
+ }long_addr;
+ uint8_t index;
+ for (index = 0; index < 4; index++)
+ {
+ long_addr.u8[index] = *data++;
+ }
+ return long_addr.u32;
+}
+
+/**
+ * @brief Converts a 8 Byte array into a 64-Bit value
+ *
+ * @param data Specifies the pointer to the 8 Byte array
+ *
+ * @return 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
+{
+ union
+ {
+ uint64_t u64;
+ uint8_t u8[8];
+ } long_addr;
+
+ uint8_t index;
+
+ for (index = 0; index < 8; index++)
+ {
+ long_addr.u8[index] = *data++;
+ }
+
+ return long_addr.u64;
+}
+
+/** @} */
+
+#endif /* UTILS_COMPILER_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/header_files/io.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/header_files/io.h
new file mode 100755
index 0000000000000000000000000000000000000000..6f2b5697a2f81fc72c8fcebb76dd4eb86fe5598b
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/header_files/io.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Arch file for SAM0.
+ *
+ * This file defines common SAM0 series.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAM_IO_
+#define _SAM_IO_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/* SAM D20 family */
+#if (SAMD20)
+# include "samd20.h"
+#endif
+
+#if (SAMD21)
+# include "samd21.h"
+#endif
+
+#if (SAMR21)
+# include "samr21.h"
+#endif
+
+#if (SAMD10)
+# include "samd10.h"
+#endif
+
+#if (SAMD11)
+# include "samd11.h"
+#endif
+
+#endif /* _SAM_IO_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
new file mode 100755
index 0000000000000000000000000000000000000000..d59417d117446c7f1cb763fd21b1daf38444bbd6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/make/Makefile.sam.in b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/make/Makefile.sam.in
new file mode 100755
index 0000000000000000000000000000000000000000..d07e471899bd8fd4c13c5a7572425b45027ec446
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/make/Makefile.sam.in
@@ -0,0 +1,502 @@
+# List of available make goals:
+#
+# all Default target, builds the project
+# clean Clean up the project
+# rebuild Rebuild the project
+# debug_flash Builds the project and debug in flash
+# debug_sram Builds the project and debug in sram
+#
+# doc Build the documentation
+# cleandoc Clean up the documentation
+# rebuilddoc Rebuild the documentation
+#
+# \file
+#
+# Copyright (c) 2011 - 2014 Atmel Corporation. All rights reserved.
+#
+# \asf_license_start
+#
+# \page License
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. The name of Atmel may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# 4. This software may only be redistributed and used in connection with an
+# Atmel microcontroller product.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# \asf_license_stop
+#
+
+# Include the config.mk file from the current working path, e.g., where the
+# user called make.
+include config.mk
+
+# Tool to use to generate documentation from the source code
+DOCGEN ?= doxygen
+
+# Look for source files relative to the top-level source directory
+VPATH := $(PRJ_PATH)
+
+# Output target file
+project_type := $(PROJECT_TYPE)
+
+# Output target file
+ifeq ($(project_type),flash)
+target := $(TARGET_FLASH)
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)
+else
+target := $(TARGET_SRAM)
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)
+endif
+
+# Output project name (target name minus suffix)
+project := $(basename $(target))
+
+# Output target file (typically ELF or static library)
+ifeq ($(suffix $(target)),.a)
+target_type := lib
+else
+ifeq ($(suffix $(target)),.elf)
+target_type := elf
+else
+$(error "Target type $(target_type) is not supported")
+endif
+endif
+
+# Allow override of operating system detection. The user can add OS=Linux or
+# OS=Windows on the command line to explicit set the host OS.
+#
+# This allows to work around broken uname utility on certain systems.
+ifdef OS
+ ifeq ($(strip $(OS)), Linux)
+ os_type := Linux
+ endif
+ ifeq ($(strip $(OS)), Windows)
+ os_type := windows32_64
+ endif
+endif
+
+os_type ?= $(strip $(shell uname))
+
+ifeq ($(os_type),windows32)
+os := Windows
+else
+ifeq ($(os_type),windows64)
+os := Windows
+else
+ifeq ($(os_type),windows32_64)
+os ?= Windows
+else
+ifeq ($(os_type),)
+os := Windows
+else
+# Default to Linux style operating system. Both Cygwin and mingw are fully
+# compatible (for this Makefile) with Linux.
+os := Linux
+endif
+endif
+endif
+endif
+
+# Output documentation directory and configuration file.
+docdir := ../doxygen/html
+doccfg := ../doxygen/doxyfile.doxygen
+
+CROSS ?= arm-none-eabi-
+AR := $(CROSS)ar
+AS := $(CROSS)as
+CC := $(CROSS)gcc
+CPP := $(CROSS)gcc -E
+CXX := $(CROSS)g++
+LD := $(CROSS)g++
+NM := $(CROSS)nm
+OBJCOPY := $(CROSS)objcopy
+OBJDUMP := $(CROSS)objdump
+SIZE := $(CROSS)size
+GDB := $(CROSS)gdb
+
+RM := rm
+ifeq ($(os),Windows)
+RMDIR := rmdir /S /Q
+else
+RMDIR := rmdir -p --ignore-fail-on-non-empty
+endif
+
+# On Windows, we need to override the shell to force the use of cmd.exe
+ifeq ($(os),Windows)
+SHELL := cmd
+endif
+
+# Strings for beautifying output
+MSG_CLEAN_FILES = "RM *.o *.d"
+MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"
+MSG_CLEAN_DOC = "RMDIR $(docdir)"
+MSG_MKDIR = "MKDIR $(dir $@)"
+
+MSG_INFO = "INFO "
+MSG_PREBUILD = "PREBUILD $(PREBUILD_CMD)"
+MSG_POSTBUILD = "POSTBUILD $(POSTBUILD_CMD)"
+
+MSG_ARCHIVING = "AR $@"
+MSG_ASSEMBLING = "AS $@"
+MSG_BINARY_IMAGE = "OBJCOPY $@"
+MSG_COMPILING = "CC $@"
+MSG_COMPILING_CXX = "CXX $@"
+MSG_EXTENDED_LISTING = "OBJDUMP $@"
+MSG_IHEX_IMAGE = "OBJCOPY $@"
+MSG_LINKING = "LN $@"
+MSG_PREPROCESSING = "CPP $@"
+MSG_SIZE = "SIZE $@"
+MSG_SYMBOL_TABLE = "NM $@"
+
+MSG_GENERATING_DOC = "DOXYGEN $(docdir)"
+
+# Don't use make's built-in rules and variables
+MAKEFLAGS += -rR
+
+# Don't print 'Entering directory ...'
+MAKEFLAGS += --no-print-directory
+
+# Function for reversing the order of a list
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
+
+# Hide command output by default, but allow the user to override this
+# by adding V=1 on the command line.
+#
+# This is inspired by the Kbuild system used by the Linux kernel.
+ifdef V
+ ifeq ("$(origin V)", "command line")
+ VERBOSE = $(V)
+ endif
+endif
+ifndef VERBOSE
+ VERBOSE = 0
+endif
+
+ifeq ($(VERBOSE), 1)
+ Q =
+else
+ Q = @
+endif
+
+arflags-gnu-y := $(ARFLAGS)
+asflags-gnu-y := $(ASFLAGS)
+cflags-gnu-y := $(CFLAGS)
+cxxflags-gnu-y := $(CXXFLAGS)
+cppflags-gnu-y := $(CPPFLAGS)
+cpuflags-gnu-y :=
+dbgflags-gnu-y := $(DBGFLAGS)
+libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))
+ldflags-gnu-y := $(LDFLAGS)
+flashflags-gnu-y :=
+clean-files :=
+clean-dirs :=
+
+clean-files += $(wildcard $(target) $(project).map)
+clean-files += $(wildcard $(project).hex $(project).bin)
+clean-files += $(wildcard $(project).lss $(project).sym)
+clean-files += $(wildcard $(build))
+
+# Use pipes instead of temporary files for communication between processes
+cflags-gnu-y += -pipe
+asflags-gnu-y += -pipe
+ldflags-gnu-y += -pipe
+
+# Archiver flags.
+arflags-gnu-y += rcs
+
+# Always enable warnings. And be very careful about implicit
+# declarations.
+cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes
+cflags-gnu-y += -Werror-implicit-function-declaration
+cxxflags-gnu-y += -Wall
+# IAR doesn't allow arithmetic on void pointers, so warn about that.
+cflags-gnu-y += -Wpointer-arith
+cxxflags-gnu-y += -Wpointer-arith
+
+# Preprocessor flags.
+cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
+asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
+
+# CPU specific flags.
+cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__
+
+# Dependency file flags.
+depflags = -MD -MP -MQ $@
+
+# Debug specific flags.
+ifdef BUILD_DEBUG_LEVEL
+dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)
+else
+dbgflags-gnu-y += -g3
+endif
+
+# Optimization specific flags.
+ifdef BUILD_OPTIMIZATION
+optflags-gnu-y = -O$(BUILD_OPTIMIZATION)
+else
+optflags-gnu-y = $(OPTIMIZATION)
+endif
+
+# Always preprocess assembler files.
+asflags-gnu-y += -x assembler-with-cpp
+# Compile C files using the GNU99 standard.
+cflags-gnu-y += -std=gnu99
+# Compile C++ files using the GNU++98 standard.
+cxxflags-gnu-y += -std=gnu++98
+
+# Don't use strict aliasing (very common in embedded applications).
+cflags-gnu-y += -fno-strict-aliasing
+cxxflags-gnu-y += -fno-strict-aliasing
+
+# Separate each function and data into its own separate section to allow
+# garbage collection of unused sections.
+cflags-gnu-y += -ffunction-sections -fdata-sections
+cxxflags-gnu-y += -ffunction-sections -fdata-sections
+
+# Various cflags.
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+cflags-gnu-y += -Wmain -Wparentheses
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings
+cflags-gnu-y += -Wsign-compare -Waggregate-return
+cflags-gnu-y += -Wmissing-declarations
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long
+cflags-gnu-y += -Wunreachable-code
+cflags-gnu-y += -Wcast-align
+cflags-gnu-y += --param max-inline-insns-single=500
+
+# To reduce application size use only integer printf function.
+cflags-gnu-y += -Dprintf=iprintf
+
+# Use newlib-nano to reduce application size
+ldflags-gnu-y += --specs=nano.specs
+
+# Garbage collect unreferred sections when linking.
+ldflags-gnu-y += -Wl,--gc-sections
+
+# Use the linker script if provided by the project.
+ifneq ($(strip $(linker_script)),)
+ldflags-gnu-y += -Wl,-T $(linker_script)
+endif
+
+# Output a link map file and a cross reference table
+ldflags-gnu-y += -Wl,-Map=$(project).map,--cref
+
+# Add library search paths relative to the top level directory.
+ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
+
+a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
+c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
+l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
+ar_flags = $(arflags-gnu-y)
+
+# Source files list and part informations must already be included before
+# running this makefile
+
+# If a custom build directory is specified, use it -- force trailing / in directory name.
+ifdef BUILD_DIR
+ build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
+else
+ build-dir =
+endif
+
+# Create object files list from source files list.
+obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
+# Create dependency files list from source files list.
+dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
+
+clean-files += $(wildcard $(obj-y))
+clean-files += $(dep-files)
+
+clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
+
+# Default target.
+.PHONY: all
+ifeq ($(project_type),all)
+all:
+ $(MAKE) all PROJECT_TYPE=flash
+ $(MAKE) all PROJECT_TYPE=sram
+else
+ifeq ($(target_type),lib)
+all: $(target) $(project).lss $(project).sym
+else
+ifeq ($(target_type),elf)
+all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
+endif
+endif
+endif
+
+prebuild:
+ifneq ($(strip $(PREBUILD_CMD)),)
+ @echo $(MSG_PREBUILD)
+ $(Q)$(PREBUILD_CMD)
+endif
+
+postbuild:
+ifneq ($(strip $(POSTBUILD_CMD)),)
+ @echo $(MSG_POSTBUILD)
+ $(Q)$(POSTBUILD_CMD)
+endif
+
+# Clean up the project.
+.PHONY: clean
+clean:
+ @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
+ $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
+ @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
+# Remove created directories, and make sure we only remove existing
+# directories, since recursive rmdir might help us a bit on the way.
+ifeq ($(os),Windows)
+ $(Q)$(if $(strip $(clean-dirs)), \
+ $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
+else
+ $(Q)$(if $(strip $(clean-dirs)), \
+ for directory in $(strip $(clean-dirs)); do \
+ if [ -d "$$directory" ]; then \
+ $(RMDIR) $$directory; \
+ fi \
+ done \
+ )
+endif
+
+# Rebuild the project.
+.PHONY: rebuild
+rebuild: clean all
+
+# Debug the project in flash.
+.PHONY: debug_flash
+debug_flash: all
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)
+
+# Debug the project in sram.
+.PHONY: debug_sram
+debug_sram: all
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)
+
+.PHONY: objfiles
+objfiles: $(obj-y)
+
+# Create object files from C source files.
+$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+ @echo $(MSG_COMPILING)
+ $(Q)$(CC) $(c_flags) -c $< -o $@
+
+# Create object files from C++ source files.
+$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+ @echo $(MSG_COMPILING_CXX)
+ $(Q)$(CXX) $(cxx_flags) -c $< -o $@
+
+# Preprocess and assemble: create object files from assembler source files.
+$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
+ifeq ($(os),Windows)
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
+else
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
+endif
+ @echo $(MSG_ASSEMBLING)
+ $(Q)$(CC) $(a_flags) -c $< -o $@
+
+# Include all dependency files to add depedency to all header files in use.
+include $(dep-files)
+
+ifeq ($(target_type),lib)
+# Archive object files into an archive
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
+ @echo $(MSG_ARCHIVING)
+ $(Q)$(AR) $(ar_flags) $@ $(obj-y)
+ @echo $(MSG_SIZE)
+ $(Q)$(SIZE) -Bxt $@
+else
+ifeq ($(target_type),elf)
+# Link the object files into an ELF file. Also make sure the target is rebuilt
+# if the common Makefile.sam.in or project config.mk is changed.
+$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)
+ @echo $(MSG_LINKING)
+ $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
+ @echo $(MSG_SIZE)
+ $(Q)$(SIZE) -Ax $@
+ $(Q)$(SIZE) -Bx $@
+endif
+endif
+
+# Create extended function listing from target output file.
+%.lss: $(target)
+ @echo $(MSG_EXTENDED_LISTING)
+ $(Q)$(OBJDUMP) -h -S $< > $@
+
+# Create symbol table from target output file.
+%.sym: $(target)
+ @echo $(MSG_SYMBOL_TABLE)
+ $(Q)$(NM) -n $< > $@
+
+# Create Intel HEX image from ELF output file.
+%.hex: $(target)
+ @echo $(MSG_IHEX_IMAGE)
+ $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@
+
+# Create binary image from ELF output file.
+%.bin: $(target)
+ @echo $(MSG_BINARY_IMAGE)
+ $(Q)$(OBJCOPY) -O binary $< $@
+
+# Provide information about the detected host operating system.
+.SECONDARY: info-os
+info-os:
+ @echo $(MSG_INFO)$(os) build host detected
+
+# Build Doxygen generated documentation.
+.PHONY: doc
+doc:
+ @echo $(MSG_GENERATING_DOC)
+ $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
+
+# Clean Doxygen generated documentation.
+.PHONY: cleandoc
+cleandoc:
+ @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
+ $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
+
+# Rebuild the Doxygen generated documentation.
+.PHONY: rebuilddoc
+rebuilddoc: cleandoc doc
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/mrecursion.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/mrecursion.h
new file mode 100755
index 0000000000000000000000000000000000000000..a05f8fa2c5392f887c56870803edda3d55eb1305
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/mrecursion.h
@@ -0,0 +1,595 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro recursion utils.
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _MRECURSION_H_
+#define _MRECURSION_H_
+
+/**
+ * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+#define DEC_256 255
+#define DEC_255 254
+#define DEC_254 253
+#define DEC_253 252
+#define DEC_252 251
+#define DEC_251 250
+#define DEC_250 249
+#define DEC_249 248
+#define DEC_248 247
+#define DEC_247 246
+#define DEC_246 245
+#define DEC_245 244
+#define DEC_244 243
+#define DEC_243 242
+#define DEC_242 241
+#define DEC_241 240
+#define DEC_240 239
+#define DEC_239 238
+#define DEC_238 237
+#define DEC_237 236
+#define DEC_236 235
+#define DEC_235 234
+#define DEC_234 233
+#define DEC_233 232
+#define DEC_232 231
+#define DEC_231 230
+#define DEC_230 229
+#define DEC_229 228
+#define DEC_228 227
+#define DEC_227 226
+#define DEC_226 225
+#define DEC_225 224
+#define DEC_224 223
+#define DEC_223 222
+#define DEC_222 221
+#define DEC_221 220
+#define DEC_220 219
+#define DEC_219 218
+#define DEC_218 217
+#define DEC_217 216
+#define DEC_216 215
+#define DEC_215 214
+#define DEC_214 213
+#define DEC_213 212
+#define DEC_212 211
+#define DEC_211 210
+#define DEC_210 209
+#define DEC_209 208
+#define DEC_208 207
+#define DEC_207 206
+#define DEC_206 205
+#define DEC_205 204
+#define DEC_204 203
+#define DEC_203 202
+#define DEC_202 201
+#define DEC_201 200
+#define DEC_200 199
+#define DEC_199 198
+#define DEC_198 197
+#define DEC_197 196
+#define DEC_196 195
+#define DEC_195 194
+#define DEC_194 193
+#define DEC_193 192
+#define DEC_192 191
+#define DEC_191 190
+#define DEC_190 189
+#define DEC_189 188
+#define DEC_188 187
+#define DEC_187 186
+#define DEC_186 185
+#define DEC_185 184
+#define DEC_184 183
+#define DEC_183 182
+#define DEC_182 181
+#define DEC_181 180
+#define DEC_180 179
+#define DEC_179 178
+#define DEC_178 177
+#define DEC_177 176
+#define DEC_176 175
+#define DEC_175 174
+#define DEC_174 173
+#define DEC_173 172
+#define DEC_172 171
+#define DEC_171 170
+#define DEC_170 169
+#define DEC_169 168
+#define DEC_168 167
+#define DEC_167 166
+#define DEC_166 165
+#define DEC_165 164
+#define DEC_164 163
+#define DEC_163 162
+#define DEC_162 161
+#define DEC_161 160
+#define DEC_160 159
+#define DEC_159 158
+#define DEC_158 157
+#define DEC_157 156
+#define DEC_156 155
+#define DEC_155 154
+#define DEC_154 153
+#define DEC_153 152
+#define DEC_152 151
+#define DEC_151 150
+#define DEC_150 149
+#define DEC_149 148
+#define DEC_148 147
+#define DEC_147 146
+#define DEC_146 145
+#define DEC_145 144
+#define DEC_144 143
+#define DEC_143 142
+#define DEC_142 141
+#define DEC_141 140
+#define DEC_140 139
+#define DEC_139 138
+#define DEC_138 137
+#define DEC_137 136
+#define DEC_136 135
+#define DEC_135 134
+#define DEC_134 133
+#define DEC_133 132
+#define DEC_132 131
+#define DEC_131 130
+#define DEC_130 129
+#define DEC_129 128
+#define DEC_128 127
+#define DEC_127 126
+#define DEC_126 125
+#define DEC_125 124
+#define DEC_124 123
+#define DEC_123 122
+#define DEC_122 121
+#define DEC_121 120
+#define DEC_120 119
+#define DEC_119 118
+#define DEC_118 117
+#define DEC_117 116
+#define DEC_116 115
+#define DEC_115 114
+#define DEC_114 113
+#define DEC_113 112
+#define DEC_112 111
+#define DEC_111 110
+#define DEC_110 109
+#define DEC_109 108
+#define DEC_108 107
+#define DEC_107 106
+#define DEC_106 105
+#define DEC_105 104
+#define DEC_104 103
+#define DEC_103 102
+#define DEC_102 101
+#define DEC_101 100
+#define DEC_100 99
+#define DEC_99 98
+#define DEC_98 97
+#define DEC_97 96
+#define DEC_96 95
+#define DEC_95 94
+#define DEC_94 93
+#define DEC_93 92
+#define DEC_92 91
+#define DEC_91 90
+#define DEC_90 89
+#define DEC_89 88
+#define DEC_88 87
+#define DEC_87 86
+#define DEC_86 85
+#define DEC_85 84
+#define DEC_84 83
+#define DEC_83 82
+#define DEC_82 81
+#define DEC_81 80
+#define DEC_80 79
+#define DEC_79 78
+#define DEC_78 77
+#define DEC_77 76
+#define DEC_76 75
+#define DEC_75 74
+#define DEC_74 73
+#define DEC_73 72
+#define DEC_72 71
+#define DEC_71 70
+#define DEC_70 69
+#define DEC_69 68
+#define DEC_68 67
+#define DEC_67 66
+#define DEC_66 65
+#define DEC_65 64
+#define DEC_64 63
+#define DEC_63 62
+#define DEC_62 61
+#define DEC_61 60
+#define DEC_60 59
+#define DEC_59 58
+#define DEC_58 57
+#define DEC_57 56
+#define DEC_56 55
+#define DEC_55 54
+#define DEC_54 53
+#define DEC_53 52
+#define DEC_52 51
+#define DEC_51 50
+#define DEC_50 49
+#define DEC_49 48
+#define DEC_48 47
+#define DEC_47 46
+#define DEC_46 45
+#define DEC_45 44
+#define DEC_44 43
+#define DEC_43 42
+#define DEC_42 41
+#define DEC_41 40
+#define DEC_40 39
+#define DEC_39 38
+#define DEC_38 37
+#define DEC_37 36
+#define DEC_36 35
+#define DEC_35 34
+#define DEC_34 33
+#define DEC_33 32
+#define DEC_32 31
+#define DEC_31 30
+#define DEC_30 29
+#define DEC_29 28
+#define DEC_28 27
+#define DEC_27 26
+#define DEC_26 25
+#define DEC_25 24
+#define DEC_24 23
+#define DEC_23 22
+#define DEC_22 21
+#define DEC_21 20
+#define DEC_20 19
+#define DEC_19 18
+#define DEC_18 17
+#define DEC_17 16
+#define DEC_16 15
+#define DEC_15 14
+#define DEC_14 13
+#define DEC_13 12
+#define DEC_12 11
+#define DEC_11 10
+#define DEC_10 9
+#define DEC_9 8
+#define DEC_8 7
+#define DEC_7 6
+#define DEC_6 5
+#define DEC_5 4
+#define DEC_4 3
+#define DEC_3 2
+#define DEC_2 1
+#define DEC_1 0
+#define DEC_(n) DEC_##n
+
+
+/** Maximal number of repetitions supported by MRECURSION. */
+#define MRECURSION_LIMIT 256
+
+/** \brief Macro recursion.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count The number of repetitious calls to macro. Valid values
+ * range from 0 to MRECURSION_LIMIT.
+ * \param[in] macro A binary operation of the form macro(data, n). This macro
+ * is expanded by MRECURSION with the current repetition number
+ * and the auxiliary data argument.
+ * \param[in] data A recursive threshold, building on this to decline by times
+ * defined with param count.
+ *
+ * \return <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
+ */
+#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data)
+
+#define MRECURSION0( macro, data)
+#define MRECURSION1( macro, data) MRECURSION0( macro, DEC_(data)) macro(data, 0)
+#define MRECURSION2( macro, data) MRECURSION1( macro, DEC_(data)) macro(data, 1)
+#define MRECURSION3( macro, data) MRECURSION2( macro, DEC_(data)) macro(data, 2)
+#define MRECURSION4( macro, data) MRECURSION3( macro, DEC_(data)) macro(data, 3)
+#define MRECURSION5( macro, data) MRECURSION4( macro, DEC_(data)) macro(data, 4)
+#define MRECURSION6( macro, data) MRECURSION5( macro, DEC_(data)) macro(data, 5)
+#define MRECURSION7( macro, data) MRECURSION6( macro, DEC_(data)) macro(data, 6)
+#define MRECURSION8( macro, data) MRECURSION7( macro, DEC_(data)) macro(data, 7)
+#define MRECURSION9( macro, data) MRECURSION8( macro, DEC_(data)) macro(data, 8)
+#define MRECURSION10( macro, data) MRECURSION9( macro, DEC_(data)) macro(data, 9)
+#define MRECURSION11( macro, data) MRECURSION10( macro, DEC_(data)) macro(data, 10)
+#define MRECURSION12( macro, data) MRECURSION11( macro, DEC_(data)) macro(data, 11)
+#define MRECURSION13( macro, data) MRECURSION12( macro, DEC_(data)) macro(data, 12)
+#define MRECURSION14( macro, data) MRECURSION13( macro, DEC_(data)) macro(data, 13)
+#define MRECURSION15( macro, data) MRECURSION14( macro, DEC_(data)) macro(data, 14)
+#define MRECURSION16( macro, data) MRECURSION15( macro, DEC_(data)) macro(data, 15)
+#define MRECURSION17( macro, data) MRECURSION16( macro, DEC_(data)) macro(data, 16)
+#define MRECURSION18( macro, data) MRECURSION17( macro, DEC_(data)) macro(data, 17)
+#define MRECURSION19( macro, data) MRECURSION18( macro, DEC_(data)) macro(data, 18)
+#define MRECURSION20( macro, data) MRECURSION19( macro, DEC_(data)) macro(data, 19)
+#define MRECURSION21( macro, data) MRECURSION20( macro, DEC_(data)) macro(data, 20)
+#define MRECURSION22( macro, data) MRECURSION21( macro, DEC_(data)) macro(data, 21)
+#define MRECURSION23( macro, data) MRECURSION22( macro, DEC_(data)) macro(data, 22)
+#define MRECURSION24( macro, data) MRECURSION23( macro, DEC_(data)) macro(data, 23)
+#define MRECURSION25( macro, data) MRECURSION24( macro, DEC_(data)) macro(data, 24)
+#define MRECURSION26( macro, data) MRECURSION25( macro, DEC_(data)) macro(data, 25)
+#define MRECURSION27( macro, data) MRECURSION26( macro, DEC_(data)) macro(data, 26)
+#define MRECURSION28( macro, data) MRECURSION27( macro, DEC_(data)) macro(data, 27)
+#define MRECURSION29( macro, data) MRECURSION28( macro, DEC_(data)) macro(data, 28)
+#define MRECURSION30( macro, data) MRECURSION29( macro, DEC_(data)) macro(data, 29)
+#define MRECURSION31( macro, data) MRECURSION30( macro, DEC_(data)) macro(data, 30)
+#define MRECURSION32( macro, data) MRECURSION31( macro, DEC_(data)) macro(data, 31)
+#define MRECURSION33( macro, data) MRECURSION32( macro, DEC_(data)) macro(data, 32)
+#define MRECURSION34( macro, data) MRECURSION33( macro, DEC_(data)) macro(data, 33)
+#define MRECURSION35( macro, data) MRECURSION34( macro, DEC_(data)) macro(data, 34)
+#define MRECURSION36( macro, data) MRECURSION35( macro, DEC_(data)) macro(data, 35)
+#define MRECURSION37( macro, data) MRECURSION36( macro, DEC_(data)) macro(data, 36)
+#define MRECURSION38( macro, data) MRECURSION37( macro, DEC_(data)) macro(data, 37)
+#define MRECURSION39( macro, data) MRECURSION38( macro, DEC_(data)) macro(data, 38)
+#define MRECURSION40( macro, data) MRECURSION39( macro, DEC_(data)) macro(data, 39)
+#define MRECURSION41( macro, data) MRECURSION40( macro, DEC_(data)) macro(data, 40)
+#define MRECURSION42( macro, data) MRECURSION41( macro, DEC_(data)) macro(data, 41)
+#define MRECURSION43( macro, data) MRECURSION42( macro, DEC_(data)) macro(data, 42)
+#define MRECURSION44( macro, data) MRECURSION43( macro, DEC_(data)) macro(data, 43)
+#define MRECURSION45( macro, data) MRECURSION44( macro, DEC_(data)) macro(data, 44)
+#define MRECURSION46( macro, data) MRECURSION45( macro, DEC_(data)) macro(data, 45)
+#define MRECURSION47( macro, data) MRECURSION46( macro, DEC_(data)) macro(data, 46)
+#define MRECURSION48( macro, data) MRECURSION47( macro, DEC_(data)) macro(data, 47)
+#define MRECURSION49( macro, data) MRECURSION48( macro, DEC_(data)) macro(data, 48)
+#define MRECURSION50( macro, data) MRECURSION49( macro, DEC_(data)) macro(data, 49)
+#define MRECURSION51( macro, data) MRECURSION50( macro, DEC_(data)) macro(data, 50)
+#define MRECURSION52( macro, data) MRECURSION51( macro, DEC_(data)) macro(data, 51)
+#define MRECURSION53( macro, data) MRECURSION52( macro, DEC_(data)) macro(data, 52)
+#define MRECURSION54( macro, data) MRECURSION53( macro, DEC_(data)) macro(data, 53)
+#define MRECURSION55( macro, data) MRECURSION54( macro, DEC_(data)) macro(data, 54)
+#define MRECURSION56( macro, data) MRECURSION55( macro, DEC_(data)) macro(data, 55)
+#define MRECURSION57( macro, data) MRECURSION56( macro, DEC_(data)) macro(data, 56)
+#define MRECURSION58( macro, data) MRECURSION57( macro, DEC_(data)) macro(data, 57)
+#define MRECURSION59( macro, data) MRECURSION58( macro, DEC_(data)) macro(data, 58)
+#define MRECURSION60( macro, data) MRECURSION59( macro, DEC_(data)) macro(data, 59)
+#define MRECURSION61( macro, data) MRECURSION60( macro, DEC_(data)) macro(data, 60)
+#define MRECURSION62( macro, data) MRECURSION61( macro, DEC_(data)) macro(data, 61)
+#define MRECURSION63( macro, data) MRECURSION62( macro, DEC_(data)) macro(data, 62)
+#define MRECURSION64( macro, data) MRECURSION63( macro, DEC_(data)) macro(data, 63)
+#define MRECURSION65( macro, data) MRECURSION64( macro, DEC_(data)) macro(data, 64)
+#define MRECURSION66( macro, data) MRECURSION65( macro, DEC_(data)) macro(data, 65)
+#define MRECURSION67( macro, data) MRECURSION66( macro, DEC_(data)) macro(data, 66)
+#define MRECURSION68( macro, data) MRECURSION67( macro, DEC_(data)) macro(data, 67)
+#define MRECURSION69( macro, data) MRECURSION68( macro, DEC_(data)) macro(data, 68)
+#define MRECURSION70( macro, data) MRECURSION69( macro, DEC_(data)) macro(data, 69)
+#define MRECURSION71( macro, data) MRECURSION70( macro, DEC_(data)) macro(data, 70)
+#define MRECURSION72( macro, data) MRECURSION71( macro, DEC_(data)) macro(data, 71)
+#define MRECURSION73( macro, data) MRECURSION72( macro, DEC_(data)) macro(data, 72)
+#define MRECURSION74( macro, data) MRECURSION73( macro, DEC_(data)) macro(data, 73)
+#define MRECURSION75( macro, data) MRECURSION74( macro, DEC_(data)) macro(data, 74)
+#define MRECURSION76( macro, data) MRECURSION75( macro, DEC_(data)) macro(data, 75)
+#define MRECURSION77( macro, data) MRECURSION76( macro, DEC_(data)) macro(data, 76)
+#define MRECURSION78( macro, data) MRECURSION77( macro, DEC_(data)) macro(data, 77)
+#define MRECURSION79( macro, data) MRECURSION78( macro, DEC_(data)) macro(data, 78)
+#define MRECURSION80( macro, data) MRECURSION79( macro, DEC_(data)) macro(data, 79)
+#define MRECURSION81( macro, data) MRECURSION80( macro, DEC_(data)) macro(data, 80)
+#define MRECURSION82( macro, data) MRECURSION81( macro, DEC_(data)) macro(data, 81)
+#define MRECURSION83( macro, data) MRECURSION82( macro, DEC_(data)) macro(data, 82)
+#define MRECURSION84( macro, data) MRECURSION83( macro, DEC_(data)) macro(data, 83)
+#define MRECURSION85( macro, data) MRECURSION84( macro, DEC_(data)) macro(data, 84)
+#define MRECURSION86( macro, data) MRECURSION85( macro, DEC_(data)) macro(data, 85)
+#define MRECURSION87( macro, data) MRECURSION86( macro, DEC_(data)) macro(data, 86)
+#define MRECURSION88( macro, data) MRECURSION87( macro, DEC_(data)) macro(data, 87)
+#define MRECURSION89( macro, data) MRECURSION88( macro, DEC_(data)) macro(data, 88)
+#define MRECURSION90( macro, data) MRECURSION89( macro, DEC_(data)) macro(data, 89)
+#define MRECURSION91( macro, data) MRECURSION90( macro, DEC_(data)) macro(data, 90)
+#define MRECURSION92( macro, data) MRECURSION91( macro, DEC_(data)) macro(data, 91)
+#define MRECURSION93( macro, data) MRECURSION92( macro, DEC_(data)) macro(data, 92)
+#define MRECURSION94( macro, data) MRECURSION93( macro, DEC_(data)) macro(data, 93)
+#define MRECURSION95( macro, data) MRECURSION94( macro, DEC_(data)) macro(data, 94)
+#define MRECURSION96( macro, data) MRECURSION95( macro, DEC_(data)) macro(data, 95)
+#define MRECURSION97( macro, data) MRECURSION96( macro, DEC_(data)) macro(data, 96)
+#define MRECURSION98( macro, data) MRECURSION97( macro, DEC_(data)) macro(data, 97)
+#define MRECURSION99( macro, data) MRECURSION98( macro, DEC_(data)) macro(data, 98)
+#define MRECURSION100(macro, data) MRECURSION99( macro, DEC_(data)) macro(data, 99)
+#define MRECURSION101(macro, data) MRECURSION100( macro, DEC_(data)) macro(data, 100)
+#define MRECURSION102(macro, data) MRECURSION101( macro, DEC_(data)) macro(data, 101)
+#define MRECURSION103(macro, data) MRECURSION102( macro, DEC_(data)) macro(data, 102)
+#define MRECURSION104(macro, data) MRECURSION103( macro, DEC_(data)) macro(data, 103)
+#define MRECURSION105(macro, data) MRECURSION104( macro, DEC_(data)) macro(data, 104)
+#define MRECURSION106(macro, data) MRECURSION105( macro, DEC_(data)) macro(data, 105)
+#define MRECURSION107(macro, data) MRECURSION106( macro, DEC_(data)) macro(data, 106)
+#define MRECURSION108(macro, data) MRECURSION107( macro, DEC_(data)) macro(data, 107)
+#define MRECURSION109(macro, data) MRECURSION108( macro, DEC_(data)) macro(data, 108)
+#define MRECURSION110(macro, data) MRECURSION109( macro, DEC_(data)) macro(data, 109)
+#define MRECURSION111(macro, data) MRECURSION110( macro, DEC_(data)) macro(data, 110)
+#define MRECURSION112(macro, data) MRECURSION111( macro, DEC_(data)) macro(data, 111)
+#define MRECURSION113(macro, data) MRECURSION112( macro, DEC_(data)) macro(data, 112)
+#define MRECURSION114(macro, data) MRECURSION113( macro, DEC_(data)) macro(data, 113)
+#define MRECURSION115(macro, data) MRECURSION114( macro, DEC_(data)) macro(data, 114)
+#define MRECURSION116(macro, data) MRECURSION115( macro, DEC_(data)) macro(data, 115)
+#define MRECURSION117(macro, data) MRECURSION116( macro, DEC_(data)) macro(data, 116)
+#define MRECURSION118(macro, data) MRECURSION117( macro, DEC_(data)) macro(data, 117)
+#define MRECURSION119(macro, data) MRECURSION118( macro, DEC_(data)) macro(data, 118)
+#define MRECURSION120(macro, data) MRECURSION119( macro, DEC_(data)) macro(data, 119)
+#define MRECURSION121(macro, data) MRECURSION120( macro, DEC_(data)) macro(data, 120)
+#define MRECURSION122(macro, data) MRECURSION121( macro, DEC_(data)) macro(data, 121)
+#define MRECURSION123(macro, data) MRECURSION122( macro, DEC_(data)) macro(data, 122)
+#define MRECURSION124(macro, data) MRECURSION123( macro, DEC_(data)) macro(data, 123)
+#define MRECURSION125(macro, data) MRECURSION124( macro, DEC_(data)) macro(data, 124)
+#define MRECURSION126(macro, data) MRECURSION125( macro, DEC_(data)) macro(data, 125)
+#define MRECURSION127(macro, data) MRECURSION126( macro, DEC_(data)) macro(data, 126)
+#define MRECURSION128(macro, data) MRECURSION127( macro, DEC_(data)) macro(data, 127)
+#define MRECURSION129(macro, data) MRECURSION128( macro, DEC_(data)) macro(data, 128)
+#define MRECURSION130(macro, data) MRECURSION129( macro, DEC_(data)) macro(data, 129)
+#define MRECURSION131(macro, data) MRECURSION130( macro, DEC_(data)) macro(data, 130)
+#define MRECURSION132(macro, data) MRECURSION131( macro, DEC_(data)) macro(data, 131)
+#define MRECURSION133(macro, data) MRECURSION132( macro, DEC_(data)) macro(data, 132)
+#define MRECURSION134(macro, data) MRECURSION133( macro, DEC_(data)) macro(data, 133)
+#define MRECURSION135(macro, data) MRECURSION134( macro, DEC_(data)) macro(data, 134)
+#define MRECURSION136(macro, data) MRECURSION135( macro, DEC_(data)) macro(data, 135)
+#define MRECURSION137(macro, data) MRECURSION136( macro, DEC_(data)) macro(data, 136)
+#define MRECURSION138(macro, data) MRECURSION137( macro, DEC_(data)) macro(data, 137)
+#define MRECURSION139(macro, data) MRECURSION138( macro, DEC_(data)) macro(data, 138)
+#define MRECURSION140(macro, data) MRECURSION139( macro, DEC_(data)) macro(data, 139)
+#define MRECURSION141(macro, data) MRECURSION140( macro, DEC_(data)) macro(data, 140)
+#define MRECURSION142(macro, data) MRECURSION141( macro, DEC_(data)) macro(data, 141)
+#define MRECURSION143(macro, data) MRECURSION142( macro, DEC_(data)) macro(data, 142)
+#define MRECURSION144(macro, data) MRECURSION143( macro, DEC_(data)) macro(data, 143)
+#define MRECURSION145(macro, data) MRECURSION144( macro, DEC_(data)) macro(data, 144)
+#define MRECURSION146(macro, data) MRECURSION145( macro, DEC_(data)) macro(data, 145)
+#define MRECURSION147(macro, data) MRECURSION146( macro, DEC_(data)) macro(data, 146)
+#define MRECURSION148(macro, data) MRECURSION147( macro, DEC_(data)) macro(data, 147)
+#define MRECURSION149(macro, data) MRECURSION148( macro, DEC_(data)) macro(data, 148)
+#define MRECURSION150(macro, data) MRECURSION149( macro, DEC_(data)) macro(data, 149)
+#define MRECURSION151(macro, data) MRECURSION150( macro, DEC_(data)) macro(data, 150)
+#define MRECURSION152(macro, data) MRECURSION151( macro, DEC_(data)) macro(data, 151)
+#define MRECURSION153(macro, data) MRECURSION152( macro, DEC_(data)) macro(data, 152)
+#define MRECURSION154(macro, data) MRECURSION153( macro, DEC_(data)) macro(data, 153)
+#define MRECURSION155(macro, data) MRECURSION154( macro, DEC_(data)) macro(data, 154)
+#define MRECURSION156(macro, data) MRECURSION155( macro, DEC_(data)) macro(data, 155)
+#define MRECURSION157(macro, data) MRECURSION156( macro, DEC_(data)) macro(data, 156)
+#define MRECURSION158(macro, data) MRECURSION157( macro, DEC_(data)) macro(data, 157)
+#define MRECURSION159(macro, data) MRECURSION158( macro, DEC_(data)) macro(data, 158)
+#define MRECURSION160(macro, data) MRECURSION159( macro, DEC_(data)) macro(data, 159)
+#define MRECURSION161(macro, data) MRECURSION160( macro, DEC_(data)) macro(data, 160)
+#define MRECURSION162(macro, data) MRECURSION161( macro, DEC_(data)) macro(data, 161)
+#define MRECURSION163(macro, data) MRECURSION162( macro, DEC_(data)) macro(data, 162)
+#define MRECURSION164(macro, data) MRECURSION163( macro, DEC_(data)) macro(data, 163)
+#define MRECURSION165(macro, data) MRECURSION164( macro, DEC_(data)) macro(data, 164)
+#define MRECURSION166(macro, data) MRECURSION165( macro, DEC_(data)) macro(data, 165)
+#define MRECURSION167(macro, data) MRECURSION166( macro, DEC_(data)) macro(data, 166)
+#define MRECURSION168(macro, data) MRECURSION167( macro, DEC_(data)) macro(data, 167)
+#define MRECURSION169(macro, data) MRECURSION168( macro, DEC_(data)) macro(data, 168)
+#define MRECURSION170(macro, data) MRECURSION169( macro, DEC_(data)) macro(data, 169)
+#define MRECURSION171(macro, data) MRECURSION170( macro, DEC_(data)) macro(data, 170)
+#define MRECURSION172(macro, data) MRECURSION171( macro, DEC_(data)) macro(data, 171)
+#define MRECURSION173(macro, data) MRECURSION172( macro, DEC_(data)) macro(data, 172)
+#define MRECURSION174(macro, data) MRECURSION173( macro, DEC_(data)) macro(data, 173)
+#define MRECURSION175(macro, data) MRECURSION174( macro, DEC_(data)) macro(data, 174)
+#define MRECURSION176(macro, data) MRECURSION175( macro, DEC_(data)) macro(data, 175)
+#define MRECURSION177(macro, data) MRECURSION176( macro, DEC_(data)) macro(data, 176)
+#define MRECURSION178(macro, data) MRECURSION177( macro, DEC_(data)) macro(data, 177)
+#define MRECURSION179(macro, data) MRECURSION178( macro, DEC_(data)) macro(data, 178)
+#define MRECURSION180(macro, data) MRECURSION179( macro, DEC_(data)) macro(data, 179)
+#define MRECURSION181(macro, data) MRECURSION180( macro, DEC_(data)) macro(data, 180)
+#define MRECURSION182(macro, data) MRECURSION181( macro, DEC_(data)) macro(data, 181)
+#define MRECURSION183(macro, data) MRECURSION182( macro, DEC_(data)) macro(data, 182)
+#define MRECURSION184(macro, data) MRECURSION183( macro, DEC_(data)) macro(data, 183)
+#define MRECURSION185(macro, data) MRECURSION184( macro, DEC_(data)) macro(data, 184)
+#define MRECURSION186(macro, data) MRECURSION185( macro, DEC_(data)) macro(data, 185)
+#define MRECURSION187(macro, data) MRECURSION186( macro, DEC_(data)) macro(data, 186)
+#define MRECURSION188(macro, data) MRECURSION187( macro, DEC_(data)) macro(data, 187)
+#define MRECURSION189(macro, data) MRECURSION188( macro, DEC_(data)) macro(data, 188)
+#define MRECURSION190(macro, data) MRECURSION189( macro, DEC_(data)) macro(data, 189)
+#define MRECURSION191(macro, data) MRECURSION190( macro, DEC_(data)) macro(data, 190)
+#define MRECURSION192(macro, data) MRECURSION191( macro, DEC_(data)) macro(data, 191)
+#define MRECURSION193(macro, data) MRECURSION192( macro, DEC_(data)) macro(data, 192)
+#define MRECURSION194(macro, data) MRECURSION193( macro, DEC_(data)) macro(data, 193)
+#define MRECURSION195(macro, data) MRECURSION194( macro, DEC_(data)) macro(data, 194)
+#define MRECURSION196(macro, data) MRECURSION195( macro, DEC_(data)) macro(data, 195)
+#define MRECURSION197(macro, data) MRECURSION196( macro, DEC_(data)) macro(data, 196)
+#define MRECURSION198(macro, data) MRECURSION197( macro, DEC_(data)) macro(data, 197)
+#define MRECURSION199(macro, data) MRECURSION198( macro, DEC_(data)) macro(data, 198)
+#define MRECURSION200(macro, data) MRECURSION199( macro, DEC_(data)) macro(data, 199)
+#define MRECURSION201(macro, data) MRECURSION200( macro, DEC_(data)) macro(data, 200)
+#define MRECURSION202(macro, data) MRECURSION201( macro, DEC_(data)) macro(data, 201)
+#define MRECURSION203(macro, data) MRECURSION202( macro, DEC_(data)) macro(data, 202)
+#define MRECURSION204(macro, data) MRECURSION203( macro, DEC_(data)) macro(data, 203)
+#define MRECURSION205(macro, data) MRECURSION204( macro, DEC_(data)) macro(data, 204)
+#define MRECURSION206(macro, data) MRECURSION205( macro, DEC_(data)) macro(data, 205)
+#define MRECURSION207(macro, data) MRECURSION206( macro, DEC_(data)) macro(data, 206)
+#define MRECURSION208(macro, data) MRECURSION207( macro, DEC_(data)) macro(data, 207)
+#define MRECURSION209(macro, data) MRECURSION208( macro, DEC_(data)) macro(data, 208)
+#define MRECURSION210(macro, data) MRECURSION209( macro, DEC_(data)) macro(data, 209)
+#define MRECURSION211(macro, data) MRECURSION210( macro, DEC_(data)) macro(data, 210)
+#define MRECURSION212(macro, data) MRECURSION211( macro, DEC_(data)) macro(data, 211)
+#define MRECURSION213(macro, data) MRECURSION212( macro, DEC_(data)) macro(data, 212)
+#define MRECURSION214(macro, data) MRECURSION213( macro, DEC_(data)) macro(data, 213)
+#define MRECURSION215(macro, data) MRECURSION214( macro, DEC_(data)) macro(data, 214)
+#define MRECURSION216(macro, data) MRECURSION215( macro, DEC_(data)) macro(data, 215)
+#define MRECURSION217(macro, data) MRECURSION216( macro, DEC_(data)) macro(data, 216)
+#define MRECURSION218(macro, data) MRECURSION217( macro, DEC_(data)) macro(data, 217)
+#define MRECURSION219(macro, data) MRECURSION218( macro, DEC_(data)) macro(data, 218)
+#define MRECURSION220(macro, data) MRECURSION219( macro, DEC_(data)) macro(data, 219)
+#define MRECURSION221(macro, data) MRECURSION220( macro, DEC_(data)) macro(data, 220)
+#define MRECURSION222(macro, data) MRECURSION221( macro, DEC_(data)) macro(data, 221)
+#define MRECURSION223(macro, data) MRECURSION222( macro, DEC_(data)) macro(data, 222)
+#define MRECURSION224(macro, data) MRECURSION223( macro, DEC_(data)) macro(data, 223)
+#define MRECURSION225(macro, data) MRECURSION224( macro, DEC_(data)) macro(data, 224)
+#define MRECURSION226(macro, data) MRECURSION225( macro, DEC_(data)) macro(data, 225)
+#define MRECURSION227(macro, data) MRECURSION226( macro, DEC_(data)) macro(data, 226)
+#define MRECURSION228(macro, data) MRECURSION227( macro, DEC_(data)) macro(data, 227)
+#define MRECURSION229(macro, data) MRECURSION228( macro, DEC_(data)) macro(data, 228)
+#define MRECURSION230(macro, data) MRECURSION229( macro, DEC_(data)) macro(data, 229)
+#define MRECURSION231(macro, data) MRECURSION230( macro, DEC_(data)) macro(data, 230)
+#define MRECURSION232(macro, data) MRECURSION231( macro, DEC_(data)) macro(data, 231)
+#define MRECURSION233(macro, data) MRECURSION232( macro, DEC_(data)) macro(data, 232)
+#define MRECURSION234(macro, data) MRECURSION233( macro, DEC_(data)) macro(data, 233)
+#define MRECURSION235(macro, data) MRECURSION234( macro, DEC_(data)) macro(data, 234)
+#define MRECURSION236(macro, data) MRECURSION235( macro, DEC_(data)) macro(data, 235)
+#define MRECURSION237(macro, data) MRECURSION236( macro, DEC_(data)) macro(data, 236)
+#define MRECURSION238(macro, data) MRECURSION237( macro, DEC_(data)) macro(data, 237)
+#define MRECURSION239(macro, data) MRECURSION238( macro, DEC_(data)) macro(data, 238)
+#define MRECURSION240(macro, data) MRECURSION239( macro, DEC_(data)) macro(data, 239)
+#define MRECURSION241(macro, data) MRECURSION240( macro, DEC_(data)) macro(data, 240)
+#define MRECURSION242(macro, data) MRECURSION241( macro, DEC_(data)) macro(data, 241)
+#define MRECURSION243(macro, data) MRECURSION242( macro, DEC_(data)) macro(data, 242)
+#define MRECURSION244(macro, data) MRECURSION243( macro, DEC_(data)) macro(data, 243)
+#define MRECURSION245(macro, data) MRECURSION244( macro, DEC_(data)) macro(data, 244)
+#define MRECURSION246(macro, data) MRECURSION245( macro, DEC_(data)) macro(data, 245)
+#define MRECURSION247(macro, data) MRECURSION246( macro, DEC_(data)) macro(data, 246)
+#define MRECURSION248(macro, data) MRECURSION247( macro, DEC_(data)) macro(data, 247)
+#define MRECURSION249(macro, data) MRECURSION248( macro, DEC_(data)) macro(data, 248)
+#define MRECURSION250(macro, data) MRECURSION249( macro, DEC_(data)) macro(data, 249)
+#define MRECURSION251(macro, data) MRECURSION250( macro, DEC_(data)) macro(data, 250)
+#define MRECURSION252(macro, data) MRECURSION251( macro, DEC_(data)) macro(data, 251)
+#define MRECURSION253(macro, data) MRECURSION252( macro, DEC_(data)) macro(data, 252)
+#define MRECURSION254(macro, data) MRECURSION253( macro, DEC_(data)) macro(data, 253)
+#define MRECURSION255(macro, data) MRECURSION254( macro, DEC_(data)) macro(data, 254)
+#define MRECURSION256(macro, data) MRECURSION255( macro, DEC_(data)) macro(data, 255)
+
+/** @} */
+
+#endif /* _MRECURSION_H_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/mrepeat.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/mrepeat.h
new file mode 100755
index 0000000000000000000000000000000000000000..127ad9e8d29bac3c405dc790c567160552159a5e
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/mrepeat.h
@@ -0,0 +1,335 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+/**
+ * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+/** Maximal number of repetitions supported by MREPEAT. */
+#define MREPEAT_LIMIT 256
+
+/** \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count The number of repetitious calls to macro. Valid values
+ * range from 0 to MREPEAT_LIMIT.
+ * \param[in] macro A binary operation of the form macro(n, data). This macro
+ * is expanded by MREPEAT with the current repetition number
+ * and the auxiliary data argument.
+ * \param[in] data Auxiliary data passed to macro.
+ *
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
+ */
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)
+
+#define MREPEAT0( macro, data)
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
+
+/** @} */
+
+#endif /* _MREPEAT_H_ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/preprocessor.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/preprocessor.h
new file mode 100755
index 0000000000000000000000000000000000000000..6442651a3a39a964051dd4ea3f204cd6c6aa4fb1
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/preprocessor.h
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor utils.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _PREPROCESSOR_H_
+#define _PREPROCESSOR_H_
+
+#include "tpaste.h"
+#include "stringz.h"
+#include "mrepeat.h"
+#include "mrecursion.h"
+
+#endif // _PREPROCESSOR_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/stringz.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/stringz.h
new file mode 100755
index 0000000000000000000000000000000000000000..747d6ac74a0c8b3f98cc16b4b6259c0c82042fad
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/stringz.h
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+/**
+ * \defgroup group_sam0_utils_stringz Preprocessor - Stringize
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the
+ * token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x) #x
+
+/** \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x) STRINGZ(x)
+
+/** @} */
+
+#endif // _STRINGZ_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/tpaste.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/tpaste.h
new file mode 100755
index 0000000000000000000000000000000000000000..f5fddbfa2a5f438f4831a7b11fb94cf124e57af5
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/preprocessor/tpaste.h
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+/**
+ * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ *
+ * @{ */
+#define TPASTE2( a, b) a##b
+#define TPASTE3( a, b, c) a##b##c
+#define TPASTE4( a, b, c, d) a##b##c##d
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
+/** @} */
+
+/** \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ *
+ * @{ */
+#define ATPASTE2( a, b) TPASTE2( a, b)
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
+/** @} */
+
+/** @} */
+
+#endif // _TPASTE_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/status_codes.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/status_codes.h
new file mode 100755
index 0000000000000000000000000000000000000000..0df6708f512166333ea6c9fedad17c3b2e9fdf8f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/status_codes.h
@@ -0,0 +1,155 @@
+/**
+ * \file
+ *
+ * \brief Status code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef STATUS_CODES_H_INCLUDED
+#define STATUS_CODES_H_INCLUDED
+
+#include <stdint.h>
+
+/**
+ * \defgroup group_sam0_utils_status_codes Status Codes
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** Mask to retrieve the error category of a status code. */
+#define STATUS_CATEGORY_MASK 0xF0
+
+/** Mask to retrieve the error code within the category of a status code. */
+#define STATUS_ERROR_MASK 0x0F
+
+/** Status code error categories. */
+enum status_categories {
+ STATUS_CATEGORY_OK = 0x00,
+ STATUS_CATEGORY_COMMON = 0x10,
+ STATUS_CATEGORY_ANALOG = 0x30,
+ STATUS_CATEGORY_COM = 0x40,
+ STATUS_CATEGORY_IO = 0x50,
+};
+
+/**
+ * Status code that may be returned by shell commands and protocol
+ * implementations.
+ *
+ * \note Any change to these status codes and the corresponding
+ * message strings is strictly forbidden. New codes can be added,
+ * however, but make sure that any message string tables are updated
+ * at the same time.
+ */
+enum status_code {
+ STATUS_OK = STATUS_CATEGORY_OK | 0x00,
+ STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01,
+ STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02,
+ STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04,
+ STATUS_BUSY = STATUS_CATEGORY_OK | 0x05,
+ STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06,
+
+ STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00,
+ STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01,
+ STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02,
+ STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03,
+ STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04,
+ STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05,
+ STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06,
+ STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07,
+ STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08,
+ STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A,
+ STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B,
+ STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c,
+ STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d,
+ STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e,
+ STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f,
+
+ STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
+ STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
+
+ STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00,
+ STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01,
+ STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02,
+
+ STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00,
+};
+typedef enum status_code status_code_genare_t;
+
+/**
+ Status codes used by MAC stack.
+ */
+enum status_code_wireless {
+ //STATUS_OK = 0, //!< Success
+ ERR_IO_ERROR = -1, //!< I/O error
+ ERR_FLUSHED = -2, //!< Request flushed from queue
+ ERR_TIMEOUT = -3, //!< Operation timed out
+ ERR_BAD_DATA = -4, //!< Data integrity check failed
+ ERR_PROTOCOL = -5, //!< Protocol error
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
+ ERR_NO_MEMORY = -7, //!< Insufficient memory
+ ERR_INVALID_ARG = -8, //!< Invalid argument
+ ERR_BAD_ADDRESS = -9, //!< Bad address
+ ERR_BUSY = -10, //!< Resource is busy
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized
+ ERR_NO_TIMER = -12, //!< No timer available
+ ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
+ ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
+
+ /**
+ * \brief Operation in progress
+ *
+ * This status code is for driver-internal use when an operation
+ * is currently being performed.
+ *
+ * \note Drivers should never return this status code to any
+ * callers. It is strictly for internal use.
+ */
+ OPERATION_IN_PROGRESS = -128,
+};
+
+typedef enum status_code_wireless status_code_t;
+
+/** @} */
+
+#endif /* STATUS_CODES_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/syscalls/gcc/syscalls.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/syscalls/gcc/syscalls.c
new file mode 100755
index 0000000000000000000000000000000000000000..aa5adedafc0d326a76f83163658793f45ef091ce
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/sam0/utils/syscalls/gcc/syscalls.c
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Syscalls for SAM0 (GCC).
+ *
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef errno
+extern int errno;
+extern int _end;
+
+extern caddr_t _sbrk(int incr);
+extern int link(char *old, char *new);
+extern int _close(int file);
+extern int _fstat(int file, struct stat *st);
+extern int _isatty(int file);
+extern int _lseek(int file, int ptr, int dir);
+extern void _exit(int status);
+extern void _kill(int pid, int sig);
+extern int _getpid(void);
+
+extern caddr_t _sbrk(int incr)
+{
+ static unsigned char *heap = NULL;
+ unsigned char *prev_heap;
+
+ if (heap == NULL) {
+ heap = (unsigned char *)&_end;
+ }
+ prev_heap = heap;
+
+ heap += incr;
+
+ return (caddr_t) prev_heap;
+}
+
+extern int link(char *old, char *new)
+{
+ return -1;
+}
+
+extern int _close(int file)
+{
+ return -1;
+}
+
+extern int _fstat(int file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+
+ return 0;
+}
+
+extern int _isatty(int file)
+{
+ return 1;
+}
+
+extern int _lseek(int file, int ptr, int dir)
+{
+ return 0;
+}
+
+extern void _exit(int status)
+{
+ printf("Exiting with status %d.\n", status);
+
+ for (;;);
+}
+
+extern void _kill(int pid, int sig)
+{
+ return;
+}
+
+extern int _getpid(void)
+{
+ return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100755
index 0000000000000000000000000000000000000000..c8feab483c7aee07b235b93666803151e052e8c7
Binary files /dev/null and b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf differ
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/arm_math.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/arm_math.h
new file mode 100755
index 0000000000000000000000000000000000000000..38713fdc848e81e915b126cb0ae8f90735add6d9
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/arm_math.h
@@ -0,0 +1,7059 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 15. July 2011
+ * $Revision: V1.0.10
+ *
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ *
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *
+ * Version 1.0.10 2011/7/15
+ * Big Endian support added and Merged M0 and M3/M4 Source code.
+ *
+ * Version 1.0.3 2010/11/29
+ * Re-organized the CMSIS folders and updated documentation.
+ *
+ * Version 1.0.2 2010/11/11
+ * Documentation updated.
+ *
+ * Version 1.0.1 2010/10/05
+ * Production release and review comments incorporated.
+ *
+ * Version 1.0.0 2010/09/20
+ * Production release and review comments incorporated.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * <b>Introduction</b>
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of modules each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * <b>Processor Support</b>
+ *
+ * The library is completely written in C and is fully CMSIS compliant.
+ * High performance is achieved through maximum use of Cortex-M4 intrinsics.
+ *
+ * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
+ * with the DSP intrinsics being emulated through software.
+ *
+ *
+ * <b>Toolchain Support</b>
+ *
+ * The library has been developed and tested with MDK-ARM version 4.21.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * <b>Using the Library</b>
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code>arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 depending on the target processor in the application.
+ *
+ * <b>Examples</b>
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * <b>Building the Library</b>
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * <b>ARM_MATH_CMx:</b>
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.
+ *
+ * <b>ARM_MATH_BIG_ENDIAN:</b>
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * <b>ARM_MATH_MATRIX_CHECK:</b>
+ * Define macro for checking on the input and output sizes of matrices
+ *
+ * <b>ARM_MATH_ROUNDING:</b>
+ * Define macro for rounding on support functions
+ *
+ * <b>__FPU_PRESENT:</b>
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * <b>Copyright Notice</b>
+ *
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#include "compiler.h"
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+ #include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#define PI 3.14159265358979f
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#define __SIMD32(addr) (*(int32_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
+/* No need to redefine __CLZ */
+#endif
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
+
+ __STATIC_INLINE uint32_t __CLZ(q31_t data);
+
+
+ __STATIC_INLINE uint32_t __CLZ(q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return(count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+ */
+
+ __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+ */
+ __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0)
+
+ __STATIC_INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (char) x;
+ s = (char) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (char) x;
+ s = (char) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t)(((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t)(((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ __STATIC_INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+
+
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t *pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t *pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t *pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ #ifdef ARM_MATH_CM0
+ q15_t A1;
+ q15_t A2;
+ #else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+ #endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /*----------------------------------------------------------------------
+ * Internal functions prototypes FFT function
+ ----------------------------------------------------------------------*/
+
+ /**
+ * @brief Core function for the floating-point CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to the twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the floating-point CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen value of 1/fftLen.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftSize length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+ * @param[in] *pBitRevTab points to the bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_f32(
+ float32_t *pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t *pBitRevTab);
+
+ /**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q31(
+ q31_t *pSrc,
+ uint32_t fftLen,
+ q31_t *pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t *pBitRevTab);
+
+ /**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q15(
+ q15_t *pSrc16,
+ uint32_t fftLen,
+ q15_t *pCoef16,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q15(
+ q15_t *pSrc16,
+ uint32_t fftLen,
+ q15_t *pCoef16,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t *pBitRevTab);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ /**
+ * @brief Processing function for the Q15 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q15 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q31 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the floating-point RFFT/RIFFT.
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+ */
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t *pkCoeffs,
+ float32_t *pvCoeffs,
+ float32_t *pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t *pkCoeffs,
+ q31_t *pvCoeffs,
+ q31_t *pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t *pkCoeffs,
+ q15_t *pvCoeffs,
+ q15_t *pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t *pCoeffs,
+ q31_t *pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t *pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t *pSinVal,
+ float32_t *pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t *pSinVal,
+ q31_t *pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+ /* Implementation of PID controller */
+
+ #ifdef ARM_MATH_CM0
+
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0 )* in ;
+
+ #else
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+ #endif
+
+ #ifdef ARM_MATH_CM0
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0] ;
+ acc += (q31_t) S->A2 * S->state[1] ;
+
+ #else
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
+
+ #endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ */
+
+
+ __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (x - S->x1) / xSpacing;
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if(i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues-1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i +1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ __STATIC_INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
+ q31_t x, uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (nValues - 1))
+ {
+ return(pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return(pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ __STATIC_INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (nValues - 1))
+ {
+ return(pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return(pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ __STATIC_INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+
+ if(index >= (nValues - 1))
+ {
+ return(pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return(pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+
+ __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in, float32_t *pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+ #elif (__FPU_USED == 1) && defined ( __TMS_740 )
+ *pOut = __builtin_sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in, q31_t *pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in, q15_t *pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex-1) * S->numCols ;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex-1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h
new file mode 100755
index 0000000000000000000000000000000000000000..aa20e6879f203e09efdeefe12d96f3dfb07901c0
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,778 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h
new file mode 100755
index 0000000000000000000000000000000000000000..902f4f12f9df3955d76ea1814d2b30fedc5a58c0
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.00
+ * @date 19. January 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h
new file mode 100755
index 0000000000000000000000000000000000000000..0e6cf3d41f11aaa69416f5e178009fd431c404ec
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.00
+ * @date 07. February 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Lib/GCC/.gitignore b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Lib/GCC/.gitignore
new file mode 100755
index 0000000000000000000000000000000000000000..5b6ae6395984b0b2060811b733cfc20d266f3552
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Lib/GCC/.gitignore
@@ -0,0 +1,4 @@
+# Libraries
+
+!*.a
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
new file mode 100755
index 0000000000000000000000000000000000000000..f44336f84b71e562b5a527e56b0b88747173474f
Binary files /dev/null and b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a differ
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/README.txt b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..41cede7b8337e5b4e8bc592e3f3f74fb0778a38f
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/ASF/thirdparty/CMSIS/README.txt
@@ -0,0 +1,37 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011 ARM Limited. All rights reserved.
+*
+* Date: 11 October 2011
+* Revision: V3.00
+*
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title: Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation - Contains CMSIS documentation.
+
+DSP_Lib - MDK project files, Examples and source files etc.. to build the
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib - CMSIS DSP Libraries.
+
+RTOS - CMSIS RTOS API template header file.
+
+SVD - CMSIS SVD Schema files and Conversion Utility.
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/asf.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/asf.h
new file mode 100755
index 0000000000000000000000000000000000000000..ebced37f7deec152e3eb4c3ad0e6ca046bf33519
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/asf.h
@@ -0,0 +1,122 @@
+/**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ASF_H
+#define ASF_H
+
+/*
+ * This file includes all API header files for the selected drivers from ASF.
+ * Note: There might be duplicate includes required by more than one driver.
+ *
+ * The file is automatically generated and will be re-written when
+ * running the ASF driver selector tool. Any changes will be discarded.
+ */
+
+// From module: Common SAM0 compiler driver
+#include <compiler.h>
+#include <status_codes.h>
+
+// From module: EXTINT - External Interrupt (Callback APIs)
+//#include <extint.h>
+//#include <extint_callback.h>
+
+// From module: Generic board support
+#include <board.h>
+
+// From module: Interrupt management - SAM implementation
+#include <interrupt.h>
+
+// From module: NVM - Non-Volatile Memory
+//#include <nvm.h>
+
+// From module: PORT - GPIO Pin Control
+#include <port.h>
+
+// From module: Part identification macros
+#include <parts.h>
+
+// From module: RTC - Real Time Counter in Count Mode (Callback APIs)
+#include <rtc_count.h>
+#include <rtc_count_interrupt.h>
+
+// From module: SAM D21/R21 USB Dual role interface
+#include <usb_dual.h>
+
+// From module: SERCOM
+#include <sercom.h>
+#include <sercom_interrupt.h>
+
+// From module: SERCOM USART - Serial Communications (Polled APIs)
+#include <usart.h>
+
+// From module: SYSTEM - Clock Management for SAMD21
+#include <clock.h>
+#include <gclk.h>
+
+// From module: SYSTEM - Core System Driver
+#include <system.h>
+
+// From module: SYSTEM - I/O Pin Multiplexer
+#include <pinmux.h>
+
+// From module: SYSTEM - Interrupt Driver
+#include <system_interrupt.h>
+
+// From module: Sleep manager - SAMD implementation
+#include <samd/sleepmgr.h>
+#include <sleepmgr.h>
+
+// From module: USB - Universal Serial Bus
+#include <usb.h>
+
+// From module: USB CDC Protocol
+#include <usb_protocol_cdc.h>
+
+// From module: USB Device CDC (Single Interface Device)
+#include <udi_cdc.h>
+
+// From module: USB Device Stack Core (Common API)
+#include <udc.h>
+#include <udd.h>
+
+#endif // ASF_H
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/command.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/command.h
new file mode 100755
index 0000000000000000000000000000000000000000..e6942be86ec12adf41f8201fdec58b463607d7a6
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/command.h
@@ -0,0 +1,121 @@
+#ifndef COMMAND_H_
+#define COMMAND_H_
+
+//**** ATMEL AVR - A P P L I C A T I O N N O T E ************************
+//*
+//* Title: AVR068 - STK500 Communication Protocol
+//* Filename: command.h
+//* Version: 1.0
+//* Last updated: 31.01.2005
+//*
+//* Support E-mail: avr@atmel.com
+//*
+//**************************************************************************
+
+// *****************[ STK message constants ]***************************
+
+#define MESSAGE_START 0x1B //= ESC = 27 decimal
+#define TOKEN 0x0E
+
+// *****************[ STK general command constants ]**************************
+
+#define CMD_SIGN_ON 0x01
+#define CMD_SET_PARAMETER 0x02
+#define CMD_GET_PARAMETER 0x03
+#define CMD_SET_DEVICE_PARAMETERS 0x04
+#define CMD_OSCCAL 0x05
+#define CMD_LOAD_ADDRESS 0x06
+#define CMD_FIRMWARE_UPGRADE 0x07
+
+
+// *****************[ STK ISP command constants ]******************************
+
+#define CMD_ENTER_PROGMODE_ISP 0x10
+#define CMD_LEAVE_PROGMODE_ISP 0x11
+#define CMD_CHIP_ERASE_ISP 0x12
+#define CMD_PROGRAM_FLASH_ISP 0x13
+#define CMD_READ_FLASH_ISP 0x14
+#define CMD_PROGRAM_EEPROM_ISP 0x15
+#define CMD_READ_EEPROM_ISP 0x16
+#define CMD_PROGRAM_FUSE_ISP 0x17
+#define CMD_READ_FUSE_ISP 0x18
+#define CMD_PROGRAM_LOCK_ISP 0x19
+#define CMD_READ_LOCK_ISP 0x1A
+#define CMD_READ_SIGNATURE_ISP 0x1B
+#define CMD_READ_OSCCAL_ISP 0x1C
+#define CMD_SPI_MULTI 0x1D
+
+// *****************[ STK PP command constants ]*******************************
+
+#define CMD_ENTER_PROGMODE_PP 0x20
+#define CMD_LEAVE_PROGMODE_PP 0x21
+#define CMD_CHIP_ERASE_PP 0x22
+#define CMD_PROGRAM_FLASH_PP 0x23
+#define CMD_READ_FLASH_PP 0x24
+#define CMD_PROGRAM_EEPROM_PP 0x25
+#define CMD_READ_EEPROM_PP 0x26
+#define CMD_PROGRAM_FUSE_PP 0x27
+#define CMD_READ_FUSE_PP 0x28
+#define CMD_PROGRAM_LOCK_PP 0x29
+#define CMD_READ_LOCK_PP 0x2A
+#define CMD_READ_SIGNATURE_PP 0x2B
+#define CMD_READ_OSCCAL_PP 0x2C
+
+#define CMD_SET_CONTROL_STACK 0x2D
+
+// *****************[ STK HVSP command constants ]*****************************
+
+#define CMD_ENTER_PROGMODE_HVSP 0x30
+#define CMD_LEAVE_PROGMODE_HVSP 0x31
+#define CMD_CHIP_ERASE_HVSP 0x32
+#define CMD_PROGRAM_FLASH_HVSP ` 0x33
+#define CMD_READ_FLASH_HVSP 0x34
+#define CMD_PROGRAM_EEPROM_HVSP 0x35
+#define CMD_READ_EEPROM_HVSP 0x36
+#define CMD_PROGRAM_FUSE_HVSP 0x37
+#define CMD_READ_FUSE_HVSP 0x38
+#define CMD_PROGRAM_LOCK_HVSP 0x39
+#define CMD_READ_LOCK_HVSP 0x3A
+#define CMD_READ_SIGNATURE_HVSP 0x3B
+#define CMD_READ_OSCCAL_HVSP 0x3C
+
+// *****************[ STK status constants ]***************************
+
+// Success
+#define STATUS_CMD_OK 0x00
+
+// Warnings
+#define STATUS_CMD_TOUT 0x80
+#define STATUS_RDY_BSY_TOUT 0x81
+#define STATUS_SET_PARAM_MISSING 0x82
+
+// Errors
+#define STATUS_CMD_FAILED 0xC0
+#define STATUS_CKSUM_ERROR 0xC1
+#define STATUS_CMD_UNKNOWN 0xC9
+
+// *****************[ STK parameter constants ]***************************
+#define PARAM_BUILD_NUMBER_LOW 0x80
+#define PARAM_BUILD_NUMBER_HIGH 0x81
+#define PARAM_HW_VER 0x90
+#define PARAM_SW_MAJOR 0x91
+#define PARAM_SW_MINOR 0x92
+#define PARAM_VTARGET 0x94
+#define PARAM_VADJUST 0x95
+#define PARAM_OSC_PSCALE 0x96
+#define PARAM_OSC_CMATCH 0x97
+#define PARAM_SCK_DURATION 0x98
+#define PARAM_TOPCARD_DETECT 0x9A
+#define PARAM_STATUS 0x9C
+#define PARAM_DATA 0x9D
+#define PARAM_RESET_POLARITY 0x9E
+#define PARAM_CONTROLLER_INIT 0x9F
+
+// *****************[ STK answer constants ]***************************
+
+#define ANSWER_CKSUM_ERROR 0xB0
+
+
+
+
+#endif /* COMMAND_H_ */
\ No newline at end of file
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_board.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_board.h
new file mode 100755
index 0000000000000000000000000000000000000000..1766a3ce3ff2bc4a43e5a41ea63ff333608b82c1
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_board.h
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board configuration.
+ *
+ * Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef CONF_BOARD_H_INCLUDED
+#define CONF_BOARD_H_INCLUDED
+
+#endif /* CONF_BOARD_H_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_clocks.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_clocks.h
new file mode 100755
index 0000000000000000000000000000000000000000..99e72b41a74fc13fbcad2cb067d76afb6472ab90
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_clocks.h
@@ -0,0 +1,183 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Clock configuration
+ *
+ * Copyright (C) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+# define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT true
+# define CONF_CLOCK_FLASH_WAIT_STATES 2
+# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
+# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
+# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
+# define CONF_CLOCK_OSC8M_ON_DEMAND true
+# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+# define CONF_CLOCK_XOSC_ENABLE false
+# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
+# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
+# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
+# define CONF_CLOCK_XOSC_ON_DEMAND true
+# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+# define CONF_CLOCK_XOSC32K_ENABLE false
+# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
+# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false
+# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
+# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
+# define CONF_CLOCK_XOSC32K_ON_DEMAND true
+# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+# define CONF_CLOCK_OSC32K_ENABLE false
+# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
+# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
+# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
+# define CONF_CLOCK_OSC32K_ON_DEMAND true
+# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+# define CONF_CLOCK_DFLL_ENABLE true
+# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY
+# define CONF_CLOCK_DFLL_ON_DEMAND true
+
+/* DFLL open loop mode configuration */
+# define CONF_CLOCK_DFLL_COARSE_VALUE (0x1f / 4)
+# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)
+
+/* DFLL closed loop mode configuration */
+# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
+# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 6
+# define CONF_CLOCK_DFLL_QUICK_LOCK true
+# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
+# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
+# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
+# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)
+# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)
+
+/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
+# define CONF_CLOCK_DPLL_ENABLE false
+# define CONF_CLOCK_DPLL_ON_DEMAND true
+# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false
+# define CONF_CLOCK_DPLL_LOCK_BYPASS false
+# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
+# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false
+
+# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_NO_TIMEOUT
+# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0
+# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
+# define CONF_CLOCK_DPLL_REFEREMCE_DIVIDER 1
+# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+# define CONF_CLOCK_CONFIGURE_GCLK true
+
+/* Configure GCLK generator 0 (Main Clock) */
+# define CONF_CLOCK_GCLK_0_ENABLE true
+# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true
+# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL
+# define CONF_CLOCK_GCLK_0_PRESCALER 1
+# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 1 */
+# define CONF_CLOCK_GCLK_1_ENABLE false
+# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
+# define CONF_CLOCK_GCLK_1_PRESCALER 1
+# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 2 (RTC) */
+# define CONF_CLOCK_GCLK_2_ENABLE true
+# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_ULP32K
+# define CONF_CLOCK_GCLK_2_PRESCALER 32
+# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 3 */
+# define CONF_CLOCK_GCLK_3_ENABLE false
+# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
+# define CONF_CLOCK_GCLK_3_PRESCALER 1
+# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 4 */
+# define CONF_CLOCK_GCLK_4_ENABLE false
+# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
+# define CONF_CLOCK_GCLK_4_PRESCALER 1
+# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 5 */
+# define CONF_CLOCK_GCLK_5_ENABLE false
+# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
+# define CONF_CLOCK_GCLK_5_PRESCALER 1
+# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 6 */
+# define CONF_CLOCK_GCLK_6_ENABLE false
+# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
+# define CONF_CLOCK_GCLK_6_PRESCALER 1
+# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
+
+/* Configure GCLK generator 7 */
+# define CONF_CLOCK_GCLK_7_ENABLE false
+# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
+# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
+# define CONF_CLOCK_GCLK_7_PRESCALER 1
+# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_extint.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_extint.h
new file mode 100755
index 0000000000000000000000000000000000000000..0f5b08a9bb9e00337e75e171d349baaf0992c403
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_extint.h
@@ -0,0 +1,48 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver Configuration Header
+ *
+ * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef CONF_EXTINT_H_INCLUDED
+#define CONF_EXTINT_H_INCLUDED
+
+# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
+
+#endif
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_sleepmgr.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_sleepmgr.h
new file mode 100755
index 0000000000000000000000000000000000000000..38a889b754636d00146158616049e0439fbafa2a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_sleepmgr.h
@@ -0,0 +1,49 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef CONF_SLEEPMGR_INCLUDED
+#define CONF_SLEEPMGR_INCLUDED
+
+// Sleep manager options
+#define CONFIG_SLEEPMGR_ENABLE
+
+#endif /* CONF_SLEEPMGR_INCLUDED */
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_usb.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_usb.h
new file mode 100755
index 0000000000000000000000000000000000000000..c4889b83b429b0583d08a93e35e48528aae5768a
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/config/conf_usb.h
@@ -0,0 +1,202 @@
+/**
+ * \file
+ *
+ * \brief USB configuration file for CDC application
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _CONF_USB_H_
+#define _CONF_USB_H_
+
+#include "compiler.h"
+#include "board.h"
+
+/**
+ * USB Device Configuration
+ * @{
+ */
+
+ // Arduino srl USB VID Definition.
+ #define USB_VENDOR_ID 0x2A03
+ #define USB_VENDOR_DESCRIPTOR "Arduino srl (www.arduino.org)"
+
+ // Arduiino Zero Pro USB PID
+ //#define USB_PRODUCT_ID 0x004D
+ //#define USB_PRODUCT_NAME "Arduino Zero PRO"
+
+ // Arduino M0 Pro USB PID
+ //#define USB_PRODUCT_ID 0x004E // Arduino M0 PID
+ //#define USB_PRODUCT_NAME "Arduino M0 PRO"
+
+ // Arduino M0 Pro USB PID
+ //#define USB_PRODUCT_ID 0x004F // Arduino M0 PRO PID
+ //#define USB_PRODUCT_NAME "Arduino M0 PRO"
+
+ // Arduino Tian USB PID
+ #define USB_PRODUCT_ID 0x0052 // Arduino Tian PID
+ #define USB_PRODUCT_NAME "Arduino Tian"
+
+ // Arduino M0s USB PID
+ //#define USB_PRODUCT_ID 0x0053 // Arduino M0s PID
+ //#define USB_PRODUCT_NAME "Arduino M0s"
+
+
+
+//! Device definition (mandatory)
+#define USB_DEVICE_VENDOR_ID USB_VENDOR_ID
+#if BOARD == UC3B_BOARD_CONTROLLER
+# define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_UC3_CDC_DEBUG
+#else
+# define USB_DEVICE_PRODUCT_ID USB_PRODUCT_ID
+
+
+#endif
+#define USB_DEVICE_MAJOR_VERSION 1
+#define USB_DEVICE_MINOR_VERSION 0
+#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA)
+#define USB_DEVICE_ATTR \
+ (USB_CONFIG_ATTR_SELF_POWERED)
+// (USB_CONFIG_ATTR_BUS_POWERED)
+// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED)
+// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED)
+
+//! USB Device string definitions (Optional)
+#define USB_DEVICE_MANUFACTURE_NAME USB_VENDOR_DESCRIPTOR
+#define USB_DEVICE_PRODUCT_NAME USB_PRODUCT_NAME
+
+// Serial Number Definition (needed for Drivers Signature)
+//#define USB_DEVICE_SERIAL_NAME "004D" // Arduino Zero PRO USB Serial Number
+//#define USB_DEVICE_SERIAL_NAME "004F" // Arduino M0 PRO USB Serial Number
+//#define USB_DEVICE_SERIAL_NAME "004E" // Arduino M0 USB Serial Number
+//#define USB_DEVICE_SERIAL_NAME "0052" // Arduino Tian Serial Number
+#define USB_DEVICE_SERIAL_NAME "0053" // Arduino M0s Serial Number
+
+
+
+
+
+/**
+ * Device speeds support
+ * Low speed not supported by CDC
+ * @{
+ */
+//! To authorize the High speed
+#if (UC3A3||UC3A4)
+#define USB_DEVICE_HS_SUPPORT
+#elif (SAM3XA||SAM3U)
+#define USB_DEVICE_HS_SUPPORT
+#endif
+//@}
+
+
+/**
+ * USB Device Callbacks definitions (Optional)
+ * @{
+ */
+#define UDC_VBUS_EVENT(b_vbus_high)
+#define UDC_SOF_EVENT()
+#define UDC_SUSPEND_EVENT()
+#define UDC_RESUME_EVENT()
+//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature
+// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable()
+// extern void user_callback_remotewakeup_enable(void);
+// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable()
+// extern void user_callback_remotewakeup_disable(void);
+#ifdef USB_DEVICE_LPM_SUPPORT
+#define UDC_SUSPEND_LPM_EVENT()
+#define UDC_REMOTEWAKEUP_LPM_ENABLE()
+#define UDC_REMOTEWAKEUP_LPM_DISABLE()
+#endif
+//! When a extra string descriptor must be supported
+//! other than manufacturer, product and serial string
+// #define UDC_GET_EXTRA_STRING()
+//@}
+
+//@}
+
+
+/**
+ * USB Interface Configuration
+ * @{
+ */
+/**
+ * Configuration of CDC interface
+ * @{
+ */
+
+//! Define two USB communication ports
+#define UDI_CDC_PORT_NB 1
+
+//! Interface callback definition
+#define UDI_CDC_ENABLE_EXT(port) true
+#define UDI_CDC_DISABLE_EXT(port)
+#define UDI_CDC_RX_NOTIFY(port)
+#define UDI_CDC_TX_EMPTY_NOTIFY(port)
+#define UDI_CDC_SET_CODING_EXT(port,cfg) main_cdc_config(port,cfg)
+#define UDI_CDC_SET_DTR_EXT(port,set)
+#define UDI_CDC_SET_RTS_EXT(port,set)
+
+//! Define it when the transfer CDC Device to Host is a low rate (<512000 bauds)
+//! to reduce CDC buffers size
+//#define UDI_CDC_LOW_RATE
+
+//! Default configuration of communication port
+#if BOARD == UC3B_BOARD_CONTROLLER
+#define UDI_CDC_DEFAULT_RATE 57600
+#else
+#define UDI_CDC_DEFAULT_RATE 115200
+#endif
+#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
+#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
+#define UDI_CDC_DEFAULT_DATABITS 8
+//@}
+//@}
+
+
+/**
+ * USB Device Driver Configuration
+ * @{
+ */
+//@}
+
+//! The includes of classes and other headers must be done at the end of this file to avoid compile error
+#include "udi_cdc_conf.h"
+#include "main.h"
+
+#endif // _CONF_USB_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/main.c b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/main.c
new file mode 100755
index 0000000000000000000000000000000000000000..15a947dc9b4b6a9532915e886d573acbb3b269f1
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/main.c
@@ -0,0 +1,280 @@
+/*---------- GNU PUBLIC LICENZE V3 ----------
+*
+* Copyright Arduino srl (c) 2015
+*
+* This file is part of Bootloader_D21.
+*
+* Bootloader_D21 is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License.
+*
+* bootloader_D21 is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with Bootloader_D21. If not, see <http://www.gnu.org/licenses/>.
+*
+*/
+
+/*
+ * Include header files for all drivers that have been imported from
+ * Atmel Software Framework (ASF).
+ */
+
+#include <asf.h>
+#include <usart_setup.h>
+
+static inline bool nvm_is_ready(void)
+{
+ /* Get a pointer to the module hardware instance */
+ Nvmctrl *const nvm_module = NVMCTRL;
+
+ return nvm_module->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+}
+#include <stk500v2.h>
+enum nvm_cache_readmode {
+ /** The NVM Controller (cache system) does not insert wait states on
+ * a cache miss. Gives the best system performance.
+ */
+ NVM_CACHE_READMODE_NO_MISS_PENALTY,
+ /** Reduces power consumption of the cache system, but inserts a
+ * wait state each time there is a cache miss
+ */
+ NVM_CACHE_READMODE_LOW_POWER,
+ /** The cache system ensures that a cache hit or miss takes the same
+ * amount of time, determined by the number of programmed flash
+ * wait states.
+ */
+ NVM_CACHE_READMODE_DETERMINISTIC,
+};
+
+enum nvm_sleep_power_mode {
+ /** NVM controller exits low power mode on first access after sleep. */
+ NVM_SLEEP_POWER_MODE_WAKEONACCESS = NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val,
+ /** NVM controller exits low power mode when the device exits sleep mode. */
+ NVM_SLEEP_POWER_MODE_WAKEUPINSTANT = NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val,
+ /** Power reduction mode in the NVM controller disabled. */
+ NVM_SLEEP_POWER_MODE_ALWAYS_AWAKE = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val,
+};
+
+
+void configure_nvm(void)
+{
+ /* Turn on the digital interface clock */
+ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_NVMCTRL);
+
+ /* Clear error flags */
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+
+ /* Check if the module is busy */
+ if (!nvm_is_ready()) {
+ return STATUS_BUSY;
+ }
+
+ /* Writing configuration to the CTRLB register */
+ NVMCTRL->CTRLB.reg =
+ NVMCTRL_CTRLB_SLEEPPRM(NVM_SLEEP_POWER_MODE_WAKEONACCESS) |
+ ((false & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
+ NVMCTRL_CTRLB_RWS(NVMCTRL->CTRLB.bit.RWS) |
+ ((false & 0x01) << NVMCTRL_CTRLB_CACHEDIS_Pos) |
+ NVMCTRL_CTRLB_READMODE(NVM_CACHE_READMODE_NO_MISS_PENALTY);
+}
+
+/**
+ * \brief Function to start the application.
+ */
+static void start_application(void)
+{
+ /* Pointer to the Application Section */
+ void (*application_code_entry)(void);
+
+ /* Rebase the Stack Pointer */
+ __set_MSP(*(uint32_t *)APP_START_ADDR);
+
+ /* Rebase the vector table base address */
+ SCB->VTOR = ((uint32_t)APP_START_ADDR & SCB_VTOR_TBLOFF_Msk);
+
+ /* Load the Reset Handler address of the application */
+ application_code_entry = (void (*)(void))(unsigned *)(*(unsigned *)
+ (APP_START_ADDR + 4));
+
+ /* Jump to user Reset Handler in the application */
+ application_code_entry();
+}
+
+struct rtc_module rtc_instance;
+
+void rtc_overflow_callback(void)
+{
+ timeout+=2;//callback is called every 2ms
+ if(timeout > TIMOUT_PERIOD)
+ {
+ rtc_count_disable(&rtc_instance);
+ rtc_count_clear_overflow(&rtc_instance);
+ NVIC_ClearPendingIRQ(RTC_IRQn);
+ udc_stop();
+ cpu_irq_disable();
+ //SCB->AIRCR = ((0x05FA<<16)|0b100); //reset cpu
+ NVIC_SystemReset() ;
+ while(1)
+ {
+ //wait for WDT
+ }
+ }
+ if((timeout % 50) == 0)
+ {
+ port_pin_toggle_output_level(LED_L_PIN); // when the board is in bootloader mode the L Led blink
+ }
+}
+void configure_timeout()
+{
+ struct rtc_count_config config_rtc_count;
+ rtc_count_get_config_defaults(&config_rtc_count);
+ config_rtc_count.prescaler = RTC_COUNT_PRESCALER_DIV_1;
+ config_rtc_count.mode = RTC_COUNT_MODE_16BIT;
+ config_rtc_count.continuously_update = true;
+ rtc_count_init(&rtc_instance, RTC, &config_rtc_count);
+ rtc_count_enable(&rtc_instance);
rtc_count_register_callback(
+ &rtc_instance, rtc_overflow_callback, RTC_COUNT_CALLBACK_OVERFLOW);
+ rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_OVERFLOW);
rtc_count_set_period(&rtc_instance, 1);//1 ms per callback
NVIC_SetPriority(RTC_IRQn, 0);//RTC Top priority
+}
+
+
+void configure_port_pins(void)
+{
+ struct port_config config_port_pin;
+ port_get_config_defaults(&config_port_pin);
+ config_port_pin.direction = PORT_PIN_DIR_INPUT;
+ config_port_pin.input_pull = PORT_PIN_PULL_UP;
+ port_pin_set_config(BUTTON_0_PIN, &config_port_pin);
+}
+
+
+//1 =16 kb
+#define BOOTLOADER_SIZE 1
+
+void protect_boot_section()
+{
+ system_interrupt_enter_critical_section();
+ volatile uint32_t raw_fusebits[2];
+
+ /* Make sure the module is ready */
+ while (!nvm_is_ready()) {
+ };
+
+ /* Read the fuse settings in the user row, 64 bit */
+ ((uint16_t*)&raw_fusebits)[0] = (uint16_t)NVM_MEMORY[NVMCTRL_USER / 2];
+ ((uint16_t*)&raw_fusebits)[1] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 1];
+ ((uint16_t*)&raw_fusebits)[2] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 2];
+ ((uint16_t*)&raw_fusebits)[3] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 3];
+ if(((raw_fusebits[0] & NVMCTRL_FUSES_BOOTPROT_Msk)>> NVMCTRL_FUSES_BOOTPROT_Pos) != BOOTLOADER_SIZE)
+ {
+ /* Auxiliary space cannot be accessed if the security bit is set */
+ if (NVMCTRL->STATUS.reg & NVMCTRL_STATUS_SB) {
+ return;
+ }
+ /* Disable Cache */
+ uint32_t temp = NVMCTRL->CTRLB.reg;
+
+ NVMCTRL->CTRLB.reg = temp | NVMCTRL_CTRLB_CACHEDIS;
+
+ /* Clear error flags */
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+
+ /* Set address, command will be issued elsewhere */
+ NVMCTRL->ADDR.reg = NVMCTRL_AUX0_ADDRESS/2;
+
+ /* Erase the user page */
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY;
+
+ /* Wait for NVM command to complete */
+ while (!(NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY));
+
+ /* Clear error flags */
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+
+ /* Set address, command will be issued elsewhere */
+ NVMCTRL->ADDR.reg = NVMCTRL_AUX0_ADDRESS/2;
+
+ /* Erase the page buffer before buffering new data */
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY;
+
+ /* Wait for NVM command to complete */
+ while (!(NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY));
+
+ /* Clear error flags */
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+
+ /* Set address, command will be issued elsewhere */
+ NVMCTRL->ADDR.reg = NVMCTRL_AUX0_ADDRESS/2;
+ raw_fusebits[0] = ((raw_fusebits[0] ^ NVMCTRL_FUSES_BOOTPROT_Msk) | NVMCTRL_FUSES_BOOTPROT(BOOTLOADER_SIZE));
+ *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = raw_fusebits[0];
+ *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = raw_fusebits[1];
+
+ /* Write the user page */
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY;
+
+ /* Restore the settings */
+ NVMCTRL->CTRLB.reg = temp;
+
+
+ //nvm_execute_command(NVM_COMMAND_WRITE_AUX_ROW, NVMCTRL_USER, 0);
+ }
+ system_interrupt_leave_critical_section();
+}
+
+int main (void)
+{
+
+ /* Check if WDT is locked */
+
+
+ if (!(WDT->CTRL.reg & WDT_CTRL_ALWAYSON)) {
+ /* Disable the Watchdog module */
+ WDT->CTRL.reg &= ~WDT_CTRL_ENABLE;
+ }
+ if(!(PM->RCAUSE.reg & PM_RCAUSE_EXT) && !(PM->RCAUSE.reg & PM_RCAUSE_WDT) && (NVM_MEMORY[APP_START_ADDR / 2] != 0xFFFF)) //Power on reset or systemResetReq -> run main app
+ {
+ start_application();
+ }
+ //if reset by wdt or reset button, run bootloader
+ irq_initialize_vectors();
+ cpu_irq_enable();
+
+ system_init();
+
+ configure_timeout();
+ configure_nvm();
+
+ // start usart
+ configure_usart();
+ // Start USB stack to authorize VBus monitoring
+ udc_start();
+ NVIC_SetPriority(USB_IRQn, 1); //USB Should have lower priority than rtc
+
+ //check if boot-protection is on
+ //(edbg does not write to boot-section if this is protected
+ //(bootprot can be manually changed to 0x07 in the "fuses" tab of Atmel tudio to reprogram)
+
+ protect_boot_section(); //uncomment for release
+
+ // set board LED initial status
+
+ port_pin_set_output_level(LED_L_PIN,LED_L_INACTIVE);
+ port_pin_set_output_level(LED_TX_PIN,LED_TX_INACTIVE);
+ port_pin_set_output_level(LED_RX_PIN,LED_RX_INACTIVE);
+
+ while (1) {
+ get_message();//STK500v2
+ }
+}
+
+void main_cdc_config(uint8_t port,usb_cdc_line_coding_t *cfg)
+{
+ if(cfg[port].dwDTERate == 1200)
+ {
+ //do nothing
+ }
+}
\ No newline at end of file
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/main.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/main.h
new file mode 100755
index 0000000000000000000000000000000000000000..3335fc40303a6c1a41d80124f207d4a1d4ca11b9
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/main.h
@@ -0,0 +1,51 @@
+/**
+ * \file
+ *
+ * \brief Main functions
+ *
+ * Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+#include "usb_protocol_cdc.h"
+
+void main_cdc_config(uint8_t port,usb_cdc_line_coding_t *cfg);
+
+#endif // _MAIN_H_
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/stk500v2.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/stk500v2.h
new file mode 100755
index 0000000000000000000000000000000000000000..6e2f85e8c20ccb5babdec1337101dc84067be0c3
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/stk500v2.h
@@ -0,0 +1,403 @@
+/*---------- GNU PUBLIC LICENZE V3 ----------
+*
+* Copyright Arduino srl (c) 2015
+*
+* This file is part of Bootloader_D21.
+*
+* Bootloader_D21 is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License.
+*
+* bootloader_D21 is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with Bootloader_D21. If not, see <http://www.gnu.org/licenses/>.
+*
+*/
+
+
+#ifndef STK500V2_H_
+#define STK500V2_H_
+
+#include"command.h"
+#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR)
+#define APP_START_ADDR (0x4000)
+#define TIMOUT_PERIOD 8000
+volatile uint32_t timeout = 0;
+volatile uint32_t current_address = APP_START_ADDR;
+uint8_t GET_COMMAND_BYTE()
+{
+ port_pin_set_output_level(LED_RX_PIN,LED_RX_INACTIVE); // RX LED management
+
+ while(!(usart_instance.hw->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) && !udi_cdc_is_rx_ready())
+ {
+
+ }
+
+ port_pin_set_output_level(LED_RX_PIN,LED_RX_ACTIVE); // RX LED management
+ if(usart_instance.hw->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)
+ {
+ return usart_instance.hw->USART.DATA.reg;
+ }
+ return udi_cdc_multi_getc(0);
+}
+
+void SEND_RESPONSE(char response)
+{
+ //if (!udi_cdc_is_tx_ready()) {
+ // /* Fifo full */
+ // udi_cdc_signal_overrun();
+ // ui_com_overflow();//not implemented yet
+ //}
+
+ port_pin_set_output_level(LED_TX_PIN,LED_TX_INACTIVE); // TX LED management
+ //wait until usb or usart is ready
+ while(!(usart_instance.hw->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) && !udi_cdc_is_tx_ready())
+ {
+
+ }
+
+ port_pin_set_output_level(LED_TX_PIN,LED_TX_ACTIVE); // TX LED management
+ /*try to send over usart*/
+ if(usart_instance.hw->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)
+ {
+ usart_instance.hw->USART.DATA.reg = response;
+ /* Wait until data is sent */
+ /*problem: need to time out in case only USB is used, this will only be a problem for the first byte,
+ after one timeout, INTFLAG_DRE will not be set if USART is not used*/
+ for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+ if ((usart_instance.hw->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC))
+ break;
+
+ }
+ }
+ // Mod for Tian compatibility
+ else
+ {
+ udi_cdc_putc(response);
+ }
+ return;
+}
+
+void commit_page()
+{
+ /*if current row is not written fully, fill rest of row with zeros, on last write in page,
+ whole buffer is written (automatic writes are on)*/
+ if(current_address >= APP_START_ADDR)
+ {
+ while(current_address%NVMCTRL_ROW_SIZE != 0)
+ {
+ NVM_MEMORY[current_address/2] = 0xffff;
+ current_address += 2;
+ }
+ /*wait until write operation is done*/
+ while(!(NVMCTRL->INTFLAG.bit.READY))
+ {
+ ;
+ }
+ }
+}
+
+
+/* DEFINES FOR DEVICE, pull out to header later TODOTODOTODO*/
+//signature for mega2560
+#define DEVICE_SIGNATURE 0x1E9801
+#define CONF_PARAM_BUILD_NUMBER_LOW 1
+#define CONF_PARAM_BUILD_NUMBER_HIGH 2
+#define CONF_PARAM_HW_VER 3
+#define CONF_PARAM_SW_MAJOR 4
+#define CONF_PARAM_SW_MINOR 5
+
+
+void handle_message(void);
+
+/* based on
+http://www.atmel.com/images/doc2591.pdf
+AVR068: STK500 communication protocol
+*/
+#define MAX_MESSAGE_LENGTH 286
+
+typedef enum
+{
+ STATE_START,
+ STATE_GET_SEQUENCE_NUMBER,
+ STATE_GET_MESSAGE_SIZE_1,
+ STATE_GET_MESSAGE_SIZE_2,
+ STATE_GET_TOKEN,
+ STATE_GET_DATA,
+ STATE_GET_CHECKSUM,
+
+} stk500v2_state;
+
+uint8_t message[MAX_MESSAGE_LENGTH];
+uint16_t message_length = 0;
+uint8_t sequence_number = 0;
+
+uint8_t get_checksum(uint16_t current_byte_in_message, uint8_t *message_to_check)
+{
+ uint8_t checksum = 0;
+ for(uint16_t i = 0; i<current_byte_in_message; i++)
+ {
+ checksum ^= message_to_check[i];
+ }
+ return checksum;
+}
+
+void get_message()
+{
+ stk500v2_state current_state = STATE_START;
+ uint32_t current_byte_in_message = 0;
+ uint32_t bytes_in_data_read = 0;
+ bool building_message = true;
+ while(building_message)
+ {
+ uint8_t received_char = GET_COMMAND_BYTE();
+ message[current_byte_in_message] = received_char;
+ current_byte_in_message++;
+ switch(current_state)
+ {
+ case STATE_START:
+ if(received_char == MESSAGE_START)
+ {
+ current_state = STATE_GET_SEQUENCE_NUMBER;
+ }
+ else
+ {
+ current_state = STATE_START;
+ current_byte_in_message = 0;
+ }
+ break;
+ case STATE_GET_SEQUENCE_NUMBER:
+ sequence_number = received_char; //ignore sequence number, always accept
+ current_state = STATE_GET_MESSAGE_SIZE_1;
+ break;
+ case STATE_GET_MESSAGE_SIZE_1:
+ message_length = (received_char << 8)&0xff00;
+ current_state = STATE_GET_MESSAGE_SIZE_2;
+ break;
+ case STATE_GET_MESSAGE_SIZE_2:
+ message_length |= received_char;
+ current_state = STATE_GET_TOKEN;
+ break;
+ case STATE_GET_TOKEN:
+ if(received_char == TOKEN)
+ {
+ current_state = STATE_GET_DATA;
+ bytes_in_data_read = 0;
+ }
+ else
+ {
+ current_state = STATE_START;
+ current_byte_in_message = 0;
+ }
+ break;
+ case STATE_GET_DATA:
+ bytes_in_data_read++;
+ if(bytes_in_data_read == message_length)
+ {
+ current_state = STATE_GET_CHECKSUM;
+ }
+ break;
+ case STATE_GET_CHECKSUM:
+ if(get_checksum(current_byte_in_message-1, message) == received_char) //ignore last byte (should not include checksum in checksum)
+ {
+ building_message = false;
+ }
+ else
+ {
+ current_state = STATE_START;
+ current_byte_in_message = 0;
+ }
+ break;
+ }
+ }
+ timeout = 0;
+ handle_message();
+
+}
+
+void handle_message()
+{
+ uint8_t return_message[MAX_MESSAGE_LENGTH];
+ uint8_t *message_body = message + 5;
+ uint16_t return_message_length = 0;
+ return_message[0] = message_body[0];
+ uint16_t bytes_to_read_or_write = 0;
+ switch(return_message[0])
+ {
+ case CMD_SIGN_ON:
+ return_message_length = 11;
+ return_message[1] = STATUS_CMD_OK;
+ return_message[2] = 8;
+ return_message[3] = 'A';
+ return_message[4] = 'V';
+ return_message[5] = 'R';
+ return_message[6] = 'I';
+ return_message[7] = 'S';
+ return_message[8] = 'P';
+ return_message[9] = '_';
+ return_message[10] = '2';
+ break;
+ case CMD_READ_SIGNATURE_ISP:
+ return_message_length = 4;
+ uint8_t signature_index = message_body[4];
+ return_message[1] = STATUS_CMD_OK;
+ return_message[2] = (DEVICE_SIGNATURE>>((2-signature_index)*8))&0xFF;
+ return_message[3] = STATUS_CMD_OK;
+ break;
+ case CMD_GET_PARAMETER:
+ return_message_length = 3;
+ uint8_t parameter = message_body[1];
+ return_message[1] = STATUS_CMD_OK;
+ switch(parameter)
+ {
+ case PARAM_BUILD_NUMBER_LOW:
+ return_message[2] = CONF_PARAM_BUILD_NUMBER_LOW;
+ break;
+ case PARAM_BUILD_NUMBER_HIGH:
+ return_message[2] = CONF_PARAM_BUILD_NUMBER_HIGH;
+ break;
+ case PARAM_HW_VER:
+ return_message[2] = CONF_PARAM_HW_VER;
+ break;
+ case PARAM_SW_MAJOR:
+ return_message[2] = CONF_PARAM_SW_MAJOR;
+ break;
+ case PARAM_SW_MINOR:
+ return_message[2] = CONF_PARAM_SW_MINOR;
+ break;
+ default:
+ return_message[2] = 0;
+ break;
+ }
+ break;
+
+ case CMD_ENTER_PROGMODE_ISP: //Ignore this one for now
+ return_message_length = 2;
+ return_message[1] = STATUS_CMD_OK;
+ break;
+ case CMD_LEAVE_PROGMODE_ISP:
+ return_message_length = 2;
+ return_message[1] = STATUS_CMD_OK;
+ timeout = (TIMOUT_PERIOD - 500);//reset and enter main app after 500 ms
+ break;
+ case CMD_SET_PARAMETER: //Ignore this one for now
+ return_message_length = 2;
+ return_message[1] = STATUS_CMD_OK;
+ break;
+ case CMD_LOAD_ADDRESS:
+ current_address = (((message_body[1]<<24) | (message_body[2]<<16) | (message_body[3]<<8) | (message_body[4]))<<1);//shift left 1 to ignore msb and convert from word to byte
+// current_address = current_address + APP_START_ADDR;
+ return_message_length = 2;
+ return_message[1] = STATUS_CMD_OK;
+ break;
+ case CMD_SPI_MULTI: //only partially implemented
+ switch(message_body[4])
+ {
+ case 0x30:
+ return_message_length = 7;
+ return_message[1] = STATUS_CMD_OK;
+ return_message[2] = 0;
+ return_message[3] = message_body[4];
+ return_message[4] = 0;
+ return_message[5] = (DEVICE_SIGNATURE>>((2-message_body[6])*8))&0xFF;;
+ return_message[6] = STATUS_CMD_OK;
+ break;
+ default:
+ return_message_length = 7;
+ return_message[1] = STATUS_CMD_OK;
+ return_message[2] = 0;
+ return_message[3] = message_body[4];
+ return_message[4] = 0;
+ return_message[5] = 0;
+ return_message[6] = STATUS_CMD_OK;
+ break;
+ }
+
+ break;
+ case CMD_CHIP_ERASE_ISP:
+ for (uint32_t current_flash_address = APP_START_ADDR; current_flash_address < NVMCTRL_FLASH_SIZE; current_flash_address += NVMCTRL_ROW_SIZE)
+ {
+ enum status_code error_code;
+ do
+ {
+ error_code = nvm_is_ready();
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+
+ /* Set address and command */
+ NVMCTRL->ADDR.reg = (uintptr_t)&NVM_MEMORY[current_flash_address / 4];
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;
+ } while (error_code == STATUS_BUSY);
+ }
+ return_message_length = 2;
+ return_message[1] = STATUS_CMD_OK;
+ break;
+ case CMD_PROGRAM_FLASH_ISP:
+
+ bytes_to_read_or_write = (message_body[1]<<8) + message_body[2];
+ if(current_address >= APP_START_ADDR)
+ {
+ uint32_t i;
+ for(i = 0; i<bytes_to_read_or_write; i+=2)
+ {
+ NVM_MEMORY[((current_address+i)/2)] = ((message_body[10+i])+(message_body[10+i+1]<<8));
+ }
+ //nvm_write_buffer(current_address, message_body+10, bytes_to_read_or_write);
+ }
+ current_address += bytes_to_read_or_write;
+ commit_page();
+ return_message_length = 2;
+ return_message[1] = STATUS_CMD_OK;
+ break;
+ case CMD_READ_FLASH_ISP:
+ bytes_to_read_or_write = (message_body[1]<<8) + message_body[2];
+ return_message_length = bytes_to_read_or_write + 3;
+ return_message[1] = STATUS_CMD_OK;
+ if(current_address >= APP_START_ADDR)
+ {
+ uint32_t i;
+ for(i = 0; i<bytes_to_read_or_write; i+=2)
+ {
+ return_message[2+i] = NVM_MEMORY[((current_address+i)/2)]&0xff;
+ return_message[2+i+1] = NVM_MEMORY[((current_address+i)/2)]>>8;
+ }
+ //nvm_read_buffer(current_address, return_message+2, bytes_to_read_or_write);
+ }
+ else
+ {
+ for(uint32_t i = 0; i<(message_body[1]<<8) + message_body[2]; i++)
+ {
+ return_message[i+2] = 0xFFFF;
+ }
+ }
+ current_address += bytes_to_read_or_write;
+ return_message[return_message_length-1] = STATUS_CMD_OK;
+ break;
+ }
+ //send message back
+ uint8_t checksum = 0;
+ checksum ^= MESSAGE_START;
+ SEND_RESPONSE(MESSAGE_START);
+ checksum ^= sequence_number;
+ SEND_RESPONSE(sequence_number);
+ checksum ^= (return_message_length>>8)&0xFF;
+ SEND_RESPONSE((return_message_length>>8)&0xFF);
+ checksum ^= return_message_length&0xFF;
+ SEND_RESPONSE((return_message_length)&0xFF);
+ checksum ^= TOKEN;
+ SEND_RESPONSE(TOKEN);
+ for(uint16_t i = 0; i< return_message_length; i++)
+ {
+ SEND_RESPONSE(return_message[i]);
+ }
+ uint8_t body_checksum = get_checksum(return_message_length, return_message);
+ checksum ^= body_checksum;
+ SEND_RESPONSE(checksum);
+}
+
+
+
+#endif /* STK500V2_H_ */
\ No newline at end of file
diff --git a/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/usart_setup.h b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/usart_setup.h
new file mode 100755
index 0000000000000000000000000000000000000000..3fa2968bf6831841a5411558725f8e56729258e7
--- /dev/null
+++ b/bootloaders/sofia/Bootloader_D21_Sofia_V2.1/src/usart_setup.h
@@ -0,0 +1,46 @@
+
+
+
+#ifndef USART_SETUP_H_
+#define USART_SETUP_H_
+/** \name Embedded debugger SOFIA SERCOM interface definitions
+* @{
+*/
+#define EDBG_SOFIA_MODULE SERCOM5
+#define EDBG_SOFIA_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3//USART_RX_3_TX_2_XCK_3
+#define EDBG_SOFIA_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
+#define EDBG_SOFIA_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
+#define EDBG_SOFIA_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SOFIA_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SOFIA_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
+#define EDBG_SOFIA_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
+/** @} */
+
+
+
+
+
+
+struct usart_module usart_instance;
+void configure_usart(void)
+{
+ struct usart_config config_usart;
+ usart_get_config_defaults(&config_usart);
+ //! [setup_change_config]
+ config_usart.baudrate = 57600;
+ config_usart.mux_setting = EDBG_SOFIA_SERCOM_MUX_SETTING;
+ config_usart.pinmux_pad0 = EDBG_SOFIA_SERCOM_PINMUX_PAD0;
+ config_usart.pinmux_pad1 = EDBG_SOFIA_SERCOM_PINMUX_PAD1;
+ config_usart.pinmux_pad2 = EDBG_SOFIA_SERCOM_PINMUX_PAD2;
+ config_usart.pinmux_pad3 = EDBG_SOFIA_SERCOM_PINMUX_PAD3;
+ //config_usart.start_frame_detection_enable = true;
+ //! [setup_change_config]
+ while (usart_init(&usart_instance, SERCOM5, &config_usart) != STATUS_OK) {
+
+ }
+ usart_enable(&usart_instance);
+}
+
+#endif /* USART_SETUP_H_ */
+
+
diff --git a/bootloaders/sofia/Sofia_Tian_151118.hex b/bootloaders/sofia/Sofia_Tian_151118.hex
new file mode 100644
index 0000000000000000000000000000000000000000..eacd8943a85addffa0f9b7a58b8a4af5b325a3c6
--- /dev/null
+++ b/bootloaders/sofia/Sofia_Tian_151118.hex
@@ -0,0 +1,970 @@
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+:1000100000000000000000000000000000000000E0
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