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Commit 4d650ce9 authored by Jonathan BAUDIN's avatar Jonathan BAUDIN
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Merge branch 'zero' of github.com:aethaniel/ArduinoZero into zero

parents 82074eed 61f33c32
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with 20 additions and 82 deletions
cores/arduino/startup.c
+ 20
− 82
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......@@ -188,7 +188,7 @@ void SystemInit( void )
/* Turn on the digital interface clock */
PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
/*
/* ----------------------------------------------------------------------------------------------
* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
*/
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x6u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
......@@ -211,7 +211,7 @@ void SystemInit( void )
/* Wait for reset to complete */
}
/*
/* ----------------------------------------------------------------------------------------------
* 2) Put XOSC32K as source of Generic Clock Generator 1
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
......@@ -225,7 +225,7 @@ void SystemInit( void )
*((uint8_t *) &GCLK->GENCTRL) = GENERIC_CLOCK_GENERATOR_XOSC32K ;
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1
GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
GCLK_GENCTRL_OE |
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
......@@ -233,11 +233,11 @@ void SystemInit( void )
/* Wait for synchronization */
}
/*
/* ----------------------------------------------------------------------------------------------
* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
*/
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock 0 (GCLKMAIN)
GCLK_CLKCTRL_GEN_GCLK1_Val | // Generic Clock Generator 1 is source
GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
GCLK_CLKCTRL_CLKEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
......@@ -245,9 +245,9 @@ void SystemInit( void )
/* Wait for synchronization */
}
/*
* 4) Enable DFLL48M clock
*/
/* ----------------------------------------------------------------------------------------------
* 4) Enable DFLL48M clock
*/
/* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
......@@ -259,15 +259,9 @@ void SystemInit( void )
/* Wait for synchronization */
}
#if 0
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference
#else
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 10 ) | // Coarse step is 31, half of the max value
SYSCTRL_DFLLMUL_FSTEP( 10 ) | // Fine step is 511, half of the max value
SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference
#endif
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
......@@ -275,14 +269,9 @@ void SystemInit( void )
}
/* Write full configuration to DFLL control register */
#if 0
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
SYSCTRL_DFLLCTRL_QLDIS | /* Disable Quick lock */
SYSCTRL_DFLLCTRL_CCDIS ; /* Disable Chill Cycle */
#else
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
SYSCTRL_DFLLCTRL_WAITLOCK |
SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
#endif
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
......@@ -292,20 +281,18 @@ void SystemInit( void )
/* Enable the DFLL */
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
{
/* Wait for locks flags */
}
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
#if 0
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
{
/* Wait for locks flags */
}
#endif
/*
/* ----------------------------------------------------------------------------------------------
* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
......@@ -318,7 +305,7 @@ void SystemInit( void )
/* Write Generic Clock Generator 0 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
GCLK_GENCTRL_OE |
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
GCLK_GENCTRL_GENEN ;
......@@ -327,40 +314,27 @@ void SystemInit( void )
/* Wait for synchronization */
}
#if 1
/*
/* ----------------------------------------------------------------------------------------------
* 6) Modify PRESCaler value of OSC8M to have 8MHz
*/
SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ;
SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
/*
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) == 0 )
{
/* Wait for synchronization
}
*/
/*
/* ----------------------------------------------------------------------------------------------
* 7) Put OSC8M as source for Generic Clock Generator 3
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
//while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
//{
///* Wait for synchronization */
//}
/* Write Generic Clock Generator 3 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
#endif
/*
* Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
......@@ -426,39 +400,3 @@ void Dummy_Handler( void )
{
}
}
#if 0
GCLK->GENDIV.reg = GCLK_GENDIV_ID(O) | GCLK_GENDIV_DIV(O); // No div since RC8M is at 1MHz by default
while (GCLK->STATUS.bit.SYNCBUSY);
GCLK->GENCTRL.reg = ( GCLK_GENCTRL_ID(O) | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC8M_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_IDC | GCLK_GENCTRL_OE ) & (~GCLK_GENCTRL_OOV);
while (GCLK->STATUS.bit.SYNCBUSY);
//-------------------------- EXAMPLE -------------------------------------------
#define DFLLREF32K_GENERATOR_GCLK_ID 2
void init_dfll_on_xosc32k(void)
{
// Setup generator on XOSC32K
gclk_gen_setup(DFLLREF32K_GENERATOR_GCLK_ID,GCLK_SOURCE_XOSC32K,1);
gclk_gen_output_conf(DFLLREF32K_GENERATOR_GCLK_ID,false,0);
gclk_setup(SYSCTRL_GCLK_ID_DFLL48,DFLLREF32K_GENERATOR_GCLK_ID,0);
//Use DFLL @ 48MHz
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0; // Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905
while((SYSCTRL->PCLKSR.reg&SYSCTRL_PCLKSR_DFLLRDY)==0);
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_MUL(1465)|SYSCTRL_DFLLMUL_FSTEP(10)|SYSCTRL_DFLLMUL_CSTEP(10);
while((SYSCTRL->PCLKSR.reg&SYSCTRL_PCLKSR_DFLLRDY)==0);
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_CCDIS|SYSCTRL_DFLLCTRL_QLDIS|SYSCTRL_DFLLCTRL_MODE;
while((SYSCTRL->PCLKSR.reg&SYSCTRL_PCLKSR_DFLLRDY)==0);
//SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE | SYSCTRL_DFLLCTRL_RUNSTDBY;
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
while((SYSCTRL->PCLKSR.reg&SYSCTRL_PCLKSR_DFLLRDY)==0);
// Wait for locks flags .
while((SYSCTRL->PCLKSR.reg&SYSCTRL_PCLKSR_DFLLLCKC)==0 || (SYSCTRL->PCLKSR.reg&SYSCTRL_PCLKSR_DFLLLCKF)==0);
}
#endif
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