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Commit 6538f895 authored by Cristian Maglie's avatar Cristian Maglie
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NMI interrupts are now correctly ignored by attach/detachInterrupt

Fixes #30
parent cc5948b2
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......@@ -76,6 +76,8 @@ void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode)
if (digitalPinToInterrupt(pin) == NOT_AN_INTERRUPT)
return;
if (digitalPinToInterrupt(pin) == EXTERNAL_INT_NMI)
return;
if (!enabled) {
__initialize();
......@@ -89,91 +91,53 @@ void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode)
callbacksInt[digitalPinToInterrupt(pin)]._ulPin = pin;
callbacksInt[digitalPinToInterrupt(pin)]._callback = callback;
// Check if normal interrupt or NMI
if (pin != 2)
{
// Look for right CONFIG register to be addressed
if (digitalPinToInterrupt(pin) > EXTERNAL_INT_7) {
config = 1;
} else {
config = 0;
}
// Configure the interrupt mode
pos = ((digitalPinToInterrupt(pin) - (8 * config)) << 2);
switch (mode)
{
case LOW:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_LOW_Val << pos;
break;
case HIGH:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_HIGH_Val << pos;
break;
case CHANGE:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_BOTH_Val << pos;
break;
case FALLING:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_FALL_Val << pos;
break;
case RISING:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_RISE_Val << pos;
break;
}
// Enable the interrupt
EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << digitalPinToInterrupt(pin));
// Look for right CONFIG register to be addressed
if (digitalPinToInterrupt(pin) > EXTERNAL_INT_7) {
config = 1;
} else {
config = 0;
}
else // Handles NMI on pin 2
// Configure the interrupt mode
pos = ((digitalPinToInterrupt(pin) - (8 * config)) << 2);
switch (mode)
{
// Configure the interrupt mode
switch (mode)
{
case LOW:
EIC->NMICTRL.reg = EIC_NMICTRL_NMISENSE_LOW;
break;
case LOW:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_LOW_Val << pos;
break;
case HIGH:
EIC->NMICTRL.reg = EIC_NMICTRL_NMISENSE_HIGH;
break;
case HIGH:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_HIGH_Val << pos;
break;
case CHANGE:
EIC->NMICTRL.reg = EIC_NMICTRL_NMISENSE_BOTH;
break;
case CHANGE:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_BOTH_Val << pos;
break;
case FALLING:
EIC->NMICTRL.reg = EIC_NMICTRL_NMISENSE_FALL;
break;
case FALLING:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_FALL_Val << pos;
break;
case RISING:
EIC->NMICTRL.reg= EIC_NMICTRL_NMISENSE_RISE;
break;
}
case RISING:
EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_RISE_Val << pos;
break;
}
// Enable the interrupt
EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << digitalPinToInterrupt(pin));
}
/*
* \brief Turns off the given interrupt.
*/
void detachInterrupt( uint32_t ulPin )
void detachInterrupt(uint32_t pin)
{
/*
// Retrieve pin information
Pio *pio = g_APinDescription[pin].pPort;
uint32_t mask = g_APinDescription[pin].ulPin;
// Disable interrupt
pio->PIO_IDR = mask;
*/
if ( digitalPinToInterrupt( ulPin ) == NOT_AN_INTERRUPT )
{
return ;
}
if (digitalPinToInterrupt(pin) == NOT_AN_INTERRUPT)
return;
if (digitalPinToInterrupt(pin) == EXTERNAL_INT_NMI)
return;
EIC->INTENCLR.reg = EIC_INTENCLR_EXTINT( 1 << digitalPinToInterrupt( ulPin ) ) ;
EIC->INTENCLR.reg = EIC_INTENCLR_EXTINT(1 << digitalPinToInterrupt(pin));
}
/*
......@@ -200,21 +164,6 @@ void EIC_Handler( void )
}
}
/*
* External Non-Maskable Interrupt Controller NVIC Interrupt Handler
*/
void NMI_Handler( void )
{
// Call the callback function if assigned
if ( callbacksInt[EXTERNAL_INT_NMI]._callback != NULL )
{
callbacksInt[EXTERNAL_INT_NMI]._callback() ;
}
// Clear the interrupt
EIC->NMIFLAG.reg = EIC_NMIFLAG_NMI ;
}
#ifdef __cplusplus
}
#endif
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