More accurate approximation for multiplication factor of PLL to make 48Mhz.

Fix #223

CHANGELOG

+SAMD CORE 1.6.17
+
+* More accurate approximation for multiplication factor of PLL to make 48Mhz. Thanks @joverbee
+
 SAMD CORE 1.6.16 2017.08.23
 
 * Is now possible to use PWM on D7 (though it can't be used with PWM on D12 at the same time). Thanks @Adminius

cores/arduino/startup.c

@@ -148,7 +148,7 @@ void SystemInit( void )
 
   SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
                          SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
-                         SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference
+                         SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference
 
   while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
   {