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Created with Raphaël 2.2.029Aug2824171431Jul11427Jun2621May1020Mar12524Feb232014131Jan258220Dec181715121130Nov29252413919Oct11630Sep2914854123Aug12Jul11764327Jun24232122May18228Apr27242221191554331Mar2362128Feb15987230Jan2724323Dec2019161514131276228Nov2523181726Oct121110330Sep282726221514231Aug29241125Jul21201918128730Jun29271776330May29272019921Apr2019654231Mar301243226Feb231918161511329Jan262221201918151312654328Dec2517161432130Nov262423201817161312111064331Oct302622Using __attribute__((packed)) instead of pragmasFixed uninitialized use of variableUSBDevice: fixed some minor warningsAdd weak hook to trigger companion chip reinitializationAdd disableFpgaClock functionFix compilation if USBCON is not defined[WORKAROUND] add 10uS of delay befor handling Setup packetPorting CDC to PluggableUSB[FIXME] Reenable full EP_SIZE USB sendAllow complete override of USB SerialNumberAllow removing CDC_ENABLED with define switch[VIDOR] Let the library call enableFpgaClockVidor: update bootloader binaries[VIDORBL] Add timeouts to i2c operations[VIDOR][PMIC] Check return value of Wire.startTransmission[TEST][DANGER]Add timeout to startTransmissionWIREAdd check for arbitration in I2C master readMake CDC/UART interface configurable from Makefile[VIDORBL] port to IRQ architectureRestore flash speedup via signatureMass rename old vidor2000Update openocd to 0.10.0-arduino7Fix runtime paths for new toolsDon't reverse nibbles in jtagReadAdd full 2M support to fpga flashMove ACK pin for complete passthroughConfigure PMIC before clocking the fpgaRename MKRVidorTEMP: set BQ power settings from user sketchTEMP: add bossacI upload tool for Vidor[PROPOSAL] SPI: add getters for private fieldsCache last used SPISettingsAllow analogWrite for extended pinsFix fpga_bitstream_section being included in all sketchesFix PINS_COUNTWiringExtended: silence warnings[VIDORBL] add descriptor and configurable offsetBL: add flashing routines[VidorBL] fix all jtag ifdefsTEST: start porting jtag to bootloader