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Arduino Core for SAMD21 CPU
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josc941e
Arduino Core for SAMD21 CPU
Commits
3e2f4e77
Commit
3e2f4e77
authored
10 years ago
by
Thibaut VIARD
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Cosmetic polishing on clock setup code
parent
61f33c32
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cores/arduino/startup.c
+6
-7
6 additions, 7 deletions
cores/arduino/startup.c
with
6 additions
and
7 deletions
cores/arduino/startup.c
+
6
−
7
View file @
3e2f4e77
...
...
@@ -222,7 +222,6 @@ void SystemInit( void )
}
/* Write Generic Clock Generator 1 configuration */
*
((
uint8_t
*
)
&
GCLK
->
GENCTRL
)
=
GENERIC_CLOCK_GENERATOR_XOSC32K
;
GCLK
->
GENCTRL
.
reg
=
GCLK_GENCTRL_ID
(
GENERIC_CLOCK_GENERATOR_XOSC32K
)
|
// Generic Clock Generator 1
GCLK_GENCTRL_SRC_XOSC32K
|
// Selected source is External 32KHz Oscillator
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
...
...
@@ -236,7 +235,7 @@ void SystemInit( void )
/* ----------------------------------------------------------------------------------------------
* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
*/
GCLK
->
CLKCTRL
.
reg
=
GCLK_CLKCTRL_ID
(
GENERIC_CLOCK_
GENERATOR_MAIN
)
|
// Generic Clock
0 (GCLKMAIN)
GCLK
->
CLKCTRL
.
reg
=
GCLK_CLKCTRL_ID
(
GENERIC_CLOCK_
MULTIPLEXER_DFLL48M
)
|
// Generic Clock
Multiplexer 0
GCLK_CLKCTRL_GEN_GCLK1
|
// Generic Clock Generator 1 is source
GCLK_CLKCTRL_CLKEN
;
...
...
@@ -281,11 +280,11 @@ void SystemInit( void )
/* Enable the DFLL */
SYSCTRL
->
DFLLCTRL
.
reg
|=
SYSCTRL_DFLLCTRL_ENABLE
;
while
(
(
SYSCTRL
->
PCLKSR
.
reg
&
SYSCTRL_PCLKSR_DFLLLCKC
)
==
0
||
(
SYSCTRL
->
PCLKSR
.
reg
&
SYSCTRL_PCLKSR_DFLLLCKF
)
==
0
)
{
/* Wait for locks flags */
}
while
(
(
SYSCTRL
->
PCLKSR
.
reg
&
SYSCTRL_PCLKSR_DFLLLCKC
)
==
0
||
(
SYSCTRL
->
PCLKSR
.
reg
&
SYSCTRL_PCLKSR_DFLLLCKF
)
==
0
)
{
/* Wait for locks flags */
}
while
(
(
SYSCTRL
->
PCLKSR
.
reg
&
SYSCTRL_PCLKSR_DFLLRDY
)
==
0
)
{
...
...
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