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Commit 3e2f4e77 authored by Thibaut VIARD's avatar Thibaut VIARD
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Cosmetic polishing on clock setup code

parent 61f33c32
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...@@ -222,7 +222,6 @@ void SystemInit( void ) ...@@ -222,7 +222,6 @@ void SystemInit( void )
} }
/* Write Generic Clock Generator 1 configuration */ /* Write Generic Clock Generator 1 configuration */
*((uint8_t *) &GCLK->GENCTRL) = GENERIC_CLOCK_GENERATOR_XOSC32K ;
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1
GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
// GCLK_GENCTRL_OE | // Output clock to a pin for tests // GCLK_GENCTRL_OE | // Output clock to a pin for tests
...@@ -236,7 +235,7 @@ void SystemInit( void ) ...@@ -236,7 +235,7 @@ void SystemInit( void )
/* ---------------------------------------------------------------------------------------------- /* ----------------------------------------------------------------------------------------------
* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference) * 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
*/ */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock 0 (GCLKMAIN) GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
GCLK_CLKCTRL_CLKEN ; GCLK_CLKCTRL_CLKEN ;
...@@ -281,11 +280,11 @@ void SystemInit( void ) ...@@ -281,11 +280,11 @@ void SystemInit( void )
/* Enable the DFLL */ /* Enable the DFLL */
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ; SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 || while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 ) (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
{ {
/* Wait for locks flags */ /* Wait for locks flags */
} }
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 ) while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{ {
......
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